Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217284/?format=api
{ "id": 2217284, "url": "http://patchwork.ozlabs.org/api/patches/2217284/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-2-james.hilliard1@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327200932.2016910-2-james.hilliard1@gmail.com>", "list_archive_url": null, "date": "2026-03-27T20:09:13", "name": "[v4,2/5] sunxi: h616: move PHY init tables into timing files", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b53dd0d61e40d374872f24506d3a59ad0b4ff635", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": { "id": 114289, "url": "http://patchwork.ozlabs.org/api/users/114289/?format=api", "username": "apritzel", "first_name": "Andre", "last_name": "Przywara", "email": "andre.przywara@arm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-2-james.hilliard1@gmail.com/mbox/", "series": [ { "id": 497825, "url": "http://patchwork.ozlabs.org/api/series/497825/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497825", "date": "2026-03-27T20:09:12", "name": "[v4,1/5] sunxi: h616: make ns_to_t() use the DRAM clock", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497825/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217284/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217284/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=B+/FsObM;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.b=\"B+/FsObM\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=james.hilliard1@gmail.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fjBZz2Gkjz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 07:10:19 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id C0E7C83FAF;\n\tFri, 27 Mar 2026 21:10:03 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 3830983FA7; Fri, 27 Mar 2026 21:10:01 +0100 (CET)", "from mail-ot1-x32d.google.com (mail-ot1-x32d.google.com\n [IPv6:2607:f8b0:4864:20::32d])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id EC7958394E\n for <u-boot@lists.denx.de>; Fri, 27 Mar 2026 21:09:58 +0100 (CET)", "by mail-ot1-x32d.google.com with SMTP id\n 46e09a7af769-7d74dbfe84cso1708901a34.1\n for <u-boot@lists.denx.de>; Fri, 27 Mar 2026 13:09:58 -0700 (PDT)", "from james-x399.localdomain (71-33-142-50.hlrn.qwest.net.\n [71.33.142.50]) by smtp.gmail.com with ESMTPSA id\n 46e09a7af769-7da0a7b5b41sm166102a34.15.2026.03.27.13.09.56\n (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256);\n Fri, 27 Mar 2026 13:09:57 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,FORGED_GMAIL_RCVD,\n FREEMAIL_ENVFROM_END_DIGIT,FREEMAIL_FROM,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=no autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=gmail.com; s=20251104; t=1774642197; x=1775246997; darn=lists.denx.de;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:from:to:cc:subject:date\n :message-id:reply-to;\n bh=t1PzgCuunsNOT2GKEFj0EWNMYKiUyLhbM9iVZXmRt4Q=;\n b=B+/FsObMQ87iIYFreNYC0zYd1z/2guYh6rDS4vKWT52ZFFlLYD/TkKkuo70OEynFJ7\n 56fOYmUn1p3NJSk5du6+zOrvh92LTifzGnAhMRg67+GYKz3isxGN3YKTz2Gz1ilVK13R\n OsktppFoot3f8/nzK9390Ha5i3kvXHo6hhDm6y/9hfkUqq28L9tR9wba129jlE/JQofM\n QATVmFYXwv7NiSdHIumR+Sd6Wv6VCbWlozhSCl1I5sS3KESrxorpd1p20ciXWeidjh0O\n m+m4Fx5lt0iJ1D4pcv+og3hyE797PkXNJi1n79mJqZMgudhaPthnPLwIBRddd1gfxIzc\n vaPQ==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n d=1e100.net; s=20251104; t=1774642197; x=1775246997;\n h=content-transfer-encoding:mime-version:references:in-reply-to\n :message-id:date:subject:cc:to:from:x-gm-gg:x-gm-message-state:from\n :to:cc:subject:date:message-id:reply-to;\n bh=t1PzgCuunsNOT2GKEFj0EWNMYKiUyLhbM9iVZXmRt4Q=;\n b=MMAqexyppKTl3XAYEQaI9TnL2kpdYtEibW45Lm1WrQr8ZARrVY/kacjOdtCEjkcR0v\n OjiI80w4fd4nWR/dL9MB/CGpKPLyHS/8342ROUlLk6vLEGbkmsVNfyNh1RhMNZ42RL2P\n +Kg9v59Am+ETvkpmWCu996CpnrHWMtdpLq283SsoV8yBFaTse9CyFWpfePuNl+SclyMk\n EOIWtH6xiJQr8JfQdxIhV3yiLnjc8cRXhjiP47qxoIVA+p89JO8+8M77APDkCWFfovdq\n XVroeyC+Lu582j5AI93TR/AT3EDVFN5eTVh05gFYdajHZm863ekNjmTFgHgUeDtt4YFf\n 4VNg==", "X-Gm-Message-State": "AOJu0Ywg8Dyst9xTZ4A7mnOQ0xtHjcSa9yk9BKWbi+YVCi8cwtyzXheb\n njK4ZYEskNcbWwaFoM5c9YHdKIw+bVJsNmJCPeMAlTReRdR9hRNFsNtR+vUVfw==", "X-Gm-Gg": "ATEYQzwDmNKan5yax8UlJSf963St0uJ52lRK6GLi17tbce0xiX+XN3pqr2YGB5someL\n /HenKaay5UNGzkMea1VibMJp9oES9Ky/+kgGvU6hitia8XatoyhUn1SJbLQBmSMK9rekkxziXnt\n xPa0myBOJPJTYGgqWbpxFH1dW2TqNoLqZAKfunov5nrOQWadXzfnB9WLoZirTtq4WvG+YxC08+z\n uGSdTFCst82+PXB8sn5ekrvXiXAIirboCU6zKUK+yhu5QecqT4lOjDNlDDul4TZ4iJnkI4UqqqK\n kgkERID7rp7oP8vj0eZ3VwyW3DI/bf9/zYGufdSo8XUPS1sPpf34qTMDV6Uwah2HatwoBocGYKQ\n dHesy1j3HW8vr508Q5Euk9Ai9227VnwQ2UV/xAEu7ds4rW02KEZgt5mv4vPUbxpKys/Okr7hqk8\n uy56h+8gLhCoQis9KZk9PJK+40iYrLki2KIKIXuS99M2ek+iwNw1gfh2n2JjhVnosLRa56tGPNq\n oPAFoRhJxSd8F74YDDfMY71Td7Eg5Cb0fCrnGtUzp97rO09BHpKZW2x/g14", "X-Received": "by 2002:a05:6830:710a:b0:7d9:b314:1452 with SMTP id\n 46e09a7af769-7d9fad15978mr2161235a34.7.1774642197416;\n Fri, 27 Mar 2026 13:09:57 -0700 (PDT)", "From": "James Hilliard <james.hilliard1@gmail.com>", "To": "u-boot@lists.denx.de", "Cc": "James Hilliard <james.hilliard1@gmail.com>,\n Andre Przywara <andre.przywara@arm.com>, Tom Rini <trini@konsulko.com>,\n Jernej Skrabec <jernej.skrabec@gmail.com>,\n Paul Kocialkowski <contact@paulk.fr>,\n \"Kory Maincent (TI.com)\" <kory.maincent@bootlin.com>,\n Mikhail Kalashnikov <iuncuim@gmail.com>,\n Richard Genoud <richard.genoud@bootlin.com>,\n Cody Eksal <masterr3c0rd@epochal.quest>,\n Samuel Holland <samuel@sholland.org>", "Subject": "[PATCH v4 2/5] sunxi: h616: move PHY init tables into timing files", "Date": "Fri, 27 Mar 2026 14:09:13 -0600", "Message-ID": "<20260327200932.2016910-2-james.hilliard1@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260327200932.2016910-1-james.hilliard1@gmail.com>", "References": "<20260327200932.2016910-1-james.hilliard1@gmail.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Store the compile-time-selected PHY initialisation data alongside\neach H616 timing implementation instead of in the common H616\nDRAM code.\n\nThe common code still consumes a single phy_init pointer, so this\nonly moves the DRAM-type-specific data without changing the\nselection model.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\n .../include/asm/arch-sunxi/dram_sun50i_h616.h | 3 ++\n arch/arm/mach-sunxi/dram_sun50i_h616.c | 41 +------------------\n .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 18 ++++++++\n .../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 18 ++++++++\n .../dram_timings/h616_lpddr4_2133.c | 18 ++++++++\n 5 files changed, 58 insertions(+), 40 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\nindex c35ef0252cb..fa12d5d2685 100644\n--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n@@ -168,6 +168,8 @@ struct dram_config {\n \tu8 bus_full_width;\n };\n \n+#define H616_PHY_INIT_LEN\t27\n+\n static inline int ns_to_t(const struct dram_para *para, int nanoseconds)\n {\n \tconst unsigned int ctrl_freq = para->clk / 2;\n@@ -175,6 +177,7 @@ static inline int ns_to_t(const struct dram_para *para, int nanoseconds)\n \treturn DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);\n }\n \n+extern const u8 *phy_init;\n void mctl_set_timing_params(const struct dram_para *para);\n \n #endif /* _SUNXI_DRAM_SUN50I_H616_H */\ndiff --git a/arch/arm/mach-sunxi/dram_sun50i_h616.c b/arch/arm/mach-sunxi/dram_sun50i_h616.c\nindex 3345c9b8e82..5ee1ca25311 100644\n--- a/arch/arm/mach-sunxi/dram_sun50i_h616.c\n+++ b/arch/arm/mach-sunxi/dram_sun50i_h616.c\n@@ -227,45 +227,6 @@ static void mctl_set_addrmap(const struct dram_config *config)\n \tmctl_ctl->addrmap[8] = 0x3F3F;\n }\n \n-#ifdef CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1\n-static const u8 phy_init[] = {\n-#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333\n-\t0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b,\n-\t0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a,\n-\t0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19,\n-\t0x06, 0x09, 0x0f\n-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)\n-\t0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19,\n-\t0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n-\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,\n-\t0x08, 0x01, 0x1a\n-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)\n-\t0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07,\n-\t0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n-\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,\n-\t0x18, 0x04, 0x1a\n-#endif\n-};\n-#else /* CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_0 */\n-static const u8 phy_init[] = {\n-#ifdef CONFIG_SUNXI_DRAM_H616_DDR3_1333\n-\t0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,\n-\t0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,\n-\t0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,\n-\t0x09, 0x05, 0x18\n-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR3)\n-\t0x18, 0x06, 0x00, 0x05, 0x04, 0x03, 0x09, 0x02,\n-\t0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n-\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,\n-\t0x17, 0x19, 0x1a\n-#elif defined(CONFIG_SUNXI_DRAM_H616_LPDDR4)\n-\t0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,\n-\t0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n-\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,\n-\t0x18, 0x03, 0x1a\n-#endif\n-};\n-#endif /* CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_0 */\n #define MASK_BYTE(reg, nr) (((reg) >> ((nr) * 8)) & 0x1f)\n static void mctl_phy_configure_odt(const struct dram_para *para)\n {\n@@ -964,7 +925,7 @@ static bool mctl_phy_init(const struct dram_para *para,\n \twritel(val2, SUNXI_DRAM_PHY0_BASE + 0x37c);\n \n \tptr = (u32 *)(SUNXI_DRAM_PHY0_BASE + 0xc0);\n-\tfor (i = 0; i < ARRAY_SIZE(phy_init); i++)\n+\tfor (i = 0; i < H616_PHY_INIT_LEN; i++)\n \t\twritel(phy_init[i], &ptr[i]);\n \n \tif (para->tpr10 & TPR10_CA_BIT_DELAY)\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\nindex 1f0d0de198c..f367f604d5f 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\n@@ -14,6 +14,24 @@\n #include <asm/arch/dram.h>\n #include <asm/arch/cpu.h>\n \n+static const u8 h616_ddr3_phy_init_default[H616_PHY_INIT_LEN] = {\n+\t0x07, 0x0b, 0x02, 0x16, 0x0d, 0x0e, 0x14, 0x19,\n+\t0x0a, 0x15, 0x03, 0x13, 0x04, 0x0c, 0x10, 0x06,\n+\t0x0f, 0x11, 0x1a, 0x01, 0x12, 0x17, 0x00, 0x08,\n+\t0x09, 0x05, 0x18\n+};\n+\n+static const u8 h616_ddr3_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {\n+\t0x08, 0x02, 0x12, 0x05, 0x15, 0x17, 0x18, 0x0b,\n+\t0x14, 0x07, 0x04, 0x13, 0x0c, 0x00, 0x16, 0x1a,\n+\t0x0a, 0x11, 0x03, 0x10, 0x0e, 0x01, 0x0d, 0x19,\n+\t0x06, 0x09, 0x0f\n+};\n+\n+const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?\n+\t\t h616_ddr3_phy_init_addr_map_1 :\n+\t\t h616_ddr3_phy_init_default;\n+\n void mctl_set_timing_params(const struct dram_para *para)\n {\n \tstruct sunxi_mctl_ctl_reg * const mctl_ctl =\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\nindex e753fd7b4af..7efb1b22a84 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\n@@ -14,6 +14,24 @@\n #include <asm/arch/dram.h>\n #include <asm/arch/cpu.h>\n \n+static const u8 h616_lpddr3_phy_init_default[H616_PHY_INIT_LEN] = {\n+\t0x18, 0x06, 0x00, 0x05, 0x04, 0x03, 0x09, 0x02,\n+\t0x08, 0x01, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n+\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,\n+\t0x17, 0x19, 0x1a\n+};\n+\n+static const u8 h616_lpddr3_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {\n+\t0x18, 0x00, 0x04, 0x09, 0x06, 0x05, 0x02, 0x19,\n+\t0x17, 0x03, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n+\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x07,\n+\t0x08, 0x01, 0x1a\n+};\n+\n+const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?\n+\t\t h616_lpddr3_phy_init_addr_map_1 :\n+\t\t h616_lpddr3_phy_init_default;\n+\n void mctl_set_timing_params(const struct dram_para *para)\n {\n \tstruct sunxi_mctl_ctl_reg * const mctl_ctl =\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\nindex bbe401464eb..055d8dd3cad 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\n@@ -12,6 +12,24 @@\n #include <asm/arch/dram.h>\n #include <asm/arch/cpu.h>\n \n+static const u8 h616_lpddr4_phy_init_default[H616_PHY_INIT_LEN] = {\n+\t0x02, 0x00, 0x17, 0x05, 0x04, 0x19, 0x06, 0x07,\n+\t0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n+\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,\n+\t0x18, 0x03, 0x1a\n+};\n+\n+static const u8 h616_lpddr4_phy_init_addr_map_1[H616_PHY_INIT_LEN] = {\n+\t0x03, 0x00, 0x17, 0x05, 0x02, 0x19, 0x06, 0x07,\n+\t0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,\n+\t0x10, 0x11, 0x12, 0x13, 0x14, 0x15, 0x16, 0x01,\n+\t0x18, 0x04, 0x1a\n+};\n+\n+const u8 *phy_init = IS_ENABLED(CONFIG_DRAM_SUNXI_PHY_ADDR_MAP_1) ?\n+\t\t h616_lpddr4_phy_init_addr_map_1 :\n+\t\t h616_lpddr4_phy_init_default;\n+\n void mctl_set_timing_params(const struct dram_para *para)\n {\n \tstruct sunxi_mctl_ctl_reg * const mctl_ctl =\n", "prefixes": [ "v4", "2/5" ] }