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GET /api/patches/2217283/?format=api
{ "id": 2217283, "url": "http://patchwork.ozlabs.org/api/patches/2217283/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-1-james.hilliard1@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327200932.2016910-1-james.hilliard1@gmail.com>", "list_archive_url": null, "date": "2026-03-27T20:09:12", "name": "[v4,1/5] sunxi: h616: make ns_to_t() use the DRAM clock", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "fde59484577403e55910cf89671700db532238da", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": { "id": 114289, "url": "http://patchwork.ozlabs.org/api/users/114289/?format=api", "username": "apritzel", "first_name": "Andre", "last_name": "Przywara", "email": "andre.przywara@arm.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327200932.2016910-1-james.hilliard1@gmail.com/mbox/", "series": [ { "id": 497825, "url": "http://patchwork.ozlabs.org/api/series/497825/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497825", "date": "2026-03-27T20:09:12", "name": "[v4,1/5] sunxi: h616: make ns_to_t() use the DRAM clock", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497825/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217283/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217283/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", 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46e09a7af769-7d9fad77586mr2049433a34.13.1774642194036;\n Fri, 27 Mar 2026 13:09:54 -0700 (PDT)", "From": "James Hilliard <james.hilliard1@gmail.com>", "To": "u-boot@lists.denx.de", "Cc": "James Hilliard <james.hilliard1@gmail.com>,\n Andre Przywara <andre.przywara@arm.com>, Tom Rini <trini@konsulko.com>,\n Jernej Skrabec <jernej.skrabec@gmail.com>,\n \"Kory Maincent (TI.com)\" <kory.maincent@bootlin.com>,\n Paul Kocialkowski <contact@paulk.fr>,\n Alper Nebi Yasak <alpernebiyasak@gmail.com>,\n Richard Genoud <richard.genoud@bootlin.com>,\n Alexander Graf <agraf@csgraf.de>, Cody Eksal <masterr3c0rd@epochal.quest>,\n Samuel Holland <samuel@sholland.org>,\n Mikhail Kalashnikov <iuncuim@gmail.com>", "Subject": "[PATCH v4 1/5] sunxi: h616: make ns_to_t() use the DRAM clock", "Date": "Fri, 27 Mar 2026 14:09:12 -0600", "Message-ID": "<20260327200932.2016910-1-james.hilliard1@gmail.com>", "X-Mailer": "git-send-email 2.43.0", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Pass struct dram_para into ns_to_t() and derive the controller\nclock from para->clk instead of CONFIG_DRAM_CLK.\n\nThis prepares the H616 timing code for selecting the DRAM\nbackend from runtime parameters instead of a fixed build-time\nclock setting.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\n .../include/asm/arch-sunxi/dram_sun50i_h616.h | 4 +--\n .../mach-sunxi/dram_timings/h616_ddr3_1333.c | 30 +++++++++----------\n .../arm/mach-sunxi/dram_timings/h616_lpddr3.c | 30 +++++++++----------\n .../dram_timings/h616_lpddr4_2133.c | 30 +++++++++----------\n 4 files changed, 47 insertions(+), 47 deletions(-)", "diff": "diff --git a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\nindex a8fdda124a0..c35ef0252cb 100644\n--- a/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n+++ b/arch/arm/include/asm/arch-sunxi/dram_sun50i_h616.h\n@@ -168,9 +168,9 @@ struct dram_config {\n \tu8 bus_full_width;\n };\n \n-static inline int ns_to_t(int nanoseconds)\n+static inline int ns_to_t(const struct dram_para *para, int nanoseconds)\n {\n-\tconst unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;\n+\tconst unsigned int ctrl_freq = para->clk / 2;\n \n \treturn DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);\n }\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\nindex 3faf8d5bd97..1f0d0de198c 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_ddr3_1333.c\n@@ -20,27 +20,27 @@ void mctl_set_timing_params(const struct dram_para *para)\n \t\t\t(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;\n \n \tu8 tccd\t\t= 2;\t\t\t/* JEDEC: 4nCK */\n-\tu8 tfaw\t\t= ns_to_t(50);\t\t/* JEDEC: 30 ns w/ 1K pages */\n-\tu8 trrd\t\t= max(ns_to_t(6), 4);\t/* JEDEC: max(6 ns, 4nCK) */\n-\tu8 trcd\t\t= ns_to_t(15);\t\t/* JEDEC: 13.5 ns */\n-\tu8 trc\t\t= ns_to_t(53);\t\t/* JEDEC: 49.5 ns */\n-\tu8 txp\t\t= max(ns_to_t(6), 3);\t/* JEDEC: max(6 ns, 3nCK) */\n-\tu8 trtp\t\t= max(ns_to_t(8), 2);\t/* JEDEC: max(7.5 ns, 4nCK) */\n-\tu8 trp\t\t= ns_to_t(15);\t\t/* JEDEC: >= 13.75 ns */\n-\tu8 tras\t\t= ns_to_t(38);\t\t/* JEDEC >= 36 ns, <= 9*trefi */\n-\tu16 trefi\t= ns_to_t(7800) / 32;\t/* JEDEC: 7.8us@Tcase <= 85C */\n-\tu16 trfc\t= ns_to_t(350);\t\t/* JEDEC: 160 ns for 2Gb */\n+\tu8 tfaw\t\t= ns_to_t(para, 50);\t/* JEDEC: 30 ns w/ 1K pages */\n+\tu8 trrd\t\t= max(ns_to_t(para, 6), 4); /* JEDEC: max(6 ns, 4nCK) */\n+\tu8 trcd\t\t= ns_to_t(para, 15);\t/* JEDEC: 13.5 ns */\n+\tu8 trc\t\t= ns_to_t(para, 53);\t/* JEDEC: 49.5 ns */\n+\tu8 txp\t\t= max(ns_to_t(para, 6), 3); /* JEDEC: max(6 ns, 3nCK) */\n+\tu8 trtp\t\t= max(ns_to_t(para, 8), 2); /* JEDEC: max(7.5 ns, 4nCK) */\n+\tu8 trp\t\t= ns_to_t(para, 15);\t/* JEDEC: >= 13.75 ns */\n+\tu8 tras\t\t= ns_to_t(para, 38);\t/* JEDEC >= 36 ns, <= 9*trefi */\n+\tu16 trefi\t= ns_to_t(para, 7800) / 32; /* JEDEC: 7.8us@Tcase <= 85C */\n+\tu16 trfc\t= ns_to_t(para, 350);\t/* JEDEC: 160 ns for 2Gb */\n \tu16 txsr\t= 4;\t\t\t/* ? */\n \n \tu8 tmrw\t\t= 0;\t\t\t/* ? */\n \tu8 tmrd\t\t= 4;\t\t\t/* JEDEC: 4nCK */\n-\tu8 tmod\t\t= max(ns_to_t(15), 12);\t/* JEDEC: max(15 ns, 12nCK) */\n-\tu8 tcke\t\t= max(ns_to_t(6), 3);\t/* JEDEC: max(5.625 ns, 3nCK) */\n-\tu8 tcksrx\t= max(ns_to_t(10), 4);\t/* JEDEC: max(10 ns, 5nCK) */\n-\tu8 tcksre\t= max(ns_to_t(10), 4);\t/* JEDEC: max(10 ns, 5nCK) */\n+\tu8 tmod\t\t= max(ns_to_t(para, 15), 12); /* JEDEC: max(15 ns, 12nCK) */\n+\tu8 tcke\t\t= max(ns_to_t(para, 6), 3); /* JEDEC: max(5.625 ns, 3nCK) */\n+\tu8 tcksrx\t= max(ns_to_t(para, 10), 4); /* JEDEC: max(10 ns, 5nCK) */\n+\tu8 tcksre\t= max(ns_to_t(para, 10), 4); /* JEDEC: max(10 ns, 5nCK) */\n \tu8 tckesr\t= tcke + 1;\t\t/* JEDEC: tCKE(min) + 1nCK */\n \tu8 trasmax\t= (para->clk / 2) / 15;\t/* JEDEC: tREFI * 9 */\n-\tu8 txs\t\t= ns_to_t(360) / 32;\t/* JEDEC: max(5nCK,tRFC+10ns) */\n+\tu8 txs\t\t= ns_to_t(para, 360) / 32; /* JEDEC: max(5nCK,tRFC+10ns) */\n \tu8 txsdll\t= 16;\t\t\t/* JEDEC: 512 nCK */\n \tu8 txsabort\t= 4;\t\t\t/* ? */\n \tu8 txsfast\t= 4;\t\t\t/* ? */\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\nindex ce2ffa7a020..e753fd7b4af 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr3.c\n@@ -20,27 +20,27 @@ void mctl_set_timing_params(const struct dram_para *para)\n \t\t\t(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;\n \n \tu8 tccd\t\t= 2;\n-\tu8 tfaw\t\t= ns_to_t(50);\n-\tu8 trrd\t\t= max(ns_to_t(6), 4);\n-\tu8 trcd\t\t= ns_to_t(24);\n-\tu8 trc\t\t= ns_to_t(70);\n-\tu8 txp\t\t= max(ns_to_t(8), 3);\n-\tu8 trtp\t\t= max(ns_to_t(8), 2);\n-\tu8 trp\t\t= ns_to_t(27);\n-\tu8 tras\t\t= ns_to_t(41);\n-\tu16 trefi\t= ns_to_t(7800) / 64;\n-\tu16 trfc\t= ns_to_t(210);\n+\tu8 tfaw\t\t= ns_to_t(para, 50);\n+\tu8 trrd\t\t= max(ns_to_t(para, 6), 4);\n+\tu8 trcd\t\t= ns_to_t(para, 24);\n+\tu8 trc\t\t= ns_to_t(para, 70);\n+\tu8 txp\t\t= max(ns_to_t(para, 8), 3);\n+\tu8 trtp\t\t= max(ns_to_t(para, 8), 2);\n+\tu8 trp\t\t= ns_to_t(para, 27);\n+\tu8 tras\t\t= ns_to_t(para, 41);\n+\tu16 trefi\t= ns_to_t(para, 7800) / 64;\n+\tu16 trfc\t= ns_to_t(para, 210);\n \tu16 txsr\t= 88;\n \n \tu8 tmrw\t\t= 5;\n \tu8 tmrd\t\t= 5;\n-\tu8 tmod\t\t= max(ns_to_t(15), 12);\n-\tu8 tcke\t\t= max(ns_to_t(6), 3);\n-\tu8 tcksrx\t= max(ns_to_t(12), 4);\n-\tu8 tcksre\t= max(ns_to_t(12), 4);\n+\tu8 tmod\t\t= max(ns_to_t(para, 15), 12);\n+\tu8 tcke\t\t= max(ns_to_t(para, 6), 3);\n+\tu8 tcksrx\t= max(ns_to_t(para, 12), 4);\n+\tu8 tcksre\t= max(ns_to_t(para, 12), 4);\n \tu8 tckesr\t= tcke + 2;\n \tu8 trasmax\t= (para->clk / 2) / 16;\n-\tu8 txs\t\t= ns_to_t(360) / 32;\n+\tu8 txs\t\t= ns_to_t(para, 360) / 32;\n \tu8 txsdll\t= 16;\n \tu8 txsabort\t= 4;\n \tu8 txsfast\t= 4;\ndiff --git a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\nindex 6f5c4acbd62..bbe401464eb 100644\n--- a/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\n+++ b/arch/arm/mach-sunxi/dram_timings/h616_lpddr4_2133.c\n@@ -18,24 +18,24 @@ void mctl_set_timing_params(const struct dram_para *para)\n \t\t\t(struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;\n \n \tu8 tccd\t\t= 4;\n-\tu8 tfaw\t\t= ns_to_t(40);\n-\tu8 trrd\t\t= max(ns_to_t(10), 2);\n-\tu8 trcd\t\t= max(ns_to_t(18), 2);\n-\tu8 trc\t\t= ns_to_t(65);\n-\tu8 txp\t\t= max(ns_to_t(8), 2);\n+\tu8 tfaw\t\t= ns_to_t(para, 40);\n+\tu8 trrd\t\t= max(ns_to_t(para, 10), 2);\n+\tu8 trcd\t\t= max(ns_to_t(para, 18), 2);\n+\tu8 trc\t\t= ns_to_t(para, 65);\n+\tu8 txp\t\t= max(ns_to_t(para, 8), 2);\n \tu8 trtp\t\t= 4;\n-\tu8 trp\t\t= ns_to_t(21);\n-\tu8 tras\t\t= ns_to_t(42);\n-\tu16 trefi\t= ns_to_t(3904) / 32;\n-\tu16 trfc\t= ns_to_t(280);\n-\tu16 txsr\t= ns_to_t(190);\n+\tu8 trp\t\t= ns_to_t(para, 21);\n+\tu8 tras\t\t= ns_to_t(para, 42);\n+\tu16 trefi\t= ns_to_t(para, 3904) / 32;\n+\tu16 trfc\t= ns_to_t(para, 280);\n+\tu16 txsr\t= ns_to_t(para, 190);\n \n-\tu8 tmrw\t\t= max(ns_to_t(14), 5);\n+\tu8 tmrw\t\t= max(ns_to_t(para, 14), 5);\n \tu8 tmrd\t\t= tmrw;\n \tu8 tmod\t\t= 12;\n-\tu8 tcke\t\t= max(ns_to_t(15), 2);\n-\tu8 tcksrx\t= max(ns_to_t(2), 2);\n-\tu8 tcksre\t= max(ns_to_t(5), 2);\n+\tu8 tcke\t\t= max(ns_to_t(para, 15), 2);\n+\tu8 tcksrx\t= max(ns_to_t(para, 2), 2);\n+\tu8 tcksre\t= max(ns_to_t(para, 5), 2);\n \tu8 tckesr\t= tcke;\n \tu8 trasmax\t= (trefi * 9) / 32;\n \tu8 txs\t\t= 4;\n@@ -49,7 +49,7 @@ void mctl_set_timing_params(const struct dram_para *para)\n \n \tu8 twtp\t\t= 24;\n \tu8 twr2rd\t= max(trrd, (u8)4) + 14;\n-\tu8 trd2wr\t= (ns_to_t(4) + 17) - ns_to_t(1);\n+\tu8 trd2wr\t= (ns_to_t(para, 4) + 17) - ns_to_t(para, 1);\n \n \t/* set DRAM timing */\n \twritel((twtp << 24) | (tfaw << 16) | (trasmax << 8) | tras,\n", "prefixes": [ "v4", "1/5" ] }