Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217137/?format=api
{ "id": 2217137, "url": "http://patchwork.ozlabs.org/api/patches/2217137/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327173209.148180-3-mbawa@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327173209.148180-3-mbawa@redhat.com>", "list_archive_url": null, "date": "2026-03-27T17:32:08", "name": "[v3,2/3] hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0f6e0cb423c0c62a4d6f70f3519bcf9e66df3bfa", "submitter": { "id": 92626, "url": "http://patchwork.ozlabs.org/api/people/92626/?format=api", "name": "Mohammadfaiz Bawa", "email": "mbawa@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327173209.148180-3-mbawa@redhat.com/mbox/", "series": [ { "id": 497807, "url": "http://patchwork.ozlabs.org/api/series/497807/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497807", "date": "2026-03-27T17:32:08", "name": "hw/tpm: add PPI support to tpm-tis-device on ARM64 virt", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497807/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217137/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217137/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=W2P1VPA1;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fj75g2ql4z1y1P\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 04:33:11 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w6B3E-0006eL-6h; Fri, 27 Mar 2026 13:32:52 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mbawa@redhat.com>) id 1w6B36-0006aD-UG\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 13:32:45 -0400", "from us-smtp-delivery-124.mimecast.com ([170.10.133.124])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mbawa@redhat.com>) id 1w6B35-0007yt-Be\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 13:32:44 -0400", "from mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com\n (ec2-35-165-154-97.us-west-2.compute.amazonaws.com [35.165.154.97]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3,\n cipher=TLS_AES_256_GCM_SHA384) id us-mta-134-OWOwgaU7MXang1WWexYB7Q-1; Fri,\n 27 Mar 2026 13:32:37 -0400", "from mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com\n (mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.4])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mx-prod-mc-08.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS\n id 3B39F1800464; Fri, 27 Mar 2026 17:32:36 +0000 (UTC)", "from mbawa-thinkpadt14gen5.bengluru.csb (unknown [10.74.88.2])\n by mx-prod-int-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP\n id 7A5A830001A1; Fri, 27 Mar 2026 17:32:29 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1774632762;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=1l0fA9dLaPFhQ3AtiN7mPv0FR5CxBzjNHadXvLmdK6s=;\n b=W2P1VPA1kupXqEv1oEjktLum9Lc2/Z659w7FLkp8cEesL1bdiKtxc7WAP5nQpRKY3AoIJ9\n ZExpEg7C3IfaXNMZP6DYSxZehVnsQWjeod0hArWvaj4jd6FomessbSR9CFkEgWDjt5cYcz\n jszBR3BjM0pE/SpOwW/44uML9qrYX9g=", "X-MC-Unique": "OWOwgaU7MXang1WWexYB7Q-1", "X-Mimecast-MFC-AGG-ID": "OWOwgaU7MXang1WWexYB7Q_1774632756", "From": "Mohammadfaiz Bawa <mbawa@redhat.com>", "To": "qemu-devel@nongnu.org", "Cc": "stefanb@linux.vnet.ibm.com, pierrick.bouvier@linaro.org,\n \"Michael S . Tsirkin\" <mst@redhat.com>, imammedo@redhat.com,\n anisinha@redhat.com, peter.maydell@linaro.org, shannon.zhaosl@gmail.com,\n qemu-arm@nongnu.org, mohamed@unpredictable.fr, philmd@linaro.org,\n Mohammadfaiz Bawa <mbawa@redhat.com>, Stefan Berger <stefanb@linux.ibm.com>", "Subject": "[PATCH v3 2/3] hw/acpi/tpm: parameterize PPI base address in\n tpm_build_ppi_acpi", "Date": "Fri, 27 Mar 2026 23:02:08 +0530", "Message-ID": "<20260327173209.148180-3-mbawa@redhat.com>", "In-Reply-To": "<20260327173209.148180-1-mbawa@redhat.com>", "References": "<20260327173209.148180-1-mbawa@redhat.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Scanned-By": "MIMEDefang 3.4.1 on 10.30.177.4", "Received-SPF": "pass client-ip=170.10.133.124; envelope-from=mbawa@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a ppi_base parameter to tpm_build_ppi_acpi() instead of\nhardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where\nPPI memory is dynamically allocated by the platform bus and the\naddress is not known at compile time.\n\nUpdate the x86 callers (ISA TIS and CRB) to pass TPM_PPI_ADDR_BASE\nexplicitly. No behavioral change.\n\nReviewed-by: Stefan Berger <stefanb@linux.ibm.com>\nSigned-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>\n---\n hw/acpi/tpm.c | 8 ++++----\n hw/i386/acpi-build.c | 2 +-\n hw/tpm/tpm_tis_isa.c | 2 +-\n include/hw/acpi/tpm.h | 3 ++-\n 4 files changed, 8 insertions(+), 7 deletions(-)", "diff": "diff --git a/hw/acpi/tpm.c b/hw/acpi/tpm.c\nindex 5fe95f2e3f..e703775984 100644\n--- a/hw/acpi/tpm.c\n+++ b/hw/acpi/tpm.c\n@@ -20,7 +20,7 @@\n #include \"qapi/error.h\"\n #include \"hw/acpi/tpm.h\"\n \n-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)\n {\n Aml *method, *field, *ifctx, *ifctx2, *ifctx3, *func_mask,\n *not_implemented, *pak, *tpm2, *tpm3, *pprm, *pprq, *zero, *one;\n@@ -40,7 +40,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n */\n aml_append(dev,\n aml_operation_region(\"TPP2\", AML_SYSTEM_MEMORY,\n- aml_int(TPM_PPI_ADDR_BASE + 0x100),\n+ aml_int(ppi_base + 0x100),\n 0x5A));\n field = aml_field(\"TPP2\", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);\n aml_append(field, aml_named_field(\"PPIN\", 8));\n@@ -56,7 +56,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n aml_append(dev,\n aml_operation_region(\n \"TPP3\", AML_SYSTEM_MEMORY,\n- aml_int(TPM_PPI_ADDR_BASE +\n+ aml_int(ppi_base +\n 0x15a /* movv, docs/specs/tpm.rst */),\n 0x1));\n field = aml_field(\"TPP3\", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);\n@@ -78,7 +78,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n \n aml_append(method,\n aml_operation_region(\"TPP1\", AML_SYSTEM_MEMORY,\n- aml_add(aml_int(TPM_PPI_ADDR_BASE), op, NULL), 0x1));\n+ aml_add(aml_int(ppi_base), op, NULL), 0x1));\n field = aml_field(\"TPP1\", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);\n aml_append(field, aml_named_field(\"TPPF\", 8));\n aml_append(method, field);\ndiff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c\nindex 4f01e2c476..0d7c83d5e9 100644\n--- a/hw/i386/acpi-build.c\n+++ b/hw/i386/acpi-build.c\n@@ -1219,7 +1219,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker,\n aml_append(dev, aml_name_decl(\"_STA\", aml_int(0xf)));\n aml_append(dev, aml_name_decl(\"_UID\", aml_int(1)));\n \n- tpm_build_ppi_acpi(tpm, dev);\n+ tpm_build_ppi_acpi(tpm, dev, TPM_PPI_ADDR_BASE);\n \n aml_append(sb_scope, dev);\n }\ndiff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c\nindex 1ca403241d..2b1267133a 100644\n--- a/hw/tpm/tpm_tis_isa.c\n+++ b/hw/tpm/tpm_tis_isa.c\n@@ -159,7 +159,7 @@ static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)\n */\n /* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */\n aml_append(dev, aml_name_decl(\"_CRS\", crs));\n- tpm_build_ppi_acpi(ti, dev);\n+ tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE);\n aml_append(scope, dev);\n }\n \ndiff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h\nindex d2bf6637c5..2ab186a745 100644\n--- a/include/hw/acpi/tpm.h\n+++ b/include/hw/acpi/tpm.h\n@@ -20,6 +20,7 @@\n #include \"hw/core/registerfields.h\"\n #include \"hw/acpi/aml-build.h\"\n #include \"system/tpm.h\"\n+#include \"exec/hwaddr.h\"\n \n #ifdef CONFIG_TPM\n \n@@ -250,7 +251,7 @@ REG32(CRB_DATA_BUFFER, 0x80)\n */\n #define TPM_I2C_INT_ENABLE_MASK 0x0\n \n-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);\n+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base);\n \n #endif /* CONFIG_TPM */\n \n", "prefixes": [ "v3", "2/3" ] }