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GET /api/patches/2217119/?format=api
{ "id": 2217119, "url": "http://patchwork.ozlabs.org/api/patches/2217119/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-22-yilun.xu@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327160132.2946114-22-yilun.xu@linux.intel.com>", "list_archive_url": null, "date": "2026-03-27T16:01:22", "name": "[v2,21/31] x86/virt/tdx: Add SEAMCALL wrappers for trusted IOMMU setup and clear", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4c523efa94dc7aaefa5e9458dcb56394789c0182", "submitter": { "id": 87470, "url": "http://patchwork.ozlabs.org/api/people/87470/?format=api", "name": "Xu Yilun", "email": "yilun.xu@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-22-yilun.xu@linux.intel.com/mbox/", "series": [ { "id": 497793, "url": "http://patchwork.ozlabs.org/api/series/497793/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497793", "date": "2026-03-27T16:01:02", "name": "PCI/TSM: PCIe Link Encryption Establishment via TDX platform services", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497793/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217119/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217119/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51307-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=XL050/D/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; helo=sin.lore.kernel.org;\n envelope-from=linux-pci+bounces-51307-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"XL050/D/\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.14", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com" ], "Received": [ "from sin.lore.kernel.org (sin.lore.kernel.org\n [IPv6:2600:3c15:e001:75::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fj6KW4Rhdz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 03:58:23 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sin.lore.kernel.org (Postfix) with ESMTP id 9FAC930B13FC\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 16:28:29 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1C0ED3FCB22;\n\tFri, 27 Mar 2026 16:23:53 +0000 (UTC)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.14])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id B9D683FBED6;\n\tFri, 27 Mar 2026 16:23:51 +0000 (UTC)", "from fmviesa006.fm.intel.com ([10.60.135.146])\n by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Mar 2026 09:23:51 -0700", "from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165])\n by fmviesa006.fm.intel.com with ESMTP; 27 Mar 2026 09:23:48 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774628633; cv=none;\n b=lK1XidmT3RAcdfHgFhArK4r47V9CnVROOb34VsLYHGyphbVkB7bGWtx0mc1wwTR9Ann/skQFHHYVLkmQQ5TRw/iAAWzgVgUKwUUUbAIIIkV5yO+J/w9H5ZnGpJ0YwJpkwJcHHDIQrnV3+PCvpffz6mzsFQ0tOny4hChzKt4CSJE=", "ARC-Message-Signature": "i=1; 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a=\"79565644\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"79565644\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"220516334\"" ], "X-ExtLoop1": "1", "From": "Xu Yilun <yilun.xu@linux.intel.com>", "To": "linux-coco@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdan.j.williams@intel.com,\n\tx86@kernel.org", "Cc": "chao.gao@intel.com,\n\tdave.jiang@intel.com,\n\tbaolu.lu@linux.intel.com,\n\tyilun.xu@linux.intel.com,\n\tyilun.xu@intel.com,\n\tzhenzhong.duan@intel.com,\n\tkvm@vger.kernel.org,\n\trick.p.edgecombe@intel.com,\n\tdave.hansen@linux.intel.com,\n\tkas@kernel.org,\n\txiaoyao.li@intel.com,\n\tvishal.l.verma@intel.com,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 21/31] x86/virt/tdx: Add SEAMCALL wrappers for trusted\n IOMMU setup and clear", "Date": "Sat, 28 Mar 2026 00:01:22 +0800", "Message-Id": "<20260327160132.2946114-22-yilun.xu@linux.intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "References": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Zhenzhong Duan <zhenzhong.duan@intel.com>\n\nAdd SEAMCALLs to setup/clear trusted IOMMU for TDX Connect.\n\nEnable TEE I/O support for a target device requires to setup trusted IOMMU\nfor the related IOMMU device first, even only for enabling physical secure\nlinks like SPDM/IDE.\n\nTDH.IOMMU.SETUP takes the register base address (VTBAR) to position an\nIOMMU device, and outputs an IOMMU_ID as the trusted IOMMU identifier.\nTDH.IOMMU.CLEAR takes the IOMMU_ID to reverse the setup.\n\nMore information see Intel TDX Connect ABI Specification [1]\nSection 3.2 TDX Connect Host-Side (SEAMCALL) Interface Functions.\n\n[1]: https://cdrdv2.intel.com/v1/dl/getContent/858625\n\nCo-developed-by: Xu Yilun <yilun.xu@linux.intel.com>\nSigned-off-by: Xu Yilun <yilun.xu@linux.intel.com>\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n arch/x86/include/asm/tdx.h | 2 ++\n arch/x86/virt/vmx/tdx/tdx.h | 2 ++\n arch/x86/virt/vmx/tdx/tdx.c | 32 ++++++++++++++++++++++++++++++--\n 3 files changed, 34 insertions(+), 2 deletions(-)", "diff": "diff --git a/arch/x86/include/asm/tdx.h b/arch/x86/include/asm/tdx.h\nindex d7605235aa9b..a59e0e43e465 100644\n--- a/arch/x86/include/asm/tdx.h\n+++ b/arch/x86/include/asm/tdx.h\n@@ -245,6 +245,8 @@ u64 tdh_mem_page_remove(struct tdx_td *td, u64 gpa, u64 level, u64 *ext_err1, u6\n u64 tdh_phymem_cache_wb(bool resume);\n u64 tdh_phymem_page_wbinvd_tdr(struct tdx_td *td);\n u64 tdh_phymem_page_wbinvd_hkid(u64 hkid, struct page *page);\n+u64 tdh_iommu_setup(u64 vtbar, struct tdx_page_array *iommu_mt, u64 *iommu_id);\n+u64 tdh_iommu_clear(u64 iommu_id, struct tdx_page_array *iommu_mt);\n #else\n static inline void tdx_init(void) { }\n static inline int tdx_cpu_enable(void) { return -ENODEV; }\ndiff --git a/arch/x86/virt/vmx/tdx/tdx.h b/arch/x86/virt/vmx/tdx/tdx.h\nindex a26fe94c07ff..b25c418f6e61 100644\n--- a/arch/x86/virt/vmx/tdx/tdx.h\n+++ b/arch/x86/virt/vmx/tdx/tdx.h\n@@ -62,6 +62,8 @@\n #define TDH_SYS_CONFIG\t\t\tSEAMCALL_LEAF_VER(TDH_SYS_CONFIG_V0, 1)\n #define TDH_EXT_INIT\t\t\t60\n #define TDH_EXT_MEM_ADD\t\t\t61\n+#define TDH_IOMMU_SETUP\t\t\t128\n+#define TDH_IOMMU_CLEAR\t\t\t129\n \n /* TDX page types */\n #define\tPT_NDA\t\t0x0\ndiff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c\nindex 294f36048c03..790713881f1f 100644\n--- a/arch/x86/virt/vmx/tdx/tdx.c\n+++ b/arch/x86/virt/vmx/tdx/tdx.c\n@@ -2084,8 +2084,8 @@ static inline u64 tdx_tdr_pa(struct tdx_td *td)\n \treturn page_to_phys(td->tdr_page);\n }\n \n-static u64 __maybe_unused __seamcall_ir_resched(sc_func_t sc_func, u64 fn,\n-\t\t\t\t\t\tstruct tdx_module_args *args)\n+static u64 __seamcall_ir_resched(sc_func_t sc_func, u64 fn,\n+\t\t\t\t struct tdx_module_args *args)\n {\n \tstruct tdx_module_args _args;\n \tu64 r;\n@@ -2478,3 +2478,31 @@ void tdx_cpu_flush_cache_for_kexec(void)\n }\n EXPORT_SYMBOL_FOR_KVM(tdx_cpu_flush_cache_for_kexec);\n #endif\n+\n+u64 tdh_iommu_setup(u64 vtbar, struct tdx_page_array *iommu_mt, u64 *iommu_id)\n+{\n+\tstruct tdx_module_args args = {\n+\t\t.rcx = vtbar,\n+\t\t.rdx = virt_to_phys(iommu_mt->root),\n+\t};\n+\tu64 r;\n+\n+\ttdx_clflush_page_array(iommu_mt);\n+\n+\tr = seamcall_ret_ir_resched(TDH_IOMMU_SETUP, &args);\n+\n+\t*iommu_id = args.rcx;\n+\treturn r;\n+}\n+EXPORT_SYMBOL_FOR_MODULES(tdh_iommu_setup, \"tdx-host\");\n+\n+u64 tdh_iommu_clear(u64 iommu_id, struct tdx_page_array *iommu_mt)\n+{\n+\tstruct tdx_module_args args = {\n+\t\t.rcx = iommu_id,\n+\t\t.rdx = virt_to_phys(iommu_mt->root),\n+\t};\n+\n+\treturn seamcall_ret_ir_resched(TDH_IOMMU_CLEAR, &args);\n+}\n+EXPORT_SYMBOL_FOR_MODULES(tdh_iommu_clear, \"tdx-host\");\n", "prefixes": [ "v2", "21/31" ] }