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GET /api/patches/2217076/?format=api
{ "id": 2217076, "url": "http://patchwork.ozlabs.org/api/patches/2217076/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-20-yilun.xu@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327160132.2946114-20-yilun.xu@linux.intel.com>", "list_archive_url": null, "date": "2026-03-27T16:01:20", "name": "[v2,19/31] iommu/vt-d: Reserve the MSB domain ID bit for the TDX module", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "57bb083342175c1c27c11df9f94c879a36a02197", "submitter": { "id": 87470, "url": "http://patchwork.ozlabs.org/api/people/87470/?format=api", "name": "Xu Yilun", "email": "yilun.xu@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-20-yilun.xu@linux.intel.com/mbox/", "series": [ { "id": 497793, "url": "http://patchwork.ozlabs.org/api/series/497793/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497793", "date": "2026-03-27T16:01:02", "name": "PCI/TSM: PCIe Link Encryption Establishment via TDX platform services", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497793/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217076/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217076/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51305-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=m/UpO+UC;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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a=\"79565634\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"79565634\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"220516311\"" ], "X-ExtLoop1": "1", "From": "Xu Yilun <yilun.xu@linux.intel.com>", "To": "linux-coco@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdan.j.williams@intel.com,\n\tx86@kernel.org", "Cc": "chao.gao@intel.com,\n\tdave.jiang@intel.com,\n\tbaolu.lu@linux.intel.com,\n\tyilun.xu@linux.intel.com,\n\tyilun.xu@intel.com,\n\tzhenzhong.duan@intel.com,\n\tkvm@vger.kernel.org,\n\trick.p.edgecombe@intel.com,\n\tdave.hansen@linux.intel.com,\n\tkas@kernel.org,\n\txiaoyao.li@intel.com,\n\tvishal.l.verma@intel.com,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 19/31] iommu/vt-d: Reserve the MSB domain ID bit for the\n TDX module", "Date": "Sat, 28 Mar 2026 00:01:20 +0800", "Message-Id": "<20260327160132.2946114-20-yilun.xu@linux.intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "References": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit" }, "content": "From: Lu Baolu <baolu.lu@linux.intel.com>\n\nThe Intel TDX Connect Architecture Specification defines some enhancements\nfor the VT-d architecture to introduce IOMMU support for TEE-IO requests.\nSection 2.2, 'Trusted DMA' states that:\n\n\"I/O TLB and DID Isolation – When IOMMU is enabled to support TDX\nConnect, the IOMMU restricts the VMM’s DID setting, reserving the MSB bit\nfor the TDX module. The TDX module always sets this reserved bit on the\ntrusted DMA table. IOMMU tags IOTLB, PASID cache, and context entries to\nindicate whether they were created from TEE-IO transactions, ensuring\nisolation between TEE and non-TEE requests in translation caches.\"\n\nReserve the MSB in the domain ID for the TDX module's use if the\nenhancement is required, which is detected if the ECAP.TDXCS bit in the\nVT-d extended capability register is set and the TVM Usable field of the\nACPI KEYP table is set.\n\nCo-developed-by: Xu Yilun <yilun.xu@linux.intel.com>\nSigned-off-by: Xu Yilun <yilun.xu@linux.intel.com>\nSigned-off-by: Lu Baolu <baolu.lu@linux.intel.com>\n---\n drivers/iommu/intel/iommu.h | 1 +\n drivers/iommu/intel/dmar.c | 52 ++++++++++++++++++++++++++++++++++++-\n 2 files changed, 52 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/iommu/intel/iommu.h b/drivers/iommu/intel/iommu.h\nindex 4a21ab6a311d..0c2b4e38dee7 100644\n--- a/drivers/iommu/intel/iommu.h\n+++ b/drivers/iommu/intel/iommu.h\n@@ -192,6 +192,7 @@\n */\n \n #define ecap_pms(e)\t\t(((e) >> 51) & 0x1)\n+#define ecap_tdxc(e)\t\t(((e) >> 50) & 0x1)\n #define ecap_rps(e)\t\t(((e) >> 49) & 0x1)\n #define ecap_smpwc(e)\t\t(((e) >> 48) & 0x1)\n #define ecap_flts(e)\t\t(((e) >> 47) & 0x1)\ndiff --git a/drivers/iommu/intel/dmar.c b/drivers/iommu/intel/dmar.c\nindex 93efd1a5dc5b..4f9571eee1d4 100644\n--- a/drivers/iommu/intel/dmar.c\n+++ b/drivers/iommu/intel/dmar.c\n@@ -1033,6 +1033,56 @@ static int map_iommu(struct intel_iommu *iommu, struct dmar_drhd_unit *drhd)\n \treturn err;\n }\n \n+static int keyp_config_unit_tvm_usable(union acpi_subtable_headers *header,\n+\t\t\t\t void *arg, const unsigned long end)\n+{\n+\tstruct acpi_keyp_config_unit *acpi_cu =\n+\t\t(struct acpi_keyp_config_unit *)&header->keyp;\n+\tint *tvm_usable = arg;\n+\n+\tif (acpi_cu->flags & ACPI_KEYP_F_TVM_USABLE)\n+\t\t*tvm_usable = 1;\n+\n+\treturn 0;\n+}\n+\n+static bool platform_is_tdxc_enhanced(void)\n+{\n+\tstatic int tvm_usable = -1;\n+\tint ret;\n+\n+\t/* only need to parse once */\n+\tif (tvm_usable != -1)\n+\t\treturn !!tvm_usable;\n+\n+\ttvm_usable = 0;\n+\tret = acpi_table_parse_keyp(ACPI_KEYP_TYPE_CONFIG_UNIT,\n+\t\t\t\t keyp_config_unit_tvm_usable, &tvm_usable);\n+\tif (ret < 0)\n+\t\ttvm_usable = 0;\n+\n+\treturn !!tvm_usable;\n+}\n+\n+static unsigned long iommu_max_domain_id(struct intel_iommu *iommu)\n+{\n+\tunsigned long ndoms = cap_ndoms(iommu->cap);\n+\n+\t/*\n+\t * Intel TDX Connect Architecture Specification, Section 2.2 Trusted DMA\n+\t *\n+\t * When IOMMU is enabled to support TDX Connect, the IOMMU restricts\n+\t * the VMM’s DID setting, reserving the MSB bit for the TDX module. The\n+\t * TDX module always sets this reserved bit on the trusted DMA table.\n+\t */\n+\tif (ecap_tdxc(iommu->ecap) && platform_is_tdxc_enhanced()) {\n+\t\tpr_info_once(\"Most Significant Bit of domain ID reserved.\\n\");\n+\t\treturn ndoms >> 1;\n+\t}\n+\n+\treturn ndoms;\n+}\n+\n static int alloc_iommu(struct dmar_drhd_unit *drhd)\n {\n \tstruct intel_iommu *iommu;\n@@ -1099,7 +1149,7 @@ static int alloc_iommu(struct dmar_drhd_unit *drhd)\n \tspin_lock_init(&iommu->lock);\n \tida_init(&iommu->domain_ida);\n \tmutex_init(&iommu->did_lock);\n-\tiommu->max_domain_id = cap_ndoms(iommu->cap);\n+\tiommu->max_domain_id = iommu_max_domain_id(iommu);\n \n \tver = readl(iommu->reg + DMAR_VER_REG);\n \tpr_info(\"%s: reg_base_addr %llx ver %d:%d cap %llx ecap %llx\\n\",\n", "prefixes": [ "v2", "19/31" ] }