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GET /api/patches/2217073/?format=api
{ "id": 2217073, "url": "http://patchwork.ozlabs.org/api/patches/2217073/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-24-yilun.xu@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327160132.2946114-24-yilun.xu@linux.intel.com>", "list_archive_url": null, "date": "2026-03-27T16:01:24", "name": "[v2,23/31] coco/tdx-host: Setup all trusted IOMMUs on TDX Connect init", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c633a41817e5f57544f0c31f65ad0befa68dc782", "submitter": { "id": 87470, "url": "http://patchwork.ozlabs.org/api/people/87470/?format=api", "name": "Xu Yilun", "email": "yilun.xu@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-24-yilun.xu@linux.intel.com/mbox/", "series": [ { "id": 497793, "url": "http://patchwork.ozlabs.org/api/series/497793/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497793", "date": "2026-03-27T16:01:02", "name": "PCI/TSM: PCIe Link Encryption Establishment via TDX platform services", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497793/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217073/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217073/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51309-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=ZrdqVmU4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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a=\"79565654\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"79565654\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"220516345\"" ], "X-ExtLoop1": "1", "From": "Xu Yilun <yilun.xu@linux.intel.com>", "To": "linux-coco@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdan.j.williams@intel.com,\n\tx86@kernel.org", "Cc": "chao.gao@intel.com,\n\tdave.jiang@intel.com,\n\tbaolu.lu@linux.intel.com,\n\tyilun.xu@linux.intel.com,\n\tyilun.xu@intel.com,\n\tzhenzhong.duan@intel.com,\n\tkvm@vger.kernel.org,\n\trick.p.edgecombe@intel.com,\n\tdave.hansen@linux.intel.com,\n\tkas@kernel.org,\n\txiaoyao.li@intel.com,\n\tvishal.l.verma@intel.com,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 23/31] coco/tdx-host: Setup all trusted IOMMUs on TDX\n Connect init", "Date": "Sat, 28 Mar 2026 00:01:24 +0800", "Message-Id": "<20260327160132.2946114-24-yilun.xu@linux.intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "References": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Setup all trusted IOMMUs on TDX Connect initialization and clear all on\nTDX Connect removal.\n\nTrusted IOMMU setup is the pre-condition for all following TDX Connect\noperations such as SPDM/IDE setup. It is more of a platform\nconfiguration than a standalone IOMMU configuration, so put the\nimplementation in tdx-host driver.\n\nThere is no dedicated way to enumerate which IOMMU devices support\ntrusted operations. The host has to call TDH.IOMMU.SETUP on all IOMMU\ndevices and tell their trusted capability by the return value.\n\nSuggested-by: Lu Baolu <baolu.lu@linux.intel.com>\nSigned-off-by: Xu Yilun <yilun.xu@linux.intel.com>\n---\n drivers/virt/coco/tdx-host/Kconfig | 1 +\n drivers/virt/coco/tdx-host/tdx-host.c | 85 +++++++++++++++++++++++++++\n 2 files changed, 86 insertions(+)", "diff": "diff --git a/drivers/virt/coco/tdx-host/Kconfig b/drivers/virt/coco/tdx-host/Kconfig\nindex 32add81b7d56..24e872f8953e 100644\n--- a/drivers/virt/coco/tdx-host/Kconfig\n+++ b/drivers/virt/coco/tdx-host/Kconfig\n@@ -13,3 +13,4 @@ config TDX_CONNECT\n \tdef_bool y\n \tdepends on TDX_HOST_SERVICES\n \tdepends on PCI_TSM\n+\tdepends on INTEL_IOMMU\ndiff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-host/tdx-host.c\nindex 5ea35a514865..98ed93ac0153 100644\n--- a/drivers/virt/coco/tdx-host/tdx-host.c\n+++ b/drivers/virt/coco/tdx-host/tdx-host.c\n@@ -6,6 +6,7 @@\n */\n \n #include <linux/device/faux.h>\n+#include <linux/dmar.h>\n #include <linux/module.h>\n #include <linux/mod_devicetable.h>\n #include <linux/pci.h>\n@@ -119,6 +120,82 @@ static void unregister_link_tsm(void *link)\n \ttsm_unregister(link);\n }\n \n+static DEFINE_XARRAY(tlink_iommu_xa);\n+\n+static void tdx_iommu_clear(u64 iommu_id, struct tdx_page_array *iommu_mt)\n+{\n+\tu64 r;\n+\n+\tr = tdh_iommu_clear(iommu_id, iommu_mt);\n+\tif (r) {\n+\t\tpr_err(\"fail to clear tdx iommu 0x%llx\\n\", r);\n+\t\tgoto leak;\n+\t}\n+\n+\tif (tdx_page_array_ctrl_release(iommu_mt, iommu_mt->nr_pages,\n+\t\t\t\t\tvirt_to_phys(iommu_mt->root))) {\n+\t\tpr_err(\"fail to release iommu_mt pages\\n\");\n+\t\tgoto leak;\n+\t}\n+\n+\treturn;\n+\n+leak:\n+\ttdx_page_array_ctrl_leak(iommu_mt);\n+}\n+\n+static int tdx_iommu_enable_one(struct dmar_drhd_unit *drhd)\n+{\n+\tunsigned int nr_pages = tdx_sysinfo->connect.iommu_mt_page_count;\n+\tu64 r, iommu_id;\n+\tint ret;\n+\n+\tstruct tdx_page_array *iommu_mt __free(tdx_page_array_free) =\n+\t\ttdx_page_array_create_iommu_mt(1, nr_pages);\n+\tif (!iommu_mt)\n+\t\treturn -ENOMEM;\n+\n+\tr = tdh_iommu_setup(drhd->reg_base_addr, iommu_mt, &iommu_id);\n+\t/* This drhd doesn't support tdx mode, skip. */\n+\tif ((r & TDX_SEAMCALL_STATUS_MASK) == TDX_OPERAND_INVALID)\n+\t\treturn 0;\n+\n+\tif (r) {\n+\t\tpr_err(\"fail to enable tdx mode for DRHD[0x%llx]\\n\",\n+\t\t drhd->reg_base_addr);\n+\t\treturn -EFAULT;\n+\t}\n+\n+\tret = xa_insert(&tlink_iommu_xa, (unsigned long)iommu_id,\n+\t\t\tno_free_ptr(iommu_mt), GFP_KERNEL);\n+\tif (ret) {\n+\t\ttdx_iommu_clear(iommu_id, iommu_mt);\n+\t\treturn ret;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static void tdx_iommu_disable_all(void *data)\n+{\n+\tstruct tdx_page_array *iommu_mt;\n+\tunsigned long iommu_id;\n+\n+\txa_for_each(&tlink_iommu_xa, iommu_id, iommu_mt)\n+\t\ttdx_iommu_clear(iommu_id, iommu_mt);\n+}\n+\n+static int tdx_iommu_enable_all(void)\n+{\n+\tint ret;\n+\n+\tret = do_for_each_drhd_unit(tdx_iommu_enable_one);\n+\tif (ret)\n+\t\ttdx_iommu_disable_all(NULL);\n+\n+\treturn ret;\n+}\n+\n static int __maybe_unused tdx_connect_init(struct device *dev)\n {\n \tstruct tsm_dev *link;\n@@ -130,6 +207,14 @@ static int __maybe_unused tdx_connect_init(struct device *dev)\n \tif (!(tdx_sysinfo->features.tdx_features0 & TDX_FEATURES0_TDXCONNECT))\n \t\treturn 0;\n \n+\tret = tdx_iommu_enable_all();\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Enable tdx iommu failed\\n\");\n+\n+\tret = devm_add_action_or_reset(dev, tdx_iommu_disable_all, NULL);\n+\tif (ret)\n+\t\treturn ret;\n+\n \tlink = tsm_register(dev, &tdx_tsm_link_ops);\n \tif (IS_ERR(link))\n \t\treturn dev_err_probe(dev, PTR_ERR(link),\n", "prefixes": [ "v2", "23/31" ] }