Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217071/?format=api
{ "id": 2217071, "url": "http://patchwork.ozlabs.org/api/patches/2217071/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-25-yilun.xu@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327160132.2946114-25-yilun.xu@linux.intel.com>", "list_archive_url": null, "date": "2026-03-27T16:01:25", "name": "[v2,24/31] coco/tdx-host: Add a helper to exchange SPDM messages through DOE", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c1f53a980c1c2f87a5eac5f9ce25ab91a5817f68", "submitter": { "id": 87470, "url": "http://patchwork.ozlabs.org/api/people/87470/?format=api", "name": "Xu Yilun", "email": "yilun.xu@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-25-yilun.xu@linux.intel.com/mbox/", "series": [ { "id": 497793, "url": "http://patchwork.ozlabs.org/api/series/497793/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497793", "date": "2026-03-27T16:01:02", "name": "PCI/TSM: PCIe Link Encryption Establishment via TDX platform services", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497793/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217071/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217071/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51310-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=OOuK9H9K;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-51310-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"OOuK9H9K\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.14", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fj5zQ3y3Xz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 03:42:42 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id 2A19D31A7785\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 16:29:30 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id E397D361DB8;\n\tFri, 27 Mar 2026 16:24:03 +0000 (UTC)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.14])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 950714014B5;\n\tFri, 27 Mar 2026 16:24:02 +0000 (UTC)", "from fmviesa006.fm.intel.com ([10.60.135.146])\n by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Mar 2026 09:24:02 -0700", "from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165])\n by fmviesa006.fm.intel.com with ESMTP; 27 Mar 2026 09:23:58 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774628643; cv=none;\n b=n7Nf6/UILff+j1zF6Ccpaiz3RoGPIzcIsogog7f9oJDYFdTpOcHzP+31wD4JFgnAqfNQs6baBkVwT3sWfrk5BlSJZEWKUw1AOWZ59aGDqGJ+a96DWJExFuu1G1BHjnG+4bN2P49lgIwTowMRpNNeUqwxtrOMkFDMdUaDOKL5hvA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774628643; c=relaxed/simple;\n\tbh=BWgvuTh4wsiASYHYze+pv0K77l3r+BTKGEH1em4ro3s=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=AwHJIm2gC0bqyHijkHVPNVleGLGY8zI8OqadgPwzdztxWxlkI8vxePcRYtSpLdjLoxLugeRMt2yspT+SnV4k9R49Ys/8BNZMVp1Pu0ZoK1ZVQ2ki1XFeje31b9oiim9E56B8F2+/aHe2qfC7DssQH5N0X3+7VrZ90m8IHAUdD4o=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com;\n spf=pass smtp.mailfrom=linux.intel.com;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=OOuK9H9K; arc=none smtp.client-ip=198.175.65.14", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774628642; x=1806164642;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=BWgvuTh4wsiASYHYze+pv0K77l3r+BTKGEH1em4ro3s=;\n b=OOuK9H9K6FQlEaahdcz38NMaZj5GtWcfEOtubz6utyeHa8O0AinedHVi\n QckDdQxVFHvDt4/FevUjx5eQU7sa7NAy+Zdye84CCNRBONJH8Jad7vixr\n vivFOF6a9oqVbWWYo9hgS7eI+/zjhxoEm8R07rvrWUCJpa//iVkiv82wx\n B7UIsnnd3C454OM3hyG+IDBEtU5ql/+tzD7Rxoye5ztS+3vex1Xeu+x+d\n UpwBaqPRndfQDFIvgZw72tib3xMrRZn7in20j67/8333OySQ5StSZXlhm\n ERWKk+TuSiy7r8FyYnf1rboI/3vQM/ghoqcjAeTTnm8Ow5X9cL2OoQ10h\n g==;", "X-CSE-ConnectionGUID": [ "4895LyNvSQubsUrMcJkjHw==", "X0Uz/QmCSSujRQRpRKYfyg==" ], "X-CSE-MsgGUID": [ "0anwO/gySa6aHPrDmMEbYA==", "DY8Zas4iTC+bZkPFfJug2w==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"79565662\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"79565662\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"220516349\"" ], "X-ExtLoop1": "1", "From": "Xu Yilun <yilun.xu@linux.intel.com>", "To": "linux-coco@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdan.j.williams@intel.com,\n\tx86@kernel.org", "Cc": "chao.gao@intel.com,\n\tdave.jiang@intel.com,\n\tbaolu.lu@linux.intel.com,\n\tyilun.xu@linux.intel.com,\n\tyilun.xu@intel.com,\n\tzhenzhong.duan@intel.com,\n\tkvm@vger.kernel.org,\n\trick.p.edgecombe@intel.com,\n\tdave.hansen@linux.intel.com,\n\tkas@kernel.org,\n\txiaoyao.li@intel.com,\n\tvishal.l.verma@intel.com,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 24/31] coco/tdx-host: Add a helper to exchange SPDM\n messages through DOE", "Date": "Sat, 28 Mar 2026 00:01:25 +0800", "Message-Id": "<20260327160132.2946114-25-yilun.xu@linux.intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "References": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Zhenzhong Duan <zhenzhong.duan@intel.com>\n\nTDX host uses this function to exchange TDX Module encrypted data with\ndevices via SPDM. It is unfortunate that TDX passes raw DOE frames with\nheaders included and the PCI DOE core wants payloads separated from\nheaders.\n\nThis conversion code is about the same amount of work as teaching the PCI\nDOE driver to support raw frames. Unless and until another raw frame use\ncase shows up, just do this conversion in the TDX TSM driver.\n\nCo-developed-by: Xu Yilun <yilun.xu@linux.intel.com>\nSigned-off-by: Xu Yilun <yilun.xu@linux.intel.com>\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\nReviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>\n---\n drivers/virt/coco/tdx-host/tdx-host.c | 61 +++++++++++++++++++++++++++\n 1 file changed, 61 insertions(+)", "diff": "diff --git a/drivers/virt/coco/tdx-host/tdx-host.c b/drivers/virt/coco/tdx-host/tdx-host.c\nindex 98ed93ac0153..06f3d194e0a8 100644\n--- a/drivers/virt/coco/tdx-host/tdx-host.c\n+++ b/drivers/virt/coco/tdx-host/tdx-host.c\n@@ -5,11 +5,13 @@\n * Copyright (C) 2025 Intel Corporation\n */\n \n+#include <linux/bitfield.h>\n #include <linux/device/faux.h>\n #include <linux/dmar.h>\n #include <linux/module.h>\n #include <linux/mod_devicetable.h>\n #include <linux/pci.h>\n+#include <linux/pci-doe.h>\n #include <linux/pci-tsm.h>\n #include <linux/tsm.h>\n \n@@ -39,6 +41,65 @@ static struct tdx_tsm_link *to_tdx_tsm_link(struct pci_tsm *tsm)\n \treturn container_of(tsm, struct tdx_tsm_link, pci.base_tsm);\n }\n \n+#define PCI_DOE_DATA_OBJECT_HEADER_1_OFFSET\t0\n+#define PCI_DOE_DATA_OBJECT_HEADER_2_OFFSET\t4\n+#define PCI_DOE_DATA_OBJECT_HEADER_SIZE\t\t8\n+#define PCI_DOE_DATA_OBJECT_PAYLOAD_OFFSET\tPCI_DOE_DATA_OBJECT_HEADER_SIZE\n+\n+#define PCI_DOE_PROTOCOL_SECURE_SPDM\t\t2\n+\n+static int __maybe_unused tdx_spdm_msg_exchange(struct tdx_tsm_link *tlink,\n+\t\t\t\t\t\tvoid *request, size_t request_sz,\n+\t\t\t\t\t\tvoid *response, size_t response_sz)\n+{\n+\tstruct pci_dev *pdev = tlink->pci.base_tsm.pdev;\n+\tvoid *req_pl_addr, *resp_pl_addr;\n+\tsize_t req_pl_sz, resp_pl_sz;\n+\tu32 data, len;\n+\tu16 vendor;\n+\tu8 type;\n+\tint ret;\n+\n+\t/*\n+\t * pci_doe() accept DOE PAYLOAD only but request carries DOE HEADER so\n+\t * shift the buffers, skip DOE HEADER in request buffer, and fill DOE\n+\t * HEADER in response buffer manually.\n+\t */\n+\n+\tdata = le32_to_cpu(*(__le32 *)(request + PCI_DOE_DATA_OBJECT_HEADER_1_OFFSET));\n+\tvendor = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_VID, data);\n+\ttype = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, data);\n+\n+\tdata = le32_to_cpu(*(__le32 *)(request + PCI_DOE_DATA_OBJECT_HEADER_2_OFFSET));\n+\tlen = FIELD_GET(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, data);\n+\n+\treq_pl_sz = len * sizeof(__le32) - PCI_DOE_DATA_OBJECT_HEADER_SIZE;\n+\tresp_pl_sz = response_sz - PCI_DOE_DATA_OBJECT_HEADER_SIZE;\n+\treq_pl_addr = request + PCI_DOE_DATA_OBJECT_HEADER_SIZE;\n+\tresp_pl_addr = response + PCI_DOE_DATA_OBJECT_HEADER_SIZE;\n+\n+\tret = pci_tsm_doe_transfer(pdev, type, req_pl_addr, req_pl_sz,\n+\t\t\t\t resp_pl_addr, resp_pl_sz);\n+\tif (ret < 0) {\n+\t\tpci_err(pdev, \"spdm msg exchange fail %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tdata = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_VID, vendor) |\n+\t FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_1_TYPE, type);\n+\t*(__le32 *)(response + PCI_DOE_DATA_OBJECT_HEADER_1_OFFSET) = cpu_to_le32(data);\n+\n+\tlen = (ret + PCI_DOE_DATA_OBJECT_HEADER_SIZE) / sizeof(__le32);\n+\tdata = FIELD_PREP(PCI_DOE_DATA_OBJECT_HEADER_2_LENGTH, len);\n+\t*(__le32 *)(response + PCI_DOE_DATA_OBJECT_HEADER_2_OFFSET) = cpu_to_le32(data);\n+\n+\tret += PCI_DOE_DATA_OBJECT_HEADER_SIZE;\n+\n+\tpci_dbg(pdev, \"%s complete: vendor 0x%x type 0x%x rsp_sz %d\\n\",\n+\t\t__func__, vendor, type, ret);\n+\treturn ret;\n+}\n+\n static int tdx_tsm_link_connect(struct pci_dev *pdev)\n {\n \treturn -ENXIO;\n", "prefixes": [ "v2", "24/31" ] }