Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217054/?format=api
{ "id": 2217054, "url": "http://patchwork.ozlabs.org/api/patches/2217054/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-10-yilun.xu@linux.intel.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327160132.2946114-10-yilun.xu@linux.intel.com>", "list_archive_url": null, "date": "2026-03-27T16:01:10", "name": "[v2,09/31] x86/virt/tdx: Move tdx_clflush_page() up in the file", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4693dd1b5ebf335dcb09633c78abb406d4000b8b", "submitter": { "id": 87470, "url": "http://patchwork.ozlabs.org/api/people/87470/?format=api", "name": "Xu Yilun", "email": "yilun.xu@linux.intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260327160132.2946114-10-yilun.xu@linux.intel.com/mbox/", "series": [ { "id": 497793, "url": "http://patchwork.ozlabs.org/api/series/497793/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497793", "date": "2026-03-27T16:01:02", "name": "PCI/TSM: PCIe Link Encryption Establishment via TDX platform services", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497793/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217054/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217054/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51295-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=jdLqOKfr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-51295-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"jdLqOKfr\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=198.175.65.14", "smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=linux.intel.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fj5k94K9rz1y1P\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 03:31:13 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 210273167CD5\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 16:25:07 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 002AB36654E;\n\tFri, 27 Mar 2026 16:23:08 +0000 (UTC)", "from mgamail.intel.com (mgamail.intel.com [198.175.65.14])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id BD852367F28;\n\tFri, 27 Mar 2026 16:23:06 +0000 (UTC)", "from fmviesa006.fm.intel.com ([10.60.135.146])\n by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 27 Mar 2026 09:23:06 -0700", "from yilunxu-optiplex-7050.sh.intel.com ([10.239.159.165])\n by fmviesa006.fm.intel.com with ESMTP; 27 Mar 2026 09:23:03 -0700" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774628587; cv=none;\n b=l8tZVybTtom/6cti/zdq5265VsSlJKM5/XYyjam4iwRVo05/gICMZBmtqU7iM6gSym4OlV+qvCFidTq2A15fUGF6mkRc2vVaPX9vNi8xJoG0hhkbsXT1AJi506cRqIi4Fy50W72hrg/13/IVpwcRe/5s34XeJFL9u57hH/4R+zo=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774628587; c=relaxed/simple;\n\tbh=NRFQsWbcpqDGf5zixGV9qrACvFa8LqbAu2Kx6hhchmk=;\n\th=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References:\n\t MIME-Version;\n b=aW/dtmitmdSMq4xX3i6+g9aoUbTFG0WYnKaxD7jEs87ofkeNo1EoTHV4t65oIvrlMqPGTIrFZ6+qG/AY2Leit8UTOCPI7z1BT0OwKJBNAgWAlAOipAYILZEcU6kQ2NacJNnGySY+nDn+OiVqpj1/aKELStpgcD/H82hyrdDglMA=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=linux.intel.com;\n spf=pass smtp.mailfrom=linux.intel.com;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=jdLqOKfr; arc=none smtp.client-ip=198.175.65.14", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774628586; x=1806164586;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=NRFQsWbcpqDGf5zixGV9qrACvFa8LqbAu2Kx6hhchmk=;\n b=jdLqOKfrLH5BvsTdi1FafVLOp5Ul829yFXXtTDZKwYaaF3fiQuAl9Wm3\n qolDGX1flfRBCt8gPdCPJcFi8zmjIffZAIYOSXSbW+6mjH9+4dLTDiLPB\n IaTG6jPkRJQ0YxaWnViCPIaG5nyKMWLCBFYYNjgnnFaBEPO7bqemVjcS9\n z2t1gK9HCEqQV/oHEK0vZbKMpJJgjroK9rwq9vYPsoF0ef4/XxL2oCT2a\n wh66gKWZLSpVpbKjd0OazfyOlvBnX57f2LRa7Q49Z17N813D5CeYj1PLh\n 6Ymwh4+NTQzzfp0cJENk/3omMp0sG2yd7TP+eDVTjfnDmF9/+mXh15Yof\n Q==;", "X-CSE-ConnectionGUID": [ "N5CHLIiwTU+kTESlG3PceQ==", "Je9XVUSpSNCJAKe+QF6ErQ==" ], "X-CSE-MsgGUID": [ "14u/s5FzSG6KBFyrqLHZbw==", "5Sf7lSvYT3SPjffYmyVSJw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"79565540\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"79565540\"", "E=Sophos;i=\"6.23,144,1770624000\";\n d=\"scan'208\";a=\"220516170\"" ], "X-ExtLoop1": "1", "From": "Xu Yilun <yilun.xu@linux.intel.com>", "To": "linux-coco@lists.linux.dev,\n\tlinux-pci@vger.kernel.org,\n\tdan.j.williams@intel.com,\n\tx86@kernel.org", "Cc": "chao.gao@intel.com,\n\tdave.jiang@intel.com,\n\tbaolu.lu@linux.intel.com,\n\tyilun.xu@linux.intel.com,\n\tyilun.xu@intel.com,\n\tzhenzhong.duan@intel.com,\n\tkvm@vger.kernel.org,\n\trick.p.edgecombe@intel.com,\n\tdave.hansen@linux.intel.com,\n\tkas@kernel.org,\n\txiaoyao.li@intel.com,\n\tvishal.l.verma@intel.com,\n\tlinux-kernel@vger.kernel.org", "Subject": "[PATCH v2 09/31] x86/virt/tdx: Move tdx_clflush_page() up in the file", "Date": "Sat, 28 Mar 2026 00:01:10 +0800", "Message-Id": "<20260327160132.2946114-10-yilun.xu@linux.intel.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "References": "<20260327160132.2946114-1-yilun.xu@linux.intel.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "Prepare to add more callers earlier in this file, so move this\nfunction up in advance.\n\nSigned-off-by: Xu Yilun <yilun.xu@linux.intel.com>\n---\n arch/x86/virt/vmx/tdx/tdx.c | 22 +++++++++++-----------\n 1 file changed, 11 insertions(+), 11 deletions(-)", "diff": "diff --git a/arch/x86/virt/vmx/tdx/tdx.c b/arch/x86/virt/vmx/tdx/tdx.c\nindex 0c5d6bdd810f..4fb56bb442f0 100644\n--- a/arch/x86/virt/vmx/tdx/tdx.c\n+++ b/arch/x86/virt/vmx/tdx/tdx.c\n@@ -1502,6 +1502,17 @@ static int init_tdmrs(struct tdmr_info_list *tdmr_list)\n \treturn 0;\n }\n \n+/*\n+ * The TDX module exposes a CLFLUSH_BEFORE_ALLOC bit to specify whether\n+ * a CLFLUSH of pages is required before handing them to the TDX module.\n+ * Be conservative and make the code simpler by doing the CLFLUSH\n+ * unconditionally.\n+ */\n+static void tdx_clflush_page(struct page *page)\n+{\n+\tclflush_cache_range(page_to_virt(page), PAGE_SIZE);\n+}\n+\n static int init_tdx_module(void)\n {\n \tint ret;\n@@ -1936,17 +1947,6 @@ static inline u64 tdx_tdr_pa(struct tdx_td *td)\n \treturn page_to_phys(td->tdr_page);\n }\n \n-/*\n- * The TDX module exposes a CLFLUSH_BEFORE_ALLOC bit to specify whether\n- * a CLFLUSH of pages is required before handing them to the TDX module.\n- * Be conservative and make the code simpler by doing the CLFLUSH\n- * unconditionally.\n- */\n-static void tdx_clflush_page(struct page *page)\n-{\n-\tclflush_cache_range(page_to_virt(page), PAGE_SIZE);\n-}\n-\n noinstr u64 tdh_vp_enter(struct tdx_vp *td, struct tdx_module_args *args)\n {\n \targs->rcx = td->tdvpr_pa;\n", "prefixes": [ "v2", "09/31" ] }