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GET /api/patches/2217045/?format=api
{ "id": 2217045, "url": "http://patchwork.ozlabs.org/api/patches/2217045/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327141029.628483-3-uros.stajic@htecgroup.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327141029.628483-3-uros.stajic@htecgroup.com>", "list_archive_url": null, "date": "2026-03-27T14:12:09", "name": "[v6,2/7] board: boston-riscv: Add initial support for P8700 Boston board", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2ff1f77f3894f84542710664f4161d33e91d37ce", "submitter": { "id": 90991, "url": "http://patchwork.ozlabs.org/api/people/90991/?format=api", "name": "Uros Stajic", "email": "uros.stajic@htecgroup.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327141029.628483-3-uros.stajic@htecgroup.com/mbox/", "series": [ { "id": 497792, "url": "http://patchwork.ozlabs.org/api/series/497792/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497792", "date": "2026-03-27T14:10:46", "name": "riscv: Add support for P8700 platform on Boston board", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/497792/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217045/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": 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b=paXxURgfl6S0x/nb/GsbeoyYvsSLaw9yJgza02H9Ka/LmEA11gAZwZR8GViogxte3IWnOMIcLz5glucVNJ0h3OnAJwWTZqI2ZK1jgm4o0xACMC+NxmAIMDg6R8qBL6q19NpzxAouM9Qu6+h/YgIVW38g4F5at8DAWq5FY1b9rNQFVsql5Ea91wAQyZni5JePodb8JKt/jJ2qMT5rgLJ3oB81AnJX480jf0HBU2CanTZIsChisCy/HlhUNO+nxHS4m7oFhi0RU01OMrhjBSsgQQzeNGSsKd51VqfABBUqCPK+CFmNbMtFB/DMLFjavO3bVIHaWtjXFa6fqDnBpUDK+A==", "From": "Uros Stajic <uros.stajic@htecgroup.com>", "To": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>", "CC": "Djordje Todorovic <Djordje.Todorovic@htecgroup.com>, Chao-ying Fu\n <cfu@mips.com>, Uros Stajic <uros.stajic@htecgroup.com>", "Subject": "[PATCH v6 2/7] board: boston-riscv: Add initial support for P8700\n Boston board", "Thread-Topic": "[PATCH v6 2/7] board: boston-riscv: Add initial support for\n P8700 Boston board", "Thread-Index": "AQHcvfOzrd8wJ8stDE+IQR7gNy02mw==", "Date": "Fri, 27 Mar 2026 14:12:09 +0000", "Message-ID": "<20260327141029.628483-3-uros.stajic@htecgroup.com>", "References": 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"Content-Type": "text/plain; charset=\"iso-8859-1\"", "Content-Transfer-Encoding": "quoted-printable", "MIME-Version": "1.0", "X-OriginatorOrg": "htecgroup.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "PA3PR09MB8140.eurprd09.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9558d634-4b02-4f5a-b5dd-08de8c0ad5c9", "X-MS-Exchange-CrossTenant-originalarrivaltime": "27 Mar 2026 14:12:09.6933 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9f85665b-7efd-4776-9dfe-b6bfda2565ee", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n msE1Mi41Uap/a+HkC0fUKHoI9bQElCOAXhcZRF8JZRcroVrdlyP/7RN+iv/TGIfL+Wwz9z0mzDm+hHbslOl3m01RBMqcqYWaKAvAQqyTpb8=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DU0PR09MB8167", "X-Mailman-Approved-At": "Fri, 27 Mar 2026 17:24:54 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Chao-ying Fu <cfu@mips.com>\n\nImplement initial board-level support for the P8700 Boston SoC.\n\nSigned-off-by: Chao-ying Fu <cfu@mips.com>\nSigned-off-by: Uros Stajic <uros.stajic@htecgroup.com>\n---\n arch/riscv/Kconfig | 11 +\n arch/riscv/dts/Makefile | 1 +\n arch/riscv/dts/boston-p8700.dts | 264 ++++++++++++++++++++++++\n board/mips/boston-riscv/Kconfig | 43 ++++\n board/mips/boston-riscv/MAINTAINERS | 9 +\n board/mips/boston-riscv/Makefile | 8 +\n board/mips/boston-riscv/boston-lcd.h | 20 ++\n board/mips/boston-riscv/boston-regs.h | 42 ++++\n board/mips/boston-riscv/boston-riscv.c | 48 +++++\n board/mips/boston-riscv/checkboard.c | 43 ++++\n board/mips/boston-riscv/config.mk | 15 ++\n board/mips/boston-riscv/lowlevel_init.S | 18 ++\n board/mips/boston-riscv/reset.c | 15 ++\n configs/boston-p8700_defconfig | 98 +++++++++\n drivers/clk/Kconfig | 2 +-\n include/configs/boston-riscv.h | 9 +\n 16 files changed, 645 insertions(+), 1 deletion(-)\n create mode 100644 arch/riscv/dts/boston-p8700.dts\n create mode 100644 board/mips/boston-riscv/Kconfig\n create mode 100644 board/mips/boston-riscv/MAINTAINERS\n create mode 100644 board/mips/boston-riscv/Makefile\n create mode 100644 board/mips/boston-riscv/boston-lcd.h\n create mode 100644 board/mips/boston-riscv/boston-regs.h\n create mode 100644 board/mips/boston-riscv/boston-riscv.c\n create mode 100644 board/mips/boston-riscv/checkboard.c\n create mode 100644 board/mips/boston-riscv/config.mk\n create mode 100644 board/mips/boston-riscv/lowlevel_init.S\n create mode 100644 board/mips/boston-riscv/reset.c\n create mode 100644 configs/boston-p8700_defconfig\n create mode 100644 include/configs/boston-riscv.h", "diff": "diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig\nindex 9e2cbe775d2..1d27e999340 100644\n--- a/arch/riscv/Kconfig\n+++ b/arch/riscv/Kconfig\n@@ -61,6 +61,16 @@ config TARGET_XILINX_MBV\n config TARGET_ASPEED_AST2700_IBEX\n \tbool \"Support Ibex RISC-V cores on Aspeed AST2700 SoC\"\n \n+config TARGET_MIPS_BOSTON\n+\tbool \"Support Mips Boston Board\"\n+\tselect DM\n+\tselect DM_EVENT\n+\tselect DM_GPIO\n+\tselect DM_SERIAL\n+\tselect OF_CONTROL\n+\tselect DISTRO_DEFAULTS\n+\timply CMD_DM\n+\n endchoice\n \n config SYS_ICACHE_OFF\n@@ -119,6 +129,7 @@ source \"board/spacemit/bananapi-f3/Kconfig\"\n source \"board/starfive/visionfive2/Kconfig\"\n source \"board/thead/th1520_lpi4a/Kconfig\"\n source \"board/xilinx/mbv/Kconfig\"\n+source \"board/mips/boston-riscv/Kconfig\"\n \n # platform-specific options below\n source \"arch/riscv/cpu/andes/Kconfig\"\ndiff --git a/arch/riscv/dts/Makefile b/arch/riscv/dts/Makefile\nindex 9b347fc3b50..63e3bd4c95f 100644\n--- a/arch/riscv/dts/Makefile\n+++ b/arch/riscv/dts/Makefile\n@@ -16,6 +16,7 @@ dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv32.dtb\n dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-mbv64.dtb\n dtb-$(CONFIG_TARGET_XILINX_MBV) += xilinx-binman.dtb\n dtb-$(CONFIG_TARGET_ASPEED_AST2700_IBEX) += ast2700-ibex.dtb\n+dtb-$(CONFIG_TARGET_MIPS_BOSTON) += boston-p8700.dtb\n \n include $(srctree)/scripts/Makefile.dts\n \ndiff --git a/arch/riscv/dts/boston-p8700.dts b/arch/riscv/dts/boston-p8700.dts\nnew file mode 100644\nindex 00000000000..8207017c6ce\n--- /dev/null\n+++ b/arch/riscv/dts/boston-p8700.dts\n@@ -0,0 +1,264 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\n+ */\n+\n+/dts-v1/;\n+\n+#include <dt-bindings/clock/boston-clock.h>\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/interrupt-controller/irq.h>\n+#include <dt-bindings/interrupt-controller/mips-gic.h>\n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\tmodel = \"p8700\";\n+\tcompatible = \"mips,p8700-boston\";\n+\n+\taliases {\n+\t\tserial0 = &uart0;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\ttimebase-frequency = <25000000>;\n+\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"mips,p8700\", \"riscv\";\n+\t\t\treg = <0>;\n+\t\t\tmmu-type = \"riscv,sv39\";\n+\t\t\triscv,isa-extensions = \"i\", \"m\", \"a\", \"f\", \"d\", \"c\", \"zba\", \"zbb\";\n+\t\t\tclocks = <&clk_boston BOSTON_CLK_CPU>;\n+\t\t\tclock-frequency = <25000000>;\n+\t\t\tbootph-all;\n+\t\t\tstatus = \"okay\";\n+\n+\t\t\tcpu0_intc: interrupt-controller {\n+\t\t\t\tcompatible = \"riscv,cpu-intc\";\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <1>;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tmemory@0 {\n+\t\tdevice_type = \"memory\";\n+\t\treg = <0x80000000 0x80000000>;\n+\t};\n+\n+\ttimer@16154000 {\n+\t\tcompatible = \"riscv,aclint-mtimer\";\n+\t\treg = <0x16108050 0x8>,\n+\t\t\t <0x16154000 0x7ff8>;\n+\t\tinterrupts-extended = <&cpu0_intc 7>;\n+\t};\n+\n+\tgic: interrupt-controller {\n+\t\tcompatible = \"mti,gic\";\n+\n+\t\tinterrupt-controller;\n+\t\t#interrupt-cells = <3>;\n+\t};\n+\n+\tpci0: pci@10000000 {\n+\t\tdevice_type = \"pci\";\n+\t\tcompatible = \"xlnx,axi-pcie-host-1.00.a\";\n+\t\treg = <0x10000000 0x2000000>;\n+\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\t#interrupt-cells = <1>;\n+\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\tranges = <0x02000000 0 0x40000000\n+\t\t\t 0x40000000 0 0x40000000>;\n+\n+\t\tbus-range = <0x00 0xff>;\n+\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &pci0_intc 1>,\n+\t\t\t\t<0 0 0 2 &pci0_intc 2>,\n+\t\t\t\t<0 0 0 3 &pci0_intc 3>,\n+\t\t\t\t<0 0 0 4 &pci0_intc 4>;\n+\n+\t\tstatus = \"disabled\";\n+\n+\t\tpci0_intc: interrupt-controller {\n+\t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t};\n+\t};\n+\n+\tpci1: pci@12000000 {\n+\t\tdevice_type = \"pci\";\n+\t\tcompatible = \"xlnx,axi-pcie-host-1.00.a\";\n+\t\treg = <0x12000000 0x2000000>;\n+\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\t#interrupt-cells = <1>;\n+\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\tranges = <0x02000000 0 0x20000000\n+\t\t\t 0x20000000 0 0x20000000>;\n+\n+\t\tbus-range = <0x00 0xff>;\n+\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &pci1_intc 1>,\n+\t\t\t\t<0 0 0 2 &pci1_intc 2>,\n+\t\t\t\t<0 0 0 3 &pci1_intc 3>,\n+\t\t\t\t<0 0 0 4 &pci1_intc 4>;\n+\n+\t\tstatus = \"disabled\";\n+\n+\t\tpci1_intc: interrupt-controller {\n+\t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t};\n+\t};\n+\n+\tpci2: pci@14000000 {\n+\t\tdevice_type = \"pci\";\n+\t\tcompatible = \"xlnx,axi-pcie-host-1.00.a\";\n+\t\treg = <0x14000000 0x2000000>;\n+\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\t#interrupt-cells = <1>;\n+\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\tranges = <0x02000000 0 0x16000000\n+\t\t\t 0x16000000 0 0x100000>;\n+\n+\t\tbus-range = <0x00 0xff>;\n+\n+\t\tinterrupt-map-mask = <0 0 0 7>;\n+\t\tinterrupt-map = <0 0 0 1 &pci2_intc 1>,\n+\t\t\t\t<0 0 0 2 &pci2_intc 2>,\n+\t\t\t\t<0 0 0 3 &pci2_intc 3>,\n+\t\t\t\t<0 0 0 4 &pci2_intc 4>;\n+\n+\t\tpci2_intc: interrupt-controller {\n+\t\t\tinterrupt-controller;\n+\t\t\t#address-cells = <0>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t};\n+\n+\t\tpci2_root@0,0,0 {\n+\t\t\tcompatible = \"pci10ee,7021\", \"pci-bridge\";\n+\t\t\treg = <0x00000000 0 0 0 0>;\n+\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\t#interrupt-cells = <1>;\n+\n+\t\t\teg20t_bridge@1,0,0 {\n+\t\t\t\tcompatible = \"pci8086,8800\", \"pci-bridge\";\n+\t\t\t\treg = <0x00010000 0 0 0 0>;\n+\n+\t\t\t\t#address-cells = <3>;\n+\t\t\t\t#size-cells = <2>;\n+\t\t\t\t#interrupt-cells = <1>;\n+\n+\t\t\t\teg20t_mac@2,0,1 {\n+\t\t\t\t\tcompatible = \"pci8086,8802\", \"intel,pch-gbe\";\n+\t\t\t\t\treg = <0x00020100 0 0 0 0>;\n+\t\t\t\t\tphy-reset-gpios = <&eg20t_gpio 6 GPIO_ACTIVE_LOW>;\n+\t\t\t\t};\n+\n+\t\t\t\teg20t_gpio: eg20t_gpio@2,0,2 {\n+\t\t\t\t\tcompatible = \"pci8086,8803\", \"intel,eg20t-gpio\";\n+\t\t\t\t\treg = <0x00020200 0 0 0 0>;\n+\n+\t\t\t\t\tgpio-controller;\n+\t\t\t\t\t#gpio-cells = <2>;\n+\t\t\t\t};\n+\n+\t\t\t\tmmc0: mmc@2,4,0 {\n+\t\t\t\t\tcompatible = \"intel,apl-sd\";\n+\t\t\t\t\treg = <0x00022000 0 0 0 0>;\n+\t\t\t\t};\n+\n+\t\t\t\tmmc1: mmc@2,4,1 {\n+\t\t\t\t\tcompatible = \"intel,apl-sd\";\n+\t\t\t\t\treg = <0x00022100 0 0 0 0>;\n+\t\t\t\t};\n+\n+\t\t\t\teg20t_i2c@2,12,2 {\n+\t\t\t\t\tcompatible = \"pci8086,8817\";\n+\t\t\t\t\treg = <0x00026200 0 0 0 0>;\n+\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <0>;\n+\n+\t\t\t\t\trtc@0x68 {\n+\t\t\t\t\t\tcompatible = \"st,m41t81s\";\n+\t\t\t\t\t\treg = <0x68>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tplat_regs: system-controller@17ffd000 {\n+\t\tcompatible = \"img,boston-platform-regs\", \"syscon\";\n+\t\treg = <0x17ffd000 0x1000>;\n+\t\tbootph-all;\n+\t};\n+\n+\tclk_boston: clock {\n+\t\tcompatible = \"img,boston-clock\";\n+\t\t#clock-cells = <1>;\n+\t\tregmap = <&plat_regs>;\n+\t\tbootph-all;\n+\t};\n+\n+\treboot: syscon-reboot {\n+\t\tcompatible = \"syscon-reboot\";\n+\t\tregmap = <&plat_regs>;\n+\t\toffset = <0x10>;\n+\t\tmask = <0x10>;\n+\t};\n+\n+\tuart0: uart@17ffe000 {\n+\t\tcompatible = \"ns16550a\";\n+\t\treg = <0x17ffe000 0x1000>;\n+\t\treg-shift = <2>;\n+\t\treg-io-width = <4>;\n+\n+\t\tinterrupt-parent = <&gic>;\n+\t\tinterrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\tclocks = <&clk_boston BOSTON_CLK_SYS>;\n+\t\tclock-frequency = <25000000>;\n+\n+\t\tbootph-all;\n+\t};\n+\n+\tlcd: lcd@17fff000 {\n+\t\tcompatible = \"img,boston-lcd\";\n+\t\treg = <0x17fff000 0x8>;\n+\t};\n+\n+\tflash@18000000 {\n+\t\tcompatible = \"cfi-flash\";\n+\t\treg = <0x18000000 0x8000000>;\n+\t\tbank-width = <2>;\n+\t};\n+};\ndiff --git a/board/mips/boston-riscv/Kconfig b/board/mips/boston-riscv/Kconfig\nnew file mode 100644\nindex 00000000000..bada4b6752d\n--- /dev/null\n+++ b/board/mips/boston-riscv/Kconfig\n@@ -0,0 +1,43 @@\n+if TARGET_MIPS_BOSTON\n+\n+config SYS_BOARD\n+\tdefault \"boston-riscv\"\n+\n+config SYS_VENDOR\n+\tdefault \"mips\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"boston-riscv\"\n+\n+config SYS_CPU\n+\tdefault \"p8700\"\n+\n+config BOARD_SPECIFIC_OPTIONS\n+\tdef_bool y\n+\tselect P8700_RISCV\n+\timply SYS_NS16550\n+\n+config SYS_CACHELINE_SIZE\n+\tdefault 64\n+\n+config SYS_SDRAM_BASE\n+\thex\n+\tdefault 0x80000000\n+\n+config SYS_INIT_SP_ADDR\n+\thex\n+\tdefault 0x80200000\n+\n+config STANDALONE_LOAD_ADDR\n+\thex\n+\tdefault 0x80200000\n+\n+config SYS_MAX_FLASH_BANKS_DETECT\n+\tbool\n+\tdefault y\n+\n+config PHY_REALTEK\n+\tbool\n+\tdefault y\n+\n+endif\ndiff --git a/board/mips/boston-riscv/MAINTAINERS b/board/mips/boston-riscv/MAINTAINERS\nnew file mode 100644\nindex 00000000000..d03491d0f0c\n--- /dev/null\n+++ b/board/mips/boston-riscv/MAINTAINERS\n@@ -0,0 +1,9 @@\n+BOSTON-RISCV BOARD\n+M:\tChao-ying Fu <cfu@mips.com>\n+S:\tMaintained\n+F:\tboard/mips/boston-riscv/\n+F:\tinclude/configs/boston-riscv.h\n+F:\tarch/riscv/cpu/p8700/\n+F:\tarch/riscv/include/asm/arch-p8700/\n+F:\tconfigs/boston-p8700_defconfig\n+F:\tarch/riscv/dts/boston-p8700.dts\ndiff --git a/board/mips/boston-riscv/Makefile b/board/mips/boston-riscv/Makefile\nnew file mode 100644\nindex 00000000000..0615c677d23\n--- /dev/null\n+++ b/board/mips/boston-riscv/Makefile\n@@ -0,0 +1,8 @@\n+# SPDX-License-Identifier: GPL-2.0\n+#\n+# Copyright (C) 2016 Imagination Technologies\n+\n+obj-y += boston-riscv.o\n+obj-y += checkboard.o\n+obj-y += lowlevel_init.o\n+obj-y += reset.o\ndiff --git a/board/mips/boston-riscv/boston-lcd.h b/board/mips/boston-riscv/boston-lcd.h\nnew file mode 100644\nindex 00000000000..5f5cd0fe126\n--- /dev/null\n+++ b/board/mips/boston-riscv/boston-lcd.h\n@@ -0,0 +1,20 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2016 Imagination Technologies\n+ */\n+\n+#ifndef __BOARD_BOSTON_LCD_H__\n+#define __BOARD_BOSTON_LCD_H__\n+\n+/**\n+ * lowlevel_display() - Display a message on Boston's LCD\n+ * @msg: The string to display\n+ *\n+ * Display the string @msg on the 7 character LCD display of the Boston board.\n+ * This is typically used for debug or to present some form of status\n+ * indication to the user, allowing faults to be identified when things go\n+ * wrong early enough that the UART isn't up.\n+ */\n+void lowlevel_display(const char msg[static 8]);\n+\n+#endif /* __BOARD_BOSTON_LCD_H__ */\ndiff --git a/board/mips/boston-riscv/boston-regs.h b/board/mips/boston-riscv/boston-regs.h\nnew file mode 100644\nindex 00000000000..60343368a68\n--- /dev/null\n+++ b/board/mips/boston-riscv/boston-regs.h\n@@ -0,0 +1,42 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2016 Imagination Technologies\n+ */\n+\n+#ifndef __BOARD_BOSTON_REGS_H__\n+#define __BOARD_BOSTON_REGS_H__\n+\n+#ifndef BOSTON_PLAT_BASE\n+#define BOSTON_PLAT_BASE\t\t(0x17ffd000)\n+#endif\n+#define BOSTON_LCD_BASE\t\t\t(0x17fff000)\n+\n+/*\n+ * Platform Register Definitions\n+ */\n+#define BOSTON_PLAT_CORE_CL\t\t(BOSTON_PLAT_BASE + 0x04)\n+\n+#define BOSTON_PLAT_SOFT_RST\t\t(BOSTON_PLAT_BASE + 0x10)\n+#define BOSTON_PLAT_SOFT_RST_SYSTEM\t(0x1 << 4)\n+\n+#define BOSTON_PLAT_DDR3STAT\t\t(BOSTON_PLAT_BASE + 0x14)\n+#define BOSTON_PLAT_DDR3STAT_CALIB\t(0x1 << 2)\n+\n+#define BOSTON_PLAT_BUILDCFG0 (BOSTON_PLAT_BASE + 0x34)\n+#define BOSTON_PLAT_BUILDCFG0_IOCU (0x1 << 0)\n+#define BOSTON_PLAT_BUILDCFG0_PCIE0 (0x1 << 1)\n+#define BOSTON_PLAT_BUILDCFG0_PCIE1 (0x1 << 2)\n+#define BOSTON_PLAT_BUILDCFG0_PCIE2 (0x1 << 3)\n+#define BOSTON_PLAT_BUILDCFG0_CFG_LTR (0xf << 4)\n+#define BOSTON_PLAT_BUILDCFG0_CFG_NUM (0xff << 8)\n+#define BOSTON_PLAT_BUILDCFG0_DP (0x1 << 24)\n+#define BOSTON_PLAT_BUILDCFG0_DP_MULT (0xf << 28)\n+\n+#define BOSTON_PLAT_DDRCONF0\t\t(BOSTON_PLAT_BASE + 0x38)\n+#define BOSTON_PLAT_DDRCONF0_SIZE\t(0xf << 0)\n+\n+#define BOSTON_PLAT_NOCPCIE0ADDR (BOSTON_PLAT_BASE + 0x3c)\n+#define BOSTON_PLAT_NOCPCIE1ADDR (BOSTON_PLAT_BASE + 0x40)\n+#define BOSTON_PLAT_NOCPCIE2ADDR (BOSTON_PLAT_BASE + 0x44) \n+\n+#endif /* __BOARD_BOSTON_REGS_H__ */\ndiff --git a/board/mips/boston-riscv/boston-riscv.c b/board/mips/boston-riscv/boston-riscv.c\nnew file mode 100644\nindex 00000000000..f3fd2ec8348\n--- /dev/null\n+++ b/board/mips/boston-riscv/boston-riscv.c\n@@ -0,0 +1,48 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2016 Imagination Technologies\n+ */\n+\n+#include \"boston-regs.h\"\n+#include <asm/encoding.h>\n+#include <asm/io.h>\n+#include <linux/types.h>\n+#include <asm/arch-p8700/p8700.h>\n+\n+#define PMACFG0_PMP3_SHIFT\t24\n+#define PMACFG0_PMP3_MASK\t(0xffUL << PMACFG0_PMP3_SHIFT)\n+#define BOSTON_IOCU_NOC_OFFSET\t0x10\n+\n+int board_early_init_r(void)\n+{\n+\tif (!IS_ENABLED(CONFIG_RISCV_MMODE))\n+\t\treturn 0;\n+\tulong pmacfg0 = csr_read(CSR_PMACFG0);\n+\n+\t/*\n+\t * Make the flash region (PMA entry corresponding to pmp3) uncached by\n+\t * setting the CCA field in CSR_PMACFG0[31:24].\n+\t */\n+\tpmacfg0 &= ~PMACFG0_PMP3_MASK;\n+\tpmacfg0 |= (ulong)CCA_CACHE_DISABLE << PMACFG0_PMP3_SHIFT;\n+\n+\tcsr_write(CSR_PMACFG0, pmacfg0);\n+\tasm volatile (\"fence\" ::: \"memory\");\n+\n+\treturn 0;\n+}\n+\n+void wait_ddr_calib(void)\n+{\n+\twhile (!(readl((void __iomem *)BOSTON_PLAT_DDR3STAT) &\n+\t\t BOSTON_PLAT_DDR3STAT_CALIB)) {\n+\t\t/* busy-wait */\n+\t}\n+}\n+\n+void setup_pcie_dma_map(void)\n+{\n+\twritel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE0ADDR);\n+\twritel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE1ADDR);\n+\twritel(0x00, (void __iomem *)BOSTON_PLAT_NOCPCIE2ADDR);\n+}\ndiff --git a/board/mips/boston-riscv/checkboard.c b/board/mips/boston-riscv/checkboard.c\nnew file mode 100644\nindex 00000000000..c7bf6734433\n--- /dev/null\n+++ b/board/mips/boston-riscv/checkboard.c\n@@ -0,0 +1,43 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2016 Imagination Technologies\n+ */\n+\n+#include \"boston-lcd.h\"\n+#include \"boston-regs.h\"\n+#include <init.h>\n+#include <asm/io.h>\n+#include <asm/arch-p8700/p8700.h>\n+\n+int checkboard(void)\n+{\n+\tu32 changelist, cfg, core, uarch;\n+\tu64 marchid;\n+\n+\tlowlevel_display(\"U-boot \");\n+\n+\tprintf(\"Board: Mips Boston RISC-V\\n\");\n+\n+\tchangelist = __raw_readl((uint32_t *)BOSTON_PLAT_CORE_CL);\n+\tif (changelist > 1) {\n+\t\tasm volatile (\"csrr %0, marchid\" : \"=r\"(marchid)::);\n+\t\tcore = (marchid >> MARCHID_CLASS_SHIFT) & MARCHID_CLASS_MASK;\n+\t\tuarch = (marchid >> MARCHID_UARCH_SHIFT) & MARCHID_UARCH_MASK;\n+\n+\t\tprintf(\"Core: class%x uarch%x cl%x\", core, uarch, changelist);\n+\n+\t\tcfg = __raw_readl((uint32_t *)BOSTON_PLAT_BUILDCFG0);\n+\t\tif (cfg & BOSTON_PLAT_BUILDCFG0_CFG_NUM)\n+\t\t\tprintf(\" config %u\",\n+\t\t\t (cfg & BOSTON_PLAT_BUILDCFG0_CFG_NUM) >> 8);\n+\t\tif (cfg & BOSTON_PLAT_BUILDCFG0_CFG_LTR)\n+\t\t\tprintf(\"%c\",\n+\t\t\t 'a' + ((cfg & BOSTON_PLAT_BUILDCFG0_CFG_LTR) >> 4) - 1);\n+\t\tif (cfg & BOSTON_PLAT_BUILDCFG0_DP)\n+\t\t\tprintf(\", x%u debug port\",\n+\t\t\t (cfg & BOSTON_PLAT_BUILDCFG0_DP_MULT) >> 28);\n+\t\tprintf(\"\\n\");\n+\t}\n+\n+\treturn 0;\n+}\ndiff --git a/board/mips/boston-riscv/config.mk b/board/mips/boston-riscv/config.mk\nnew file mode 100644\nindex 00000000000..c1e242f1088\n--- /dev/null\n+++ b/board/mips/boston-riscv/config.mk\n@@ -0,0 +1,15 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+\n+quiet_cmd_srec_cat = SRECCAT $@\n+ cmd_srec_cat = srec_cat -output $@ -$2 \\\n+\t\t\t$< -binary \\\n+\t\t\t-fill 0x00 -within $< -binary -range-pad 16 \\\n+\t\t\t-offset $3\n+\n+u-boot.mcs: u-boot.bin\n+\t$(call cmd,srec_cat,intel,0x7c00000)\n+\n+# if srec_cat is present build u-boot.mcs by default\n+has_srec_cat = $(call try-run,srec_cat -VERSion,y,n)\n+INPUTS-$(has_srec_cat) += u-boot.mcs\n+CLEAN_FILES += u-boot.mcs\ndiff --git a/board/mips/boston-riscv/lowlevel_init.S b/board/mips/boston-riscv/lowlevel_init.S\nnew file mode 100644\nindex 00000000000..8fa85749e40\n--- /dev/null\n+++ b/board/mips/boston-riscv/lowlevel_init.S\n@@ -0,0 +1,18 @@\n+/* SPDX-License-Identifier: GPL-2.0 */\n+/*\n+ * Copyright (C) 2016 Imagination Technologies\n+ */\n+\n+#include \"boston-regs.h\"\n+\n+.data\n+\n+msg_ddr_cal:\t.ascii \"DDR Cal \"\n+msg_ddr_ok:\t.ascii \"DDR OK \"\n+\n+.text\n+\n+\t.globl lowlevel_display\n+lowlevel_display:\n+\tli\tt0, BOSTON_LCD_BASE\n+\tjr\tra\ndiff --git a/board/mips/boston-riscv/reset.c b/board/mips/boston-riscv/reset.c\nnew file mode 100644\nindex 00000000000..8e7e0572aad\n--- /dev/null\n+++ b/board/mips/boston-riscv/reset.c\n@@ -0,0 +1,15 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * Copyright (C) 2017 Imagination Technologies\n+ */\n+\n+#include \"boston-regs.h\"\n+#include <asm/io.h>\n+#include <linux/delay.h>\n+\n+void _machine_restart(void)\n+{\n+\twritel(BOSTON_PLAT_SOFT_RST_SYSTEM, (void __iomem *)BOSTON_PLAT_SOFT_RST);\n+\n+\tudelay(1000);\n+}\ndiff --git a/configs/boston-p8700_defconfig b/configs/boston-p8700_defconfig\nnew file mode 100644\nindex 00000000000..498ccb15b4c\n--- /dev/null\n+++ b/configs/boston-p8700_defconfig\n@@ -0,0 +1,98 @@\n+CONFIG_RISCV=y\n+CONFIG_SYS_TEXT_BASE=0x1fc00000\n+CONFIG_ENV_SIZE=0x40000\n+CONFIG_ENV_SECT_SIZE=0x40000\n+CONFIG_TARGET_MIPS_BOSTON=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"boston-p8700\"\n+\n+CONFIG_DISTRO_DEFAULTS=y\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+CONFIG_FIT_BEST_MATCH=y\n+CONFIG_OF_STDOUT_VIA_ALIAS=y\n+CONFIG_SYS_PROMPT=\"boston # \"\n+CONFIG_CMD_GREPENV=y\n+CONFIG_CMD_MEMTEST=y\n+CONFIG_SYS_MEMTEST_START=0x80000000\n+CONFIG_SYS_MEMTEST_END=0x90000000\n+CONFIG_BOOTDELAY=-1\n+\n+CONFIG_NR_DRAM_BANKS=1\n+CONFIG_ARCH_RV64I=y\n+CONFIG_DISPLAY_CPUINFO=y\n+CONFIG_DISPLAY_BOARDINFO=y\n+CONFIG_BOARD_INIT=n\n+#CONFIG_CMD_BOOTEFI_SELFTEST=y\n+#CONFIG_CMD_NVEDIT_EFI=y\n+CONFIG_CMD_MII=y\n+# CONFIG_OF_PRIOR_STAGE=y\n+CONFIG_DM_MTD=y\n+CONFIG_SMP=n\n+CONFIG_XIP=y\n+CONFIG_CLK_BOSTON=y\n+CONFIG_RISCV_ISA_C=n\n+CONFIG_SHOW_REGS=y\n+CONFIG_SYS_NS16550=y\n+\n+CONFIG_CMD_PCI=y\n+CONFIG_CMD_SNTP=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_LINK_LOCAL=y\n+CONFIG_CMD_TIME=y\n+CONFIG_CMD_EXT4_WRITE=y\n+CONFIG_ENV_IS_IN_FLASH=y\n+CONFIG_ENV_ADDR=0x1ffc0000\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_MTD=y\n+CONFIG_MTD_NOR_FLASH=y\n+CONFIG_FLASH_CFI_DRIVER=y\n+CONFIG_CFI_FLASH=y\n+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y\n+CONFIG_SYS_FLASH_USE_PROTECTION=y\n+CONFIG_SYS_FLASH_CFI=y\n+CONFIG_SYS_FLASH_PROTECTION=y\n+CONFIG_DM_ETH=y\n+CONFIG_PCH_GBE=y\n+CONFIG_PCI=y\n+CONFIG_DM_PCI=y\n+CONFIG_PCI_XILINX=y\n+CONFIG_LZ4=y\n+CONFIG_CLK=y\n+CONFIG_EG20T_GPIO=y\n+\n+CONFIG_MMC=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_CMD_CPU=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_OF_EMBED=y\n+CONFIG_CPU=y\n+CONFIG_MMC_SDHCI=y\n+CONFIG_MMC_PCI=y\n+\n+CONFIG_UNIT_TEST=y\n+CONFIG_UT_LIB=n\n+CONFIG_UT_LIB_ASN1=n\n+CONFIG_UT_LOG=n\n+CONFIG_UT_TIME=y\n+CONFIG_UT_UNICODE=n\n+CONFIG_UT_ENV=n\n+CONFIG_UT_OVERLAY=n\n+\n+CONFIG_SYS_LOAD_ADDR=0x80000000\n+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y\n+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000\n+CONFIG_TEXT_BASE=0x1fc00000\n+CONFIG_SYS_MALLOC_LEN=0x00800000\n+CONFIG_SYS_BOOTM_LEN=0x04000000\n+CONFIG_SYS_MAX_FLASH_SECT=1024\n+CONFIG_PHY_ANEG_TIMEOUT=40000\n+CONFIG_NET_RETRY_COUNT=10\n+CONFIG_ENV_CALLBACK_LIST_STATIC=\"io.coherent:io_coherent,\"\n+CONFIG_BOOTARGS=\"root=/dev/sda rw earlycon console=ttyS0,115200n8r\"\n+CONFIG_BOARD_EARLY_INIT_R=y\n+CONFIG_PCI_BRIDGE_MEM_ALIGNMENT=0x1\ndiff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig\nindex c88931c8ec4..3d5829544ef 100644\n--- a/drivers/clk/Kconfig\n+++ b/drivers/clk/Kconfig\n@@ -60,7 +60,7 @@ config CLK_BCM6345\n \t clocks on BCM6345 SoCs. HW has no rate changing capabilities.\n \n config CLK_BOSTON\n-\tdef_bool y if TARGET_BOSTON\n+\tdef_bool y if TARGET_BOSTON || TARGET_MIPS_BOSTON\n \tdepends on CLK\n \tselect REGMAP\n \tselect SYSCON\ndiff --git a/include/configs/boston-riscv.h b/include/configs/boston-riscv.h\nnew file mode 100644\nindex 00000000000..f1ee6f6032a\n--- /dev/null\n+++ b/include/configs/boston-riscv.h\n@@ -0,0 +1,9 @@\n+/* SPDX-License-Identifier: GPL-2.0+ */\n+/*\n+ * Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\n+ */\n+\n+#ifndef __CONFIG_BOSTON_RISCV_H\n+#define __CONFIG_BOSTON_RISCV_H\n+\n+#endif /* __CONFIG_BOSTON_RISCV_H */\n", "prefixes": [ "v6", "2/7" ] }