Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2217044/?format=api
{ "id": 2217044, "url": "http://patchwork.ozlabs.org/api/patches/2217044/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327141029.628483-2-uros.stajic@htecgroup.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327141029.628483-2-uros.stajic@htecgroup.com>", "list_archive_url": null, "date": "2026-03-27T14:11:15", "name": "[v6,1/7] riscv: Add initial support for P8700 SoC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "955c696da875f0a000e6a34812f8c35543dccb45", "submitter": { "id": 90991, "url": "http://patchwork.ozlabs.org/api/people/90991/?format=api", "name": "Uros Stajic", "email": "uros.stajic@htecgroup.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327141029.628483-2-uros.stajic@htecgroup.com/mbox/", "series": [ { "id": 497792, "url": "http://patchwork.ozlabs.org/api/series/497792/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497792", "date": "2026-03-27T14:10:46", "name": "riscv: Add support for P8700 platform on Boston board", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/497792/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217044/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217044/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=rFXIxcSw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=htecgroup.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.b=\"rFXIxcSw\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=reject dis=none)\n header.from=htecgroup.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=uros.stajic@htecgroup.com", "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=htecgroup.com;" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fj5fl5GPLz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 28 Mar 2026 03:28:15 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D2A8E84178;\n\tFri, 27 Mar 2026 17:24:56 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 5C7FC83FC6; Fri, 27 Mar 2026 15:11:22 +0100 (CET)", "from AS8PR04CU009.outbound.protection.outlook.com\n (mail-westeuropeazlp170110003.outbound.protection.outlook.com\n [IPv6:2a01:111:f403:c201::3])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id F160983C14\n for <u-boot@lists.denx.de>; Fri, 27 Mar 2026 15:11:17 +0100 (CET)", "from PA3PR09MB8140.eurprd09.prod.outlook.com (2603:10a6:102:4d4::20)\n by AM0PR09MB3969.eurprd09.prod.outlook.com (2603:10a6:208:19e::16)\n with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9745.23; Fri, 27 Mar\n 2026 14:11:15 +0000", "from PA3PR09MB8140.eurprd09.prod.outlook.com\n ([fe80::ca17:d4db:b6cd:fb81]) by PA3PR09MB8140.eurprd09.prod.outlook.com\n ([fe80::ca17:d4db:b6cd:fb81%6]) with mapi id 15.20.9745.019; Fri, 27 Mar 2026\n 14:11:15 +0000" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_BLOCKED,\n SPF_HELO_PASS,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none;\n b=Qf2dWVUW1ZQT6BRlB4Ix8xSOgOR/GeeSPXub9Euk95WaoropOMck+xx1wMX21MuIhCq7n2m0PTdp0E3Ko2mL5FaAYQGRJXq6lCwgpKQhiY9UcRo9WmKK4WhxKQMu+LK1JmGwESQNLQbSCsPgMMZ43lYrZLDzHHTFjdyH3EMHNEtcJTIkkcDIr2aScrOYuL9JPj+e5TEY5pNqsnYU6acZWto2NaCEAltpfo82BKIdOExv3BA/n207wjcKX+URrSeNSBezTUe4L99CujwPsuj26voEP6w5t6UgvRD11Cxv9ImGrACoOZNSxkCznCsOyjtvkS0I0ATkDu5msj8WrERAPA==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector10001;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1;\n bh=o+/ND8d6+dGfbyhQAq4aZG/YjqyQb9I7TjJsyRVdGPI=;\n b=MtYlMzua53Yj4qjoxurkcwPRAkKsEm6OKRSX6/KcAf5S8fo9+GCBnCASiY4qAVp4ujcV5kPGzwjlOJR1SIoJnhoB8nwDO+w5o5irjpb5n91JPWwGTU9bbJtjJU8yYYJMDPIB5sd5OLnervxbVX36SHv+V4pZdmSe8JOkE/syqS6LitTo+VyFDo/YfkAsb9jb2ewRnEr41sqmPlwoCOUjwPCLL934yM2+6k1d+gjoCkXddISnZiNB1Hgs/m5TlC0TrM5DtoaxrJb69t8UTFz2tSrD1jYFQb9BfPibNayUUFsGWWDMgLyPAqxf/A4tHvZ2eejaUB/RQKV2pdOcaGCMvQ==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass\n smtp.mailfrom=htecgroup.com; dmarc=pass action=none\n header.from=htecgroup.com; dkim=pass header.d=htecgroup.com; arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=htecgroup.com;\n s=selector1;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=o+/ND8d6+dGfbyhQAq4aZG/YjqyQb9I7TjJsyRVdGPI=;\n b=rFXIxcSwyGYeRlNYf2NmjhaZDX4R8GGd0pQs28y42fs7oxj/EUhiRkspYZElLclmctF8UymZ9DVllLUSCjDBOjOIjOtvlm/C03nN+Wo8Nuz5Aakf+ldqfEWuOLHNMA6GmLL5ONxklB6a8aj1BJ90Pk1upbIvQYYQbTVZJFNAgz9kxJ05i82G2zbMglnYGVTyxsRN2aBjHxX07Fin+suirleglmQ10EYIRtQ9zX6gCte+MIY2zfhGaha4bWM2LxEWkel9Ui8mD94lzHrQrhq24PacXsMPiks39BmdhsJvTc0niYkDPfDCC4Oqi/S2BbjGi9AOaq1/xam2VloPM+LYlA==", "From": "Uros Stajic <uros.stajic@htecgroup.com>", "To": "\"u-boot@lists.denx.de\" <u-boot@lists.denx.de>", "CC": "Djordje Todorovic <Djordje.Todorovic@htecgroup.com>, Chao-ying Fu\n <cfu@mips.com>, Uros Stajic <uros.stajic@htecgroup.com>", "Subject": "[PATCH v6 1/7] riscv: Add initial support for P8700 SoC", "Thread-Topic": "[PATCH v6 1/7] riscv: Add initial support for P8700 SoC", "Thread-Index": "AQHcvfOT04ZaizXAPkeedKvDKxrTEw==", "Date": "Fri, 27 Mar 2026 14:11:15 +0000", "Message-ID": "<20260327141029.628483-2-uros.stajic@htecgroup.com>", "References": "<20260327141029.628483-1-uros.stajic@htecgroup.com>", "In-Reply-To": "<20260327141029.628483-1-uros.stajic@htecgroup.com>", "Accept-Language": "en-US", "Content-Language": "en-US", "X-MS-Has-Attach": "", "X-MS-TNEF-Correlator": "", "authentication-results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.a=rsa-sha256 header.s=selector1 header.b=rFXIxcSw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=htecgroup.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=htecgroup.com header.i=@htecgroup.com\n header.b=\"rFXIxcSw\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=reject dis=none)\n header.from=htecgroup.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=uros.stajic@htecgroup.com", "dkim=none (message not signed)\n header.d=none;dmarc=none action=none header.from=htecgroup.com;" ], "x-ms-publictraffictype": "Email", "x-ms-traffictypediagnostic": "PA3PR09MB8140:EE_|AM0PR09MB3969:EE_", "x-ms-office365-filtering-correlation-id": "bcaf3327-f381-4281-52a2-08de8c0ab58a", "x-ms-exchange-senderadcheck": "1", "x-ms-exchange-antispam-relay": "0", "x-microsoft-antispam": "BCL:0;\n ARA:13230040|366016|1800799024|376014|38070700021|22082099003|18002099003|56012099003;", "x-microsoft-antispam-message-info": "\n 0VDNIUQWQHAJf35D+52Dqust/muvHmmkuBwblosCcAC2JaHSohi6w57Y/ejDhA8Xx4PjhKk6B4hABAoINNOknY6CQa20xX4axj5mGX0qIvWM5QBTZhNcyUUIySxpg9knkNzAXgTf9Qgj2z4G+fg0VZRVOmF0kSWKA4GoQ87QoN+LAJD6NZh0dPT0XAwb/YW5Kj/sX3VUZJmRr9vxciSRqlFmNWscBUsmKneufV7aYmH3VXg4ARl8um5zntivVmFdyxUoO02iy6ysH9rFLwRbEdPpkD+vyBLEZTCEkTBGtQwMjijTb5YTJIk0oC0mcxm3XrIw7Xm+VyQs/PSxa50zmEr69XV3EnHvb7q0S+0A2QUyymIempvY6x70Ael60tbQHfI2isjxC0qoz1ElYqybUDW/eiZjYXn8mLoXPElg0UZ9AkSzZrpkWJorucQA0mEy0YqJAEeMeniZUhKDQivZizPErKkmPjtpN2VMUkFcxpZ4Uoal/NzNLHYYLRxrz4D5Fj/ZmeHVKIhYSWSHxDPeCJDEs9MtjlwqD+py8YDxarD2rCvfc5mToK8UY5+6kD245IaA1DKVR2zWC4HWfVltiyoQMJTJ3OHfvWrkrpmiWDOrblug+jbN5X5Jxn8OZwQpluFyCQIDTDb/5DPb/OiRNVp0mnBd84m72ztqRps1rqUrhowhwXNCP4zE7MXFXnaqkf6NCIaGzrDgeLhbP5Vk4NOVxnICZzQuVAz1koznfJuSK9gKy2t0PNn6thXb1gtnWuGhjGdfmGfjAtmxKuBoNFGjERCVCmopA2QN72lw3RU=", "x-forefront-antispam-report": "CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:;\n IPV:NLI; SFV:NSPM; H:PA3PR09MB8140.eurprd09.prod.outlook.com; PTR:; CAT:NONE;\n SFS:(13230040)(366016)(1800799024)(376014)(38070700021)(22082099003)(18002099003)(56012099003);\n DIR:OUT; SFP:1102;", "x-ms-exchange-antispam-messagedata-chunkcount": "1", "x-ms-exchange-antispam-messagedata-0": "=?utf-8?q?D+lWOMwSPGr90MWaEqCD6qay/YEM?=\n\t=?utf-8?q?VWF/sj7F0PnOnuRPsdIKMQHjdZ6BOmnVfyB2pLH0xj2OPkA5lkAnrgFBxNldnkiB0?=\n\t=?utf-8?q?Vrm7y7RPt4F/CMuXE+pkw8LXjrh1kPeZjXe/w8Df4pAirW6lbsoYBdj2bfUEw7YA8?=\n\t=?utf-8?q?xGLf++vo3IUry4TrhqjPje7WHs5ZBi9WavWfPI5XG2cP9gWaOfojj2P0BPxpkgyGv?=\n\t=?utf-8?q?5/kHRgsbji8oCFJuk5aV9M8mm1TuXQBcjieViQUEAeFm2nwsD77cMpwFoEykRlxBu?=\n\t=?utf-8?q?Me2YPVJi8pQGo8mhmIzyDhujJKhEDNHjuL0y04IYpCRBYcc3w65rSAHEUNJZjftEY?=\n\t=?utf-8?q?5Pq1xLlTknVfme7OWwcFQzBlhkGlnaCizDH/Hx4u7LdG+9HdDSNnbDQU8juy2emrW?=\n\t=?utf-8?q?kqz8tY9dHSM36thIYqonzTsRZT7VpH/EdgVW67SVbI6cJr2c1F2VNsC75JEnj93Kf?=\n\t=?utf-8?q?BGK78pQccNiWeSq4RnNHhHvRIw8Y6yDHTEEj2E0iUn2sy/XRFFM3qvy67iiWsVuRj?=\n\t=?utf-8?q?IYidZ4R7gt02bEEBZDCeEj6XbrDWgdL37o0N4k4qZvbVkzFPCh1cYZmjHNFlWxFmm?=\n\t=?utf-8?q?H3ugyy/eTELlbjjurbbGPXULcTYb5/0S3KJicNdF2YMtktD2iDBZq0DSB/C+6+w49?=\n\t=?utf-8?q?18iciyuZiJqydha4uE4PpSWUGsFk7JZUIxMUk64Vhx2ynlGZyNSEAKZwhHmRb3jfT?=\n\t=?utf-8?q?FQwu5DiuMCuO8e/kntUzJWtbxktw8mTKVXWfoyEkte/VQe73WUpvMx6zC2tyzLHHS?=\n\t=?utf-8?q?r1xTmQwNlEMUwfGZgfHl5wSGh6B7L/bqpkbPh0GJjLJyQIvhhgcYsjZyjPlLjZlOt?=\n\t=?utf-8?q?/qprVOHGlI0017Zw4OYe5rcdzRGoaS903O787YXNyl4jJLtSCzvWe9QM5AZHwL/AU?=\n\t=?utf-8?q?YTmjRCtusUpjxJ3NQG0lm//hhtiixExo3DmjgqzOJB+6wIu4zdnn/RioohsyQtQz8?=\n\t=?utf-8?q?gZLsXKzBTcYW5oghnQwadNyoE0rsUscanF9RgKCyOp/l5un4QEECEND9GQoRB1mTB?=\n\t=?utf-8?q?qXsPAc1yb+YHrhQNT2MUSC6q2T0MHRHyyvp/t14Cv1/wRdxaeq68VHjNoHk2F34k/?=\n\t=?utf-8?q?aZa4eKuHzqgbsIy7MhDr87TGmWuPqAXWmiT5+KeUVvlxa7PrtIRQNjNa0Uw6stO2e?=\n\t=?utf-8?q?a2jQbz5ZV+KXOYrSg+dQGBFLGRMKK/CNssraTIUIJjpG0v6tzrUupNLinX2H6X3SY?=\n\t=?utf-8?q?mowGGmR9KSE4NLKrTsQXS782r5uHfiJb1hrqzJKss2RLtjJQroCfuQ8BRiE6DNZtG?=\n\t=?utf-8?q?L/xM3ksNd/oNk6nuLknXRLQEsDGwJshmsYkkj1j/r5MAUjWT7r0t1bvsa3GU/S8ei?=\n\t=?utf-8?q?oGYdJWFdfjeRstA6KM0fi75keVxmm20a1PmIfXOZo53Shr6d4bQV7jNz7vShJVU6S?=\n\t=?utf-8?q?n06X/AT7RiVUfqli2Oh+PD/X1y6RQ/gHJihiVoIaytt79zbhFq2/4C7+UKpqCviYV?=\n\t=?utf-8?q?9Lye1deuTRIS4j2zfre8nFOSbu1AAn1yIbCXhmoYxlJsaRBVe8/OJSPC41LF2qo8p?=\n\t=?utf-8?q?nzxnXapt3ConIDtDMDsJPNfOLFooCqNMlUAlqlNhhJlSRZ0dr+QvOq0j1KNgz94ff?=\n\t=?utf-8?q?S++plTSxz1A8tvpc8ln11VknSC4cJQb/pncabfAc8tp3Ouf4jildESSdT0y0ZcLF6?=\n\t=?utf-8?q?EAfhcv185X4Dhga/IHsmEh5eITcxLdDI3QkYDzooR9juns39Tlk8o=3D?=", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-ID": "<53240D1BA9118B458AD7D38E0CEF5CAC@eurprd09.prod.outlook.com>", "Content-Transfer-Encoding": "base64", "MIME-Version": "1.0", "X-OriginatorOrg": "htecgroup.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-AuthSource": "PA3PR09MB8140.eurprd09.prod.outlook.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n bcaf3327-f381-4281-52a2-08de8c0ab58a", "X-MS-Exchange-CrossTenant-originalarrivaltime": "27 Mar 2026 14:11:15.5949 (UTC)", "X-MS-Exchange-CrossTenant-fromentityheader": "Hosted", "X-MS-Exchange-CrossTenant-id": "9f85665b-7efd-4776-9dfe-b6bfda2565ee", "X-MS-Exchange-CrossTenant-mailboxtype": "HOSTED", "X-MS-Exchange-CrossTenant-userprincipalname": "\n 3EaI1v0pjMfaheTZRoOb0ufe39Y/A/AfMb62+jJGBBGxPQpOj05JMLAMMtWd1+HV7aVnkQuNFlVBQgGD7FOyNJo909nOV5LpZcrKnPNeww8=", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "AM0PR09MB3969", "X-Mailman-Approved-At": "Fri, 27 Mar 2026 17:24:54 +0100", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Chao-ying Fu <cfu@mips.com>\n\nAdd initial platform support for the P8700-F, a high-performance\nmulti-core RV64GC SoC with optional multi-cluster configuration and\nhardware multithreading.\n\nThis patch introduces the initial platform code necessary to support\nthe P8700 CPU in U-Boot.\n\nSigned-off-by: Chao-ying Fu <cfu@mips.com>\nSigned-off-by: Uros Stajic <uros.stajic@htecgroup.com>\n---\n arch/riscv/Kconfig | 8 ++\n arch/riscv/cpu/p8700/Kconfig | 14 +++\n arch/riscv/cpu/p8700/Makefile | 8 ++\n arch/riscv/cpu/p8700/cache.c | 93 +++++++++++++++++++\n arch/riscv/cpu/p8700/cpu.c | 105 ++++++++++++++++++++++\n arch/riscv/cpu/p8700/dram.c | 37 ++++++++\n arch/riscv/cpu/p8700/p8700.c | 12 +++\n arch/riscv/include/asm/arch-p8700/p8700.h | 101 +++++++++++++++++++++\n 8 files changed, 378 insertions(+)\n create mode 100644 arch/riscv/cpu/p8700/Kconfig\n create mode 100644 arch/riscv/cpu/p8700/Makefile\n create mode 100644 arch/riscv/cpu/p8700/cache.c\n create mode 100644 arch/riscv/cpu/p8700/cpu.c\n create mode 100644 arch/riscv/cpu/p8700/dram.c\n create mode 100644 arch/riscv/cpu/p8700/p8700.c\n create mode 100644 arch/riscv/include/asm/arch-p8700/p8700.h", "diff": "diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig\r\nindex 79867656b15..9e2cbe775d2 100644\r\n--- a/arch/riscv/Kconfig\r\n+++ b/arch/riscv/Kconfig\r\n@@ -132,6 +132,7 @@ source \"arch/riscv/cpu/jh7110/Kconfig\"\r\n source \"arch/riscv/cpu/k1/Kconfig\"\r\n source \"arch/riscv/cpu/k230/Kconfig\"\r\n source \"arch/riscv/cpu/th1520/Kconfig\"\r\n+source \"arch/riscv/cpu/p8700/Kconfig\"\r\n \r\n # architecture-specific options below\r\n \r\n@@ -442,6 +443,13 @@ config SBI\r\n \tbool\r\n \tdefault y if RISCV_SMODE || SPL_RISCV_SMODE\r\n \r\n+config RISCV_CM_BASE\r\n+\thex \"RISCV CM Base Address\"\r\n+\tdefault 0x16100000\r\n+\thelp\r\n+\t The physical base address at which to map the Coherence Manager\r\n+\t Global Configuration Registers (GCRs).\r\n+\r\n choice\r\n \tprompt \"SBI support\"\r\n \tdefault SBI_V02\r\ndiff --git a/arch/riscv/cpu/p8700/Kconfig b/arch/riscv/cpu/p8700/Kconfig\r\nnew file mode 100644\r\nindex 00000000000..0913a6ce8f2\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/Kconfig\r\n@@ -0,0 +1,14 @@\r\n+# SPDX-License-Identifier: GPL-2.0+\r\n+#\r\n+# Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\r\n+\r\n+config P8700_RISCV\r\n+\tbool\r\n+\tselect ARCH_EARLY_INIT_R\r\n+\timply CPU\r\n+\timply CPU_RISCV\r\n+\timply RISCV_ACLINT if (RISCV_MMODE || SPL_RISCV_MMODE)\r\n+\timply CMD_CPU\r\n+\timply SPL_CPU_SUPPORT\r\n+\timply SPL_OPENSBI\r\n+\timply SPL_LOAD_FIT\r\ndiff --git a/arch/riscv/cpu/p8700/Makefile b/arch/riscv/cpu/p8700/Makefile\r\nnew file mode 100644\r\nindex 00000000000..04291375a29\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/Makefile\r\n@@ -0,0 +1,8 @@\r\n+# SPDX-License-Identifier: GPL-2.0+\r\n+#\r\n+# Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\r\n+\r\n+obj-y += cache.o\r\n+obj-y += cpu.o\r\n+obj-y += dram.o\r\n+obj-y += p8700.o\r\ndiff --git a/arch/riscv/cpu/p8700/cache.c b/arch/riscv/cpu/p8700/cache.c\r\nnew file mode 100644\r\nindex 00000000000..06e60156394\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/cache.c\r\n@@ -0,0 +1,93 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\r\n+ */\r\n+\r\n+#include <cpu_func.h>\r\n+#include <asm/global_data.h>\r\n+#include <asm/io.h>\r\n+#include <asm/arch-p8700/p8700.h>\r\n+\r\n+#define MCACHE_BASE_INST 0xec0500f3\r\n+\r\n+/* NOTE: We force to use a0 in mcache to encode via .word.\r\n+ * 0xec0500f3 is a manually encoded custom RISC-V MCACHE instruction.\r\n+ * The bits [19:15] are set to 01010, selecting register x10 (a0)\r\n+ * as the source operand.\r\n+ * The bits [24:20] represent the 'op' field, which is currently set to 0.\r\n+ * Different cache operations are applied by OR-ing (op << 20) dynamically\r\n+ * to this base value.\r\n+ * Because of this encoding, the variable 'addr' is forced into register a0,\r\n+ * so that the MCACHE instruction uses the address in a0 as its operand.\r\n+ */\r\n+#define cache_loop(start, end, lsize, op) do {\t\t\t\t\\\r\n+\tconst __typeof__(lsize) __lsize = (lsize);\t\t\t\\\r\n+\tconst register void *addr asm(\"a0\") = (const void *)((start) & ~(__lsize - 1));\t\\\r\n+\tconst void *aend = (const void *)(((end) - 1) & ~(__lsize - 1));\t\\\r\n+\tfor (; addr <= aend; addr += __lsize)\t\t\t\t\\\r\n+\t\tasm volatile (\".word %0 | %1 # force to use %2\" \\\r\n+\t\t\t\t\t::\"i\"(MCACHE_BASE_INST), \"i\"((op) << 20), \"r\"(addr)); \\\r\n+} while (0)\r\n+\r\n+static unsigned long lsize;\r\n+static unsigned long l1d_total_size;\r\n+static unsigned long slsize;\r\n+\r\n+static void probe_cache_config(void)\r\n+{\r\n+\tlsize = 64;\r\n+\tl1d_total_size = 64 * 1024;\r\n+\r\n+\tint l2_config = 0;\r\n+\r\n+\tl2_config = readl((void __iomem *)(CM_BASE + GCR_L2_CONFIG_OFFSET));\r\n+\tint l2_line_size_info = (l2_config >> L2_LINE_SIZE_SHIFT)\r\n+\t\t\t\t& L2_LINE_SIZE_MASK;\r\n+\tslsize = (l2_line_size_info == 0) ? 0 : 1 << (l2_line_size_info + 1);\r\n+}\r\n+\r\n+void flush_dcache_range(unsigned long start, unsigned long end)\r\n+{\r\n+\tif (lsize == 0)\r\n+\t\tprobe_cache_config();\r\n+\r\n+\t/* aend will be miscalculated when size is zero, so we return here */\r\n+\tif (start >= end)\r\n+\t\treturn;\r\n+\r\n+\tcache_loop(start, end, lsize, HIT_WRITEBACK_INV_D);\r\n+\r\n+\t/* flush L2 cache */\r\n+\tif (slsize)\r\n+\t\tcache_loop(start, end, slsize, HIT_WRITEBACK_INV_SD);\r\n+\r\n+\t/* Instruction Hazard Barrier (IHB) — a hint-encoded SLLI (rd=0, rs1=0, imm=1).\r\n+\t * Ensures that all subsequent instruction fetches, including speculative ones,\r\n+\t * observe state changes from prior instructions.\r\n+\t * Required after MCACHE instructions when instruction fetch depends on cache ops.\r\n+\t */\r\n+\tasm volatile (\"slli x0,x0,1 # ihb\");\r\n+}\r\n+\r\n+void invalidate_dcache_range(unsigned long start, unsigned long end)\r\n+{\r\n+\tif (lsize == 0)\r\n+\t\tprobe_cache_config();\r\n+\r\n+\t/* aend will be miscalculated when size is zero, so we return here */\r\n+\tif (start >= end)\r\n+\t\treturn;\r\n+\r\n+\t/* invalidate L2 cache */\r\n+\tif (slsize)\r\n+\t\tcache_loop(start, end, slsize, HIT_INVALIDATE_SD);\r\n+\r\n+\tcache_loop(start, end, lsize, HIT_INVALIDATE_D);\r\n+\r\n+\t/* Instruction Hazard Barrier (IHB) — a hint-encoded SLLI (rd=0, rs1=0, imm=1).\r\n+\t * Ensures that all subsequent instruction fetches, including speculative ones,\r\n+\t * observe state changes from prior instructions.\r\n+\t * Required after MCACHE instructions when instruction fetch depends on cache ops.\r\n+\t */\r\n+\tasm volatile (\"slli x0,x0,1 # ihb\");\r\n+}\r\ndiff --git a/arch/riscv/cpu/p8700/cpu.c b/arch/riscv/cpu/p8700/cpu.c\r\nnew file mode 100644\r\nindex 00000000000..55b9f939f8e\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/cpu.c\r\n@@ -0,0 +1,105 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\r\n+ */\r\n+\r\n+#include <asm/encoding.h>\r\n+#include <asm/io.h>\r\n+#include <linux/types.h>\r\n+#include <asm/arch-p8700/p8700.h>\r\n+\r\n+static __noreturn void jump_to_addr(ulong addr)\r\n+{\r\n+\tasm volatile (\"jr %0\" :: \"r\"(addr) : \"memory\");\r\n+\t__builtin_unreachable();\r\n+}\r\n+\r\n+void harts_early_init(void)\r\n+{\r\n+\tif (!IS_ENABLED(CONFIG_RISCV_MMODE))\r\n+\t\treturn;\r\n+\r\n+\tulong hartid = csr_read(CSR_MHARTID);\r\n+\r\n+\t/* Wait for DDR3 calibration */\r\n+\twait_ddr_calib();\r\n+\r\n+\t/*\r\n+\t * Only mhartid[3:0] == 0 performs CM/GCR programming.\r\n+\t * Other harts skip CM/GCR setup and go straight to PMP/PMA setup.\r\n+\t */\r\n+\tif ((hartid & 0xFULL) == 0) {\r\n+\t\tulong cm_base = CM_BASE;\r\n+\t\tvoid __iomem *gcr_win = (void __iomem *)0x1fb80000;\r\n+\t\tulong cluster = (hartid >> MHARTID_CLUSTER_SHIFT) &\r\n+\t\t\t\tMHARTID_CLUSTER_MASK;\r\n+\r\n+\t\tcm_base += cluster << CM_BASE_CLUSTER_SHIFT;\r\n+\r\n+\t\tif ((hartid & 0xFFFFUL) == 0)\r\n+\t\t\twriteq(cm_base, gcr_win + GCR_BASE_OFFSET);\r\n+\r\n+\t\tulong core = (hartid >> MHARTID_CORE_SHIFT) & MHARTID_CORE_MASK;\r\n+\r\n+\t\t/* Enable coherency for the current core */\r\n+\t\tcm_base += core << CM_BASE_CORE_SHIFT;\r\n+\t\twriteq((u64)GCR_CL_COH_EN_EN,\r\n+\t\t (void __iomem *)(cm_base + P8700_GCR_C0_COH_EN));\r\n+\r\n+\t\t/*\r\n+\t\t * On hart 0, default PCIe DMA mapping should be the non-IOCU\r\n+\t\t * target.\r\n+\t\t */\r\n+\t\tif (hartid == 0)\r\n+\t\t\tsetup_pcie_dma_map();\r\n+\t}\r\n+\r\n+\t/* PMP setup */\r\n+\tcsr_write(pmpaddr1, 0x2fffffffUL);\r\n+\tcsr_write(pmpaddr2, 0x07ff7fffUL);\r\n+\tcsr_write(pmpaddr3, 0x07f3ffffUL);\r\n+\tcsr_write(pmpaddr4, 0x1fffffffffffffffUL);\r\n+\r\n+\tunsigned long pmpcfg = ((unsigned long)(PMP_NAPOT | PMP_R | PMP_W |\r\n+\t\t\t\t\t\tPMP_X) << 32) |\r\n+\t\t\t\t((unsigned long)(PMP_NAPOT | PMP_R |\r\n+\t\t\t\t\t\tPMP_X) << 24) |\r\n+\t\t\t\t((unsigned long)(PMP_NAPOT | PMP_R | PMP_W |\r\n+\t\t\t\t\t\tPMP_X) << 16) |\r\n+\t\t\t\t((unsigned long)(PMP_NAPOT | PMP_R | PMP_W |\r\n+\t\t\t\t\t\tPMP_X) << 8);\r\n+\r\n+\tcsr_write(pmpcfg0, pmpcfg);\r\n+\r\n+\t/* PMA/cache attributes */\r\n+\tulong pmacfg0;\r\n+\r\n+\tif (hartid == 0) {\r\n+\t\t/*\r\n+\t\t * Hart 0: cacheable for pma0, pma1, pma3; uncacheable for\r\n+\t\t * pma2, pma4.\r\n+\t\t */\r\n+\t\tpmacfg0 = ((unsigned long)CCA_CACHE_DISABLE << 32) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE << 24) |\r\n+\t\t\t((unsigned long)CCA_CACHE_DISABLE << 16) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE << 8) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE);\r\n+\t} else {\r\n+\t\t/*\r\n+\t\t * Hart 1 or above: cacheable for pma0, pma1; uncacheable for\r\n+\t\t * pma2, pma3, pma4.\r\n+\t\t */\r\n+\t\tpmacfg0 = ((unsigned long)CCA_CACHE_DISABLE << 32) |\r\n+\t\t\t((unsigned long)CCA_CACHE_DISABLE << 24) |\r\n+\t\t\t((unsigned long)CCA_CACHE_DISABLE << 16) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE << 8) |\r\n+\t\t\t((unsigned long)CCA_CACHE_ENABLE);\r\n+\t}\r\n+\r\n+\tasm volatile (\"csrw %0, %1\" :: \"i\"(CSR_PMACFG0), \"r\"(pmacfg0));\r\n+\tasm volatile (\"fence\" ::: \"memory\");\r\n+\r\n+\t/* Secondary harts: after early setup, jump to the common entry point */\r\n+\tif (hartid != 0)\r\n+\t\tjump_to_addr(CONFIG_SYS_LOAD_ADDR);\r\n+}\r\ndiff --git a/arch/riscv/cpu/p8700/dram.c b/arch/riscv/cpu/p8700/dram.c\r\nnew file mode 100644\r\nindex 00000000000..2b54326be39\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/dram.c\r\n@@ -0,0 +1,37 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2018, Bin Meng <bmeng.cn@gmail.com>\r\n+ */\r\n+\r\n+#include <fdtdec.h>\r\n+#include <init.h>\r\n+#include <linux/sizes.h>\r\n+\r\n+DECLARE_GLOBAL_DATA_PTR;\r\n+\r\n+int dram_init(void)\r\n+{\r\n+\treturn fdtdec_setup_mem_size_base();\r\n+}\r\n+\r\n+int dram_init_banksize(void)\r\n+{\r\n+\treturn fdtdec_setup_memory_banksize();\r\n+}\r\n+\r\n+phys_size_t board_get_usable_ram_top(phys_size_t total_size)\r\n+{\r\n+\tif (IS_ENABLED(CONFIG_64BIT)) {\r\n+\t\t/*\r\n+\t\t * Ensure that we run from first 4GB so that all\r\n+\t\t * addresses used by U-Boot are 32bit addresses.\r\n+\t\t *\r\n+\t\t * This in-turn ensures that 32bit DMA capable\r\n+\t\t * devices work fine because DMA mapping APIs will\r\n+\t\t * provide 32bit DMA addresses only.\r\n+\t\t */\r\n+\t\tif (gd->ram_top > SZ_4G)\r\n+\t\t\treturn SZ_4G;\r\n+\t}\r\n+\treturn gd->ram_top;\r\n+}\r\ndiff --git a/arch/riscv/cpu/p8700/p8700.c b/arch/riscv/cpu/p8700/p8700.c\r\nnew file mode 100644\r\nindex 00000000000..41d5547c511\r\n--- /dev/null\r\n+++ b/arch/riscv/cpu/p8700/p8700.c\r\n@@ -0,0 +1,12 @@\r\n+// SPDX-License-Identifier: GPL-2.0+\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\r\n+ */\r\n+\r\n+#include <asm/io.h>\r\n+#include <linux/types.h>\r\n+#include <asm/arch-p8700/p8700.h>\r\n+\r\n+__weak void wait_ddr_calib(void) { }\r\n+\r\n+__weak void setup_pcie_dma_map(void) { }\r\ndiff --git a/arch/riscv/include/asm/arch-p8700/p8700.h b/arch/riscv/include/asm/arch-p8700/p8700.h\r\nnew file mode 100644\r\nindex 00000000000..d6cc125d76a\r\n--- /dev/null\r\n+++ b/arch/riscv/include/asm/arch-p8700/p8700.h\r\n@@ -0,0 +1,101 @@\r\n+/* SPDX-License-Identifier: GPL-2.0 */\r\n+/*\r\n+ * Copyright (C) 2021, Chao-ying Fu <cfu@mips.com>\r\n+ */\r\n+\r\n+#ifndef __P8700_H__\r\n+#define __P8700_H__\r\n+\r\n+#define CSR_MIPSCONFIG7\t\t0x7d7\r\n+#define CSR_PMACFG0\t\t\t0x7e0\r\n+\r\n+#define MHARTID_HART_SHIFT\t0\r\n+#define MHARTID_HART_MASK\t0xf\r\n+#define MHARTID_CORE_SHIFT\t4\r\n+#define MHARTID_CORE_MASK\t0xff\r\n+#define MHARTID_CLUSTER_SHIFT\t16\r\n+#define MHARTID_CLUSTER_MASK\t0xf\r\n+\r\n+#define MARCHID_UARCH_SHIFT\t0\r\n+#define MARCHID_UARCH_MASK\t0xff\r\n+#define MARCHID_CLASS_SHIFT\t8\r\n+#define MARCHID_CLASS_MASK\t0xff\r\n+#define MARCHID_CLASS_M\t\t0\r\n+#define MARCHID_CLASS_I\t\t1\r\n+#define MARCHID_CLASS_P\t\t2\r\n+\r\n+#define CM_BASE_CORE_SHIFT\t8\r\n+#define CM_BASE_CLUSTER_SHIFT\t19\r\n+\r\n+#define P8700_TIMER_ADDR\t0x16108050\r\n+\r\n+#define CCA_CACHE_ENABLE\t0\r\n+#define CCA_BUFFER_CACHE\t1\r\n+#define CCA_CACHE_DISABLE\t2\r\n+#define CCA_UNCACHE_ACC\t\t3\r\n+#define PMA_SPECULATION\t\t(0x1 << 3)\r\n+\r\n+#define L1_I_CACHE 0\r\n+#define L1_D_CACHE 1\r\n+#define L3_CACHE 2\r\n+#define L2_CACHE 3\r\n+\r\n+#define HIT_INVALIDATE 4\r\n+#define HIT_WRITEBACK_INV 5\r\n+\r\n+#define HIT_INVALIDATE_D ((HIT_INVALIDATE << 2) | L1_D_CACHE)\r\n+#define HIT_INVALIDATE_SD ((HIT_INVALIDATE << 2) | L2_CACHE)\r\n+#define HIT_WRITEBACK_INV_D ((HIT_WRITEBACK_INV << 2) | L1_D_CACHE)\r\n+#define HIT_WRITEBACK_INV_SD ((HIT_WRITEBACK_INV << 2) | L2_CACHE)\r\n+\r\n+#define L1D_LINE_SIZE_SHIFT\t10\r\n+#define L1D_LINE_SIZE_MASK\t0x7\r\n+\r\n+#define GCR_L2_CONFIG_OFFSET\t0x0130\r\n+#define L2_LINE_SIZE_SHIFT\t8\r\n+#define L2_LINE_SIZE_MASK\t0xf\r\n+\r\n+#define PMP_R\t\t\t0x01\r\n+#define PMP_W\t\t\t0x02\r\n+#define PMP_X\t\t\t0x04\r\n+#define PMP_TOR\t\t\t0x8\r\n+#define PMP_NA4\t\t\t0x10\r\n+#define PMP_NAPOT\t\t0x18\r\n+\r\n+#define CM_BASE\t\t\tCONFIG_RISCV_CM_BASE\r\n+#define CPC_BASE\t\t(CM_BASE + 0x8000)\r\n+\r\n+/* CPC Block offsets */\r\n+#define CPC_OFF_LOCAL\t\t0x2000\r\n+\r\n+#define CPC_PWRUP_CTL\t\t0x0030\r\n+\r\n+#define CPC_SYS_CONFIG\t\t0x0140\r\n+\r\n+#define CPC_Cx_CMD\t\t0x0000\r\n+#define CPC_Cx_CMD_RESET\t0x4\r\n+\r\n+#define P8700_GCR_C0_COH_EN\t0x20f8\r\n+#define P8700_GCR_C1_COH_EN\t0x21f8\r\n+#define P8700_GCR_C2_COH_EN\t0x22f8\r\n+#define P8700_GCR_C3_COH_EN\t0x23f8\r\n+#define P8700_GCR_C4_COH_EN\t0x24f8\r\n+#define P8700_GCR_C5_COH_EN\t0x25f8\r\n+\r\n+#define GCR_CL_COH_EN\t\t0x2008\r\n+#define GCR_CL_COH_EN_EN\t(0x1 << 0)\r\n+#define GCR_BASE_OFFSET\t\t0x0008\r\n+#define GIC_BASE_OFFSET\t\t0x0080\r\n+#define CPC_BASE_OFFSET\t\t0x0088\r\n+#define ENABLE\t\t\t0x1\r\n+#define COUNT_STOP\t\t(0x1 << 28)\r\n+#define GIC_LOCAL_SECTION_OFS\t0x8000\r\n+#define GIC_VL_MASK\t\t0x08\r\n+#define GIC_VL_RMASK\t\t0x0c\r\n+#define GIC_VL_SMASK\t\t0x10\r\n+#define GIC_VL_COMPARE_MAP\t0x44\r\n+\r\n+void wait_ddr_calib(void);\r\n+void setup_pcie_dma_map(void);\r\n+\r\n+#endif /* __P8700_H__ */\r\n", "prefixes": [ "v6", "1/7" ] }