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GET /api/patches/2217027/?format=api
{ "id": 2217027, "url": "http://patchwork.ozlabs.org/api/patches/2217027/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327160446.330583-1-pbonzini@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327160446.330583-1-pbonzini@redhat.com>", "list_archive_url": null, "date": "2026-03-27T16:04:46", "name": "target/i386/tcg: svm: implement GMET", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "e0fec7fff15ed04c3925089a121c1d12f122a074", "submitter": { "id": 2701, "url": "http://patchwork.ozlabs.org/api/people/2701/?format=api", "name": "Paolo Bonzini", "email": "pbonzini@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327160446.330583-1-pbonzini@redhat.com/mbox/", "series": [ { "id": 497789, "url": "http://patchwork.ozlabs.org/api/series/497789/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497789", "date": "2026-03-27T16:04:46", "name": "target/i386/tcg: svm: implement GMET", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497789/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2217027/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2217027/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n 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DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "GMET (Guest Mode Execution Trap) has two effects: it disables\nthe U bit check when the guest is in user mode, and enables\nthe SMEP check when the guest is in kernel mode.\n\nSigned-off-by: Paolo Bonzini <pbonzini@redhat.com>\n---\n target/i386/cpu.h | 2 ++\n target/i386/svm.h | 1 +\n target/i386/cpu.c | 2 +-\n target/i386/tcg/system/excp_helper.c | 20 ++++++++++++++++----\n target/i386/tcg/system/svm_helper.c | 4 ++++\n 5 files changed, 24 insertions(+), 5 deletions(-)", "diff": "diff --git a/target/i386/cpu.h b/target/i386/cpu.h\nindex 0b539155c40..82b7d1a52e4 100644\n--- a/target/i386/cpu.h\n+++ b/target/i386/cpu.h\n@@ -354,6 +354,7 @@ typedef enum X86Seg {\n #define PG_MODE_NXE (1 << 2)\n #define PG_MODE_PSE (1 << 3)\n #define PG_MODE_LA57 (1 << 4)\n+#define PG_MODE_SVM_GMET (1 << 5)\n #define PG_MODE_SVM_MASK MAKE_64BIT_MASK(0, 15)\n \n /* Bits of CR4 that do not affect the NPT page format. */\n@@ -879,6 +880,7 @@ uint64_t x86_cpu_get_supported_feature_word(X86CPU *cpu, FeatureWord w);\n #define CPUID_SVM_AVIC (1U << 13)\n #define CPUID_SVM_V_VMSAVE_VMLOAD (1U << 15)\n #define CPUID_SVM_VGIF (1U << 16)\n+#define CPUID_SVM_GMET (1U << 17)\n #define CPUID_SVM_VNMI (1U << 25)\n #define CPUID_SVM_SVME_ADDR_CHK (1U << 28)\n \ndiff --git a/target/i386/svm.h b/target/i386/svm.h\nindex 1bd78447306..e05a66ecc43 100644\n--- a/target/i386/svm.h\n+++ b/target/i386/svm.h\n@@ -140,6 +140,7 @@\n #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */\n \n #define SVM_NPT_ENABLED (1 << 0)\n+#define SVM_GMET_ENABLED (1 << 3)\n \n #define SVM_NPTEXIT_GPA (1ULL << 32)\n #define SVM_NPTEXIT_GPT (1ULL << 33)\ndiff --git a/target/i386/cpu.c b/target/i386/cpu.c\nindex d02f6f0653e..ec80649658c 100644\n--- a/target/i386/cpu.c\n+++ b/target/i386/cpu.c\n@@ -960,7 +960,7 @@ void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,\n #else\n #define CPUID_SVM_KERNEL_FEATURES 0\n #endif\n-#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | \\\n+#define TCG_SVM_FEATURES (CPUID_SVM_NPT | CPUID_SVM_VGIF | CPUID_SVM_GMET | \\\n CPUID_SVM_SVME_ADDR_CHK | CPUID_SVM_KERNEL_FEATURES)\n \n #define TCG_KVM_FEATURES 0\ndiff --git a/target/i386/tcg/system/excp_helper.c b/target/i386/tcg/system/excp_helper.c\nindex d7ea77c8558..bd99e8416f5 100644\n--- a/target/i386/tcg/system/excp_helper.c\n+++ b/target/i386/tcg/system/excp_helper.c\n@@ -371,7 +371,9 @@ do_check_protect_pse36:\n ptep ^= PG_NX_MASK;\n \n /* can the page can be put in the TLB? prot will tell us */\n- if (is_user && !(ptep & PG_USER_MASK)) {\n+\n+ /* GMET disables checks to the U bit other than the SMEP check below. */\n+ if (is_user && !(ptep & PG_USER_MASK) && !(pg_mode & PG_MODE_SVM_GMET)) {\n goto do_fault_protect;\n }\n \n@@ -384,7 +386,7 @@ do_check_protect_pse36:\n }\n if (!(ptep & PG_NX_MASK) &&\n (is_user ||\n- !((pg_mode & PG_MODE_SMEP) && (ptep & PG_USER_MASK)))) {\n+ !((pg_mode & (PG_MODE_SMEP | PG_MODE_SVM_GMET)) && (ptep & PG_USER_MASK)))) {\n prot |= PAGE_EXEC;\n }\n \n@@ -543,6 +545,17 @@ static G_NORETURN void raise_stage2(CPUX86State *env, TranslateFault *err,\n cpu_vmexit(env, SVM_EXIT_NPF, exit_info_1, retaddr);\n }\n \n+static int cpu_mmu_index_svm(CPUX86State *env)\n+{\n+ unsigned pl = env->hflags & HF_CPL_MASK;\n+ int mmu_index_32 = (env->nested_pg_mode & PG_MODE_LMA) ? 0 : 1;\n+ int mmu_index_base =\n+ pl < 3 && (env->nested_pg_mode & PG_MODE_SVM_GMET)\n+ ? MMU_KNOSMAP64_IDX : MMU_USER64_IDX;\n+\n+ return mmu_index_base + mmu_index_32;\n+}\n+\n static bool get_physical_address(CPUX86State *env, vaddr addr,\n MMUAccessType access_type, int mmu_idx,\n TranslateResult *out, TranslateFault *err,\n@@ -562,8 +575,7 @@ static bool get_physical_address(CPUX86State *env, vaddr addr,\n if (likely(use_stage2)) {\n in.cr3 = env->nested_cr3;\n in.pg_mode = env->nested_pg_mode;\n- in.mmu_idx =\n- env->nested_pg_mode & PG_MODE_LMA ? MMU_USER64_IDX : MMU_USER32_IDX;\n+ in.mmu_idx = cpu_mmu_index_svm(env);\n in.ptw_idx = MMU_PHYS_IDX;\n \n if (!mmu_translate(env, &in, out, err, ra)) {\ndiff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/svm_helper.c\nindex d5ffabc2f4d..14e46f00bb6 100644\n--- a/target/i386/tcg/system/svm_helper.c\n+++ b/target/i386/tcg/system/svm_helper.c\n@@ -296,6 +296,10 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)\n env->hflags2 |= HF2_NPT_MASK;\n \n env->nested_pg_mode = get_pg_mode(env) & PG_MODE_SVM_MASK;\n+ if ((nested_ctl & SVM_GMET_ENABLED) &&\n+ (env->features[FEAT_SVM] & CPUID_SVM_GMET)) {\n+ env->nested_pg_mode |= PG_MODE_SVM_GMET;\n+ }\n \n tlb_flush_by_mmuidx(cs, 1 << MMU_NESTED_IDX);\n }\n", "prefixes": [] }