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GET /api/patches/2216951/?format=api
{ "id": 2216951, "url": "http://patchwork.ozlabs.org/api/patches/2216951/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327121015.996806-3-pranav.sanwal@amd.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327121015.996806-3-pranav.sanwal@amd.com>", "list_archive_url": null, "date": "2026-03-27T12:10:14", "name": "[2/3] arm: versal2: Map PCIe DBI and config regions when PCIe is enabled", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6a1eae4e5411ebff89afcd5ea9d92e1f5b7810e4", "submitter": { "id": 92240, "url": "http://patchwork.ozlabs.org/api/people/92240/?format=api", "name": "Pranav Sanwal", "email": "pranav.sanwal@amd.com" }, "delegate": { "id": 1692, "url": "http://patchwork.ozlabs.org/api/users/1692/?format=api", "username": "monstr", "first_name": "Michal", "last_name": "Simek", "email": "monstr@monstr.eu" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327121015.996806-3-pranav.sanwal@amd.com/mbox/", "series": [ { "id": 497757, "url": "http://patchwork.ozlabs.org/api/series/497757/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497757", "date": "2026-03-27T12:10:12", "name": "Add PCIe and NVMe support for AMD Versal Gen 2", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497757/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216951/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216951/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=QaflU3Yu;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; 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helo=satlexmb08.amd.com; pr=C", "From": "Pranav Sanwal <pranav.sanwal@amd.com>", "To": "<u-boot@lists.denx.de>", "CC": "<git@amd.com>, <michal.simek@amd.com>", "Subject": "[PATCH 2/3] arm: versal2: Map PCIe DBI and config regions when PCIe\n is enabled", "Date": "Fri, 27 Mar 2026 17:40:14 +0530", "Message-ID": "<20260327121015.996806-3-pranav.sanwal@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260327121015.996806-1-pranav.sanwal@amd.com>", "References": "<20260327121015.996806-1-pranav.sanwal@amd.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CO1PEPF00012E82:EE_|PH0PR12MB7932:EE_", "X-MS-Office365-Filtering-Correlation-Id": "701ed661-a34e-4c03-fa07-08de8bf9d9a3", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|1800799024|36860700016|376014|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n bFuWrvpXZvCw7vwQ6hXgxBKgHDkBtClPfqJg9c1xOiwwxeEriV+kzz8MzRFcXR8BpKcKc37OgkU/UmarWj2OZC10oi/bCWCcQ6A+Ii3Z0ZJLVwx0IUDUVeXbT3Zc3trdsE+SBB7g8rVbldBUwe7piU1bfSnuQlyY5bNcGt/S5nYh/iw8VVPcMoT9GtW1vobWUsmgQwensp0VAnNgRvyBIGoZuiIZeFwMJCO39hKMFUbYzrq35tbBms1GbpiNic3n3EKIqQ2gN9GcwUoNyK5tTWvDRwSVddVUt4EwQgdwMQ/orfdoinq6LpYEV0FRAgNKcYU9XPBM5oSl5dSM/3cpIFERI0ZleRbEA2xmFCFpzThwR5VgWQMT7/mwtTld4PHgxw6c7OYE62fll7ewukudF1Zeqi60dI8C3OiqPPdGpedf7zDvPh9kDejt4JU3ZRx9JBEWWlVM0nxllSjYPnWX+KrC+LztCPXW6X8Fxr1+GNjmFnsyR26udb0tkzT60iICblXcJvw724e5y07tdNsa/pyfnF562DPtLKTDciruKCwfB+9Fp+NEd77BRh5mxI2OSYjBbI2Nhgg6487YuxZjJ+FyTf6UZPs5nEosd4J911jv+jZhcCYVQa4c6Fa3eNeQ4uMCRBz+TbJ4MDQlVNsSf3PdIuZxqEGSZYilGJqyrZpv1GHdqEVSkjbF0XQPaQdSioh7poTDYwVydCtZlm3fRCJfu18P6l0v07BxZJsi3L+8FdpdSKsXhhB/iYbRf/1Us0JzMjRkyExvzHhPPIXdcQ==", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb08.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1PEPF00012E82.namprd03.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH0PR12MB7932", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "The AMD Versal Gen 2 PCIe host controller places its DBI registers\n(0x100000000000, 1 MB) and config space (0x100000100000, 255 MB)\nabove 1 TB. Without MMU entries covering these ranges, U-Boot faults\nwhen the PCIe driver accesses them.\n\nThe two regions are merged into a single entry as these are\ncontiguous and share identical MMU attributes. Add this\nentry under a CONFIG_IS_ENABLED(PCIE_DW_AMD) guard so it is only\nincluded when the PCIe driver is configured. VERSAL2_MEM_MAP_USED is\nadjusted from 5 to 6 accordingly, keeping the DRAM bank index correct.\n\nSigned-off-by: Pranav Sanwal <pranav.sanwal@amd.com>\n---\n arch/arm/mach-versal2/cpu.c | 16 +++++++++++++++-\n 1 file changed, 15 insertions(+), 1 deletion(-)", "diff": "diff --git a/arch/arm/mach-versal2/cpu.c b/arch/arm/mach-versal2/cpu.c\nindex 9a02fe40733..9998386fed4 100644\n--- a/arch/arm/mach-versal2/cpu.c\n+++ b/arch/arm/mach-versal2/cpu.c\n@@ -18,7 +18,11 @@\n \n DECLARE_GLOBAL_DATA_PTR;\n \n+#if CONFIG_IS_ENABLED(PCIE_DW_AMD)\n+#define VERSAL2_MEM_MAP_USED\t6\n+#else\n #define VERSAL2_MEM_MAP_USED\t5\n+#endif\n \n #define DRAM_BANKS CONFIG_NR_DRAM_BANKS\n \n@@ -60,6 +64,16 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = {\n \t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n \t\t\t PTE_BLOCK_NON_SHARE |\n \t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+#if CONFIG_IS_ENABLED(PCIE_DW_AMD)\n+\t}, {\n+\t\t/* PCIe DBI (1 MB) and config space (255 MB) are contiguous */\n+\t\t.virt = 0x100000000000UL,\n+\t\t.phys = 0x100000000000UL,\n+\t\t.size = 0x10000000UL,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t PTE_BLOCK_NON_SHARE |\n+\t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+#endif\n \t}\n };\n \n@@ -69,7 +83,7 @@ static struct mm_region versal2_mem_map[VERSAL2_MEM_MAP_MAX] = {\n * @num_banks: Number of valid DRAM banks in bank_info array\n *\n * Copies DRAM bank information into the global versal2_mem_map[] array\n- * starting at index VERSAL2_MEM_MAP_USED (5), which is after the fixed\n+ * starting at index VERSAL2_MEM_MAP_USED, which is after the fixed\n * device mappings. This must be called early in boot before MMU\n * initialization so that get_page_table_size() can calculate the\n * required page table size based on actual memory configuration.\n", "prefixes": [ "2/3" ] }