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GET /api/patches/2216950/?format=api
{ "id": 2216950, "url": "http://patchwork.ozlabs.org/api/patches/2216950/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260327121015.996806-2-pranav.sanwal@amd.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327121015.996806-2-pranav.sanwal@amd.com>", "list_archive_url": null, "date": "2026-03-27T12:10:13", "name": "[1/3] pci: Add AMD Versal2 DW PCIe host controller driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b2061210d6fe5a7259fa35441f202f24da814ff1", "submitter": { "id": 92240, "url": "http://patchwork.ozlabs.org/api/people/92240/?format=api", "name": "Pranav Sanwal", "email": "pranav.sanwal@amd.com" }, "delegate": { "id": 1692, "url": "http://patchwork.ozlabs.org/api/users/1692/?format=api", "username": "monstr", "first_name": "Michal", "last_name": "Simek", "email": "monstr@monstr.eu" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260327121015.996806-2-pranav.sanwal@amd.com/mbox/", "series": [ { "id": 497757, "url": "http://patchwork.ozlabs.org/api/series/497757/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497757", "date": "2026-03-27T12:10:12", "name": "Add PCIe and NVMe support for AMD Versal Gen 2", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497757/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216950/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216950/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=wYGiBapN;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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helo=satlexmb07.amd.com; pr=C", "From": "Pranav Sanwal <pranav.sanwal@amd.com>", "To": "<u-boot@lists.denx.de>", "CC": "<git@amd.com>, <michal.simek@amd.com>", "Subject": "[PATCH 1/3] pci: Add AMD Versal2 DW PCIe host controller driver", "Date": "Fri, 27 Mar 2026 17:40:13 +0530", "Message-ID": "<20260327121015.996806-2-pranav.sanwal@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260327121015.996806-1-pranav.sanwal@amd.com>", "References": "<20260327121015.996806-1-pranav.sanwal@amd.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "CY4PEPF0000E9D6:EE_|PH7PR12MB8794:EE_", "X-MS-Office365-Filtering-Correlation-Id": "cf10cecd-3fc8-4d30-ffed-08de8bf9d6c3", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;\n ARA:13230040|82310400026|1800799024|36860700016|376014|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n QORnMj7SpVy+9+ksyNpriOxvhb1o1YPtgdYoGH5tILCXro9EKsVBvk4AzWY50nOC83L6aOyULwX3VO1DifpLSd4WRFHm+Hgeb513CpSv/wwEvDMZ9uUWErj7k4U0+SvLHyZUcQUYJJjjFAsavELy6+UvgvwfsuD1s4CYqkrmkBOHr27hU6jhY26R7VdSBRAsFSiz5GrxlocvBFvoKzQSqkXeJ3U4Cbh+KroEuqDx7iIXoBqwLykU12QZxWHCni/PPx4Zo9cUyG2qLpQaC/fThRB/N1vSagzlcrp8QRkgAa4CKMQphIaFRmcqnlcAtEuCvLypSsjdIzv4G+4nPCfTZKBtEyKX+jhAuS2A/WKILHxLwa5LH9HbBTdSZjISUHDhIhxe8ibYdWuGPda1It8SGrL4RbummdO/2r4BfFM/R8aE2PEPpeAZ1VfzJnqhfJekrZWb5KLH3NVqnlNH6WqB9k5qRwf8Rw4sRZvK4OGVBGI+5IaTKspzwOtCJnVVbYovpS6a2YeeHKaImW9KBhBAvl4i4/DP2pg1RRz2ObLINVCYWmICxyEKOAfGdzg5EVbaeEOejlog6uDR5EdhSBymfmPG74sBx84rnWFqOGl5g7OV77D9PrlErKGvsCMROid4wrd4AOCjX9AG/PX0ZcAunmBTJYAH8BZGTzJuhraJL8+tw+cFnZ2nNTYWrTPcWDwHdlz2ufjXEg9qDe9qrqblWIn4jncAGvUrxWVxo1nGkmc9RY9qkiC+FIhu4ApCD7guDV6/wsaOii33YBdWXibPzQ==", "X-Forefront-Antispam-Report": "CIP:165.204.84.17; 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Ip=[165.204.84.17];\n Helo=[satlexmb07.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CY4PEPF0000E9D6.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "PH7PR12MB8794", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add support for the DesignWare-based PCIe host controller found in\nAMD Versal2 SoCs. This enables PCIe functionality (e.g. NVMe storage)\non boards such as the VEK385.\n\nThe driver builds on the existing pcie_dw_common infrastructure and\nadds Versal2-specific handling: it maps the SLCR register region to\nmask and clear TLP interrupt status bits, parses dbi/config/atu/slcr\nregister regions from device tree, and supports an optional PERST#\nGPIO on child nodes for endpoint reset sequencing. The outbound iATU\nis programmed for the non-prefetchable memory window from device tree\nranges.\n\nSigned-off-by: Pranav Sanwal <pranav.sanwal@amd.com>\n---\n MAINTAINERS | 5 +\n drivers/pci/Kconfig | 11 ++\n drivers/pci/Makefile | 1 +\n drivers/pci/pcie_dw_amd.c | 250 ++++++++++++++++++++++++++++++++++++++\n 4 files changed, 267 insertions(+)\n create mode 100644 drivers/pci/pcie_dw_amd.c", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 4d168349ae6..a51586d5759 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -65,6 +65,11 @@ F:\tinclude/alist.h\n F:\tlib/alist.c\n F:\ttest/lib/alist.c\n \n+AMD VERSAL2 PCIE DRIVER\n+M:\tPranav Sanwal <pranav.sanwal@amd.com>\n+S:\tMaintained\n+F:\tdrivers/pci/pcie_dw_amd.c\n+\n ANDROID AB\n M:\tMattijs Korpershoek <mkorpershoek@kernel.org>\n R:\tIgor Opaniuk <igor.opaniuk@gmail.com>\ndiff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig\nindex 8fc57895a78..39df0e776df 100644\n--- a/drivers/pci/Kconfig\n+++ b/drivers/pci/Kconfig\n@@ -456,6 +456,17 @@ config PCIE_STARFIVE_JH7110\n \t Say Y here if you want to enable PLDA XpressRich PCIe controller\n \t support on StarFive JH7110 SoC.\n \n+config PCIE_DW_AMD\n+\tbool \"AMD Versal2 DW PCIe host controller\"\n+\tdepends on ARCH_VERSAL2\n+\tdepends on DM_GPIO\n+\tselect PCIE_DW_COMMON\n+\tselect SYS_PCI_64BIT\n+\thelp\n+\t Say Y here to enable support for the AMD Versal Gen 2 PCIe\n+\t host controller. This is a DesignWare-based PCIe controller\n+\t used in AMD Versal Gen 2 SoCs.\n+\n config PCIE_DW_IMX\n \tbool \"i.MX DW PCIe controller support\"\n \tdepends on ARCH_IMX8M || ARCH_IMX9\ndiff --git a/drivers/pci/Makefile b/drivers/pci/Makefile\nindex 98f3c226f63..e6d71fd172b 100644\n--- a/drivers/pci/Makefile\n+++ b/drivers/pci/Makefile\n@@ -56,4 +56,5 @@ obj-$(CONFIG_PCIE_UNIPHIER) += pcie_uniphier.o\n obj-$(CONFIG_PCIE_XILINX_NWL) += pcie-xilinx-nwl.o\n obj-$(CONFIG_PCIE_PLDA_COMMON) += pcie_plda_common.o\n obj-$(CONFIG_PCIE_STARFIVE_JH7110) += pcie_starfive_jh7110.o\n+obj-$(CONFIG_PCIE_DW_AMD) += pcie_dw_amd.o\n obj-$(CONFIG_PCIE_DW_IMX) += pcie_dw_imx.o\ndiff --git a/drivers/pci/pcie_dw_amd.c b/drivers/pci/pcie_dw_amd.c\nnew file mode 100644\nindex 00000000000..c5a30cd324a\n--- /dev/null\n+++ b/drivers/pci/pcie_dw_amd.c\n@@ -0,0 +1,250 @@\n+// SPDX-License-Identifier: GPL-2.0\n+/*\n+ * AMD Versal2 DesignWare PCIe host controller driver\n+ *\n+ * Copyright (C) 2025-2026 Advanced Micro Devices, Inc.\n+ * Author: Pranav Sanwal <pranav.sanwal@amd.com>\n+ */\n+\n+#include <dm.h>\n+#include <log.h>\n+#include <pci.h>\n+#include <wait_bit.h>\n+\n+#include <asm/gpio.h>\n+#include <asm/io.h>\n+#include <dm/device_compat.h>\n+#include <dm/ofnode.h>\n+#include <linux/delay.h>\n+\n+#include \"pcie_dw_common.h\"\n+\n+/*\n+ * SLCR (System Level Control Register) Interrupt Register Offsets\n+ * These are relative to the SLCR base address from device tree\n+ */\n+#define AMD_DW_TLP_IR_STATUS_MISC\t0x4c0\n+#define AMD_DW_TLP_IR_DISABLE_MISC\t0x4cc\n+\n+/* Interrupt bit definitions */\n+#define AMD_DW_PCIE_INTR_CMPL_TIMEOUT\t\t15\n+#define AMD_DW_PCIE_INTR_PM_PME_RCVD\t\t24\n+#define AMD_DW_PCIE_INTR_PME_TO_ACK_RCVD\t25\n+#define AMD_DW_PCIE_INTR_MISC_CORRECTABLE\t26\n+#define AMD_DW_PCIE_INTR_NONFATAL\t\t27\n+#define AMD_DW_PCIE_INTR_FATAL\t\t\t28\n+\n+#define AMD_DW_PCIE_INTR_INTX_MASK\t\tGENMASK(23, 16)\n+\n+#define AMD_DW_PCIE_IMR_ALL_MASK\t\\\n+\t(BIT(AMD_DW_PCIE_INTR_CMPL_TIMEOUT)\t| \\\n+\t BIT(AMD_DW_PCIE_INTR_PM_PME_RCVD)\t| \\\n+\t BIT(AMD_DW_PCIE_INTR_PME_TO_ACK_RCVD)\t| \\\n+\t BIT(AMD_DW_PCIE_INTR_MISC_CORRECTABLE)\t| \\\n+\t BIT(AMD_DW_PCIE_INTR_NONFATAL)\t\t| \\\n+\t BIT(AMD_DW_PCIE_INTR_FATAL)\t\t| \\\n+\t AMD_DW_PCIE_INTR_INTX_MASK)\n+\n+/* DW PCIe Debug Registers (in DBI space) */\n+#define AMD_DW_PCIE_PORT_DEBUG1\t\t\t0x72c\n+#define AMD_DW_PCIE_PORT_DEBUG1_LINK_UP\t\tBIT(4)\n+#define AMD_DW_PCIE_PORT_DEBUG1_LINK_IN_TRAINING\tBIT(29)\n+#define AMD_DW_PCIE_DBI_64BIT_MEM_DECODE\t\tBIT(0)\n+\n+/* Link training timeout */\n+#define LINK_WAIT_MSLEEP_MAX\t\t1000\n+\n+/* PCIe spec timing requirements */\n+#define PCIE_RESET_CONFIG_WAIT_MS\t100\n+#define PCIE_T_PERST_WAIT_MS\t\t1\n+\n+/**\n+ * struct amd_dw_pcie - AMD DesignWare PCIe controller private data\n+ * @dw: DesignWare PCIe common structure\n+ * @slcr_base: System Level Control Register base (for interrupts)\n+ */\n+struct amd_dw_pcie {\n+\tstruct pcie_dw dw;\n+\tvoid __iomem *slcr_base;\n+};\n+\n+static void amd_dw_pcie_init_port(struct amd_dw_pcie *pcie)\n+{\n+\tu32 val;\n+\n+\tif (!pcie->slcr_base)\n+\t\treturn;\n+\n+\t/* Disable all TLP interrupts */\n+\twritel(AMD_DW_PCIE_IMR_ALL_MASK,\n+\t pcie->slcr_base + AMD_DW_TLP_IR_DISABLE_MISC);\n+\n+\t/* Clear any pending TLP interrupts */\n+\tval = readl(pcie->slcr_base + AMD_DW_TLP_IR_STATUS_MISC);\n+\tval &= AMD_DW_PCIE_IMR_ALL_MASK;\n+\twritel(val, pcie->slcr_base + AMD_DW_TLP_IR_STATUS_MISC);\n+}\n+\n+static void amd_dw_pcie_start_link(struct amd_dw_pcie *pcie)\n+{\n+\tvoid __iomem *reg = pcie->dw.dbi_base + AMD_DW_PCIE_PORT_DEBUG1;\n+\tstruct udevice *dev = pcie->dw.dev;\n+\tstruct pcie_dw *pci = &pcie->dw;\n+\tint ret;\n+\n+\tret = wait_for_bit_le32(reg, AMD_DW_PCIE_PORT_DEBUG1_LINK_UP,\n+\t\t\t\ttrue, LINK_WAIT_MSLEEP_MAX,\n+\t\t\t\tfalse);\n+\tif (!ret)\n+\t\tret = wait_for_bit_le32(reg,\n+\t\t\t\t\tAMD_DW_PCIE_PORT_DEBUG1_LINK_IN_TRAINING,\n+\t\t\t\t\tfalse, LINK_WAIT_MSLEEP_MAX, false);\n+\tif (ret)\n+\t\tdev_warn(dev, \"PCIE-%d: Link down\\n\", dev_seq(dev));\n+\telse\n+\t\tdev_dbg(dev, \"PCIE-%d: Link up (Gen%d-x%d, Bus%d)\\n\",\n+\t\t\tdev_seq(dev), pcie_dw_get_link_speed(pci),\n+\t\t\tpcie_dw_get_link_width(pci), pci->first_busno);\n+}\n+\n+static void amd_dw_pcie_host_init(struct amd_dw_pcie *pcie)\n+{\n+\tstruct pcie_dw *pci = &pcie->dw;\n+\n+\t/*\n+\t * Set 64-bit prefetchable memory decode capability. U-Boot's pci_auto.c\n+\t * reads this bit before assigning prefetchable BARs. If cleared, it skips\n+\t * PCI_PREF_BASE_UPPER32 programming, causing 64-bit BAR assignment to fail.\n+\t */\n+\tdw_pcie_dbi_write_enable(pci, true);\n+\tsetbits_le32(pci->dbi_base + PCI_PREF_MEMORY_BASE,\n+\t\t AMD_DW_PCIE_DBI_64BIT_MEM_DECODE);\n+\tdw_pcie_dbi_write_enable(pci, false);\n+\n+\tamd_dw_pcie_init_port(pcie);\n+\tpcie_dw_setup_host(pci);\n+}\n+\n+static void amd_dw_pcie_request_gpio(struct udevice *dev)\n+{\n+\tstruct gpio_desc perst_gpio;\n+\tofnode child_node;\n+\tint ret;\n+\n+\t/*\n+\t * PERST# reset GPIO is optional. Child PCI endpoint nodes may carry a\n+\t * 'reset-gpios' property to toggle the endpoint reset signal during\n+\t * initialization. If absent, the endpoint is assumed to be already\n+\t * released from reset.\n+\t */\n+\tofnode_for_each_subnode(child_node, dev_ofnode(dev)) {\n+\t\tret = gpio_request_by_name_nodev(child_node, \"reset-gpios\", 0,\n+\t\t\t\t\t\t &perst_gpio, GPIOD_IS_OUT);\n+\t\tif (!ret) {\n+\t\t\tdev_dbg(dev, \"Found reset-gpios in child node %s\\n\",\n+\t\t\t\tofnode_get_name(child_node));\n+\t\t\tdm_gpio_set_value(&perst_gpio, 1);\n+\t\t\tmdelay(PCIE_T_PERST_WAIT_MS);\n+\t\t\tdm_gpio_set_value(&perst_gpio, 0);\n+\t\t\tmdelay(PCIE_RESET_CONFIG_WAIT_MS);\n+\t\t\tdm_gpio_free(dev, &perst_gpio);\n+\t\t}\n+\t}\n+}\n+\n+static int amd_dw_pcie_of_to_plat(struct udevice *dev)\n+{\n+\tstruct pci_region *io_region, *mem_region, *pref_region;\n+\tstruct amd_dw_pcie *pcie = dev_get_priv(dev);\n+\tstruct pcie_dw *pci = &pcie->dw;\n+\tint ret;\n+\n+\tpci->dev = dev;\n+\n+\tpci->dbi_base = dev_read_addr_name_ptr(dev, \"dbi\");\n+\tif (!pci->dbi_base) {\n+\t\tdev_err(dev, \"Missing 'dbi' register region\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpci->cfg_base = dev_read_addr_size_name_ptr(dev, \"config\", &pci->cfg_size);\n+\tif (!pci->cfg_base) {\n+\t\tdev_err(dev, \"Missing 'config' register region\\n\");\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tpci->atu_base = dev_read_addr_name_ptr(dev, \"atu\");\n+\tif (!pci->atu_base) {\n+\t\tdev_dbg(dev, \"No 'atu' region, using default offset from DBI\\n\");\n+\t\tpci->atu_base = pci->dbi_base + DEFAULT_DBI_ATU_OFFSET;\n+\t}\n+\n+\tpcie->slcr_base = dev_read_addr_name_ptr(dev, \"slcr\");\n+\tif (!pcie->slcr_base)\n+\t\tdev_dbg(dev, \"No 'slcr' region, interrupt features disabled\\n\");\n+\n+\tret = pci_get_regions(dev, &io_region, &mem_region, &pref_region);\n+\tif (ret < 0) {\n+\t\tdev_err(dev, \"Failed to get PCI regions: %d\\n\", ret);\n+\t\treturn ret;\n+\t}\n+\n+\tif (mem_region)\n+\t\tpci->mem = *mem_region;\n+\n+\treturn 0;\n+}\n+\n+static int amd_dw_pcie_probe(struct udevice *dev)\n+{\n+\tstruct amd_dw_pcie *pcie = dev_get_priv(dev);\n+\tstruct pcie_dw *pci = &pcie->dw;\n+\n+\t/* Set first bus number */\n+\tpci->first_busno = dev_seq(dev);\n+\n+\tamd_dw_pcie_request_gpio(dev);\n+\tamd_dw_pcie_host_init(pcie);\n+\tamd_dw_pcie_start_link(pcie);\n+\n+\tif (pci->mem.size) {\n+\t\tdev_dbg(dev, \"Programming ATU region 0 for MEM: phys=0x%llx bus=0x%llx size=0x%llx\\n\",\n+\t\t\t(unsigned long long)pci->mem.phys_start,\n+\t\t\t(unsigned long long)pci->mem.bus_start,\n+\t\t\t(unsigned long long)pci->mem.size);\n+\t\tpcie_dw_prog_outbound_atu_unroll(pci,\n+\t\t\t\t\t\t PCIE_ATU_REGION_INDEX0,\n+\t\t\t\t\t\t PCIE_ATU_TYPE_MEM,\n+\t\t\t\t\t\t pci->mem.phys_start,\n+\t\t\t\t\t\t pci->mem.bus_start,\n+\t\t\t\t\t\t pci->mem.size);\n+\t} else {\n+\t\tdev_warn(dev, \"No MEM region configured!\\n\");\n+\t}\n+\n+\tdev_dbg(dev, \"dbi: 0x%lx | config: 0x%lx | atu: 0x%lx | slcr: 0x%lx\\n\",\n+\t\t(long)pci->dbi_base, (long)pci->cfg_base,\n+\t\t(long)pci->atu_base, (long)pcie->slcr_base);\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_pci_ops amd_dw_pcie_ops = {\n+\t.read_config\t= pcie_dw_read_config,\n+\t.write_config\t= pcie_dw_write_config,\n+};\n+\n+static const struct udevice_id amd_dw_pcie_ids[] = {\n+\t{ .compatible = \"amd,versal2-mdb-host\" },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(pcie_dw_amd) = {\n+\t.name\t\t= \"pcie_dw_amd\",\n+\t.id\t\t= UCLASS_PCI,\n+\t.of_match\t= amd_dw_pcie_ids,\n+\t.ops\t\t= &amd_dw_pcie_ops,\n+\t.of_to_plat\t= amd_dw_pcie_of_to_plat,\n+\t.probe\t\t= amd_dw_pcie_probe,\n+\t.priv_auto\t= sizeof(struct amd_dw_pcie),\n+};\n", "prefixes": [ "1/3" ] }