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GET /api/patches/2216944/?format=api
{ "id": 2216944, "url": "http://patchwork.ozlabs.org/api/patches/2216944/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327-tpm-tis-sysbus-ppi-v2-2-d8ec84d25dbc@redhat.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327-tpm-tis-sysbus-ppi-v2-2-d8ec84d25dbc@redhat.com>", "list_archive_url": null, "date": "2026-03-27T11:48:23", "name": "[v2,2/3] hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "23c55005f417f8ede04a7017352bbfa971c0fe68", "submitter": { "id": 92626, "url": "http://patchwork.ozlabs.org/api/people/92626/?format=api", "name": "Mohammadfaiz Bawa", "email": "mbawa@redhat.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327-tpm-tis-sysbus-ppi-v2-2-d8ec84d25dbc@redhat.com/mbox/", "series": [ { "id": 497755, "url": "http://patchwork.ozlabs.org/api/series/497755/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497755", "date": "2026-03-27T11:48:21", "name": "hw/tpm: add PPI support to tpm-tis-device on ARM64 virt", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497755/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216944/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216944/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=redhat.com header.i=@redhat.com header.a=rsa-sha256\n header.s=mimecast20190719 header.b=IMbODeMz;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhzSg37bLz1yFr\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:49:07 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w65gU-0006wQ-Tr; Fri, 27 Mar 2026 07:49:02 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mbawa@redhat.com>) id 1w65gR-0006u9-1m\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:48:59 -0400", "from us-smtp-delivery-124.mimecast.com ([170.10.133.124])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <mbawa@redhat.com>) id 1w65gP-0000R2-BX\n for qemu-devel@nongnu.org; Fri, 27 Mar 2026 07:48:58 -0400", "from mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com\n (ec2-54-186-198-63.us-west-2.compute.amazonaws.com [54.186.198.63]) by\n relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.3,\n cipher=TLS_AES_256_GCM_SHA384) id us-mta-392-eZXR0pF_MKqnysy0nIhaYw-1; Fri,\n 27 Mar 2026 07:48:53 -0400", "from mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com\n (mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com [10.30.177.12])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest\n SHA256)\n (No client certificate requested)\n by mx-prod-mc-01.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTPS\n id E087E195608C; Fri, 27 Mar 2026 11:48:51 +0000 (UTC)", "from mbawa-thinkpadt14gen5.bengluru.csb (unknown [10.74.88.10])\n by mx-prod-int-03.mail-002.prod.us-west-2.aws.redhat.com (Postfix) with ESMTP\n id E6BC219560B1; Fri, 27 Mar 2026 11:48:45 +0000 (UTC)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com;\n s=mimecast20190719; t=1774612136;\n h=from:from:reply-to:subject:subject:date:date:message-id:message-id:\n to:to:cc:cc:mime-version:mime-version:content-type:content-type:\n content-transfer-encoding:content-transfer-encoding:\n in-reply-to:in-reply-to:references:references;\n bh=vNfBpMAfcLKVWxGQFoc6sYSvJTCHtumHh8ghhvrEnQM=;\n b=IMbODeMzZYlkA8MKtRkfOKgC8m2DDb9l8iMSUYW8IUedB9LNLYT3NvX8RjyaF8AglCHMbd\n qapqJ6fSRx0Q6BpayAu7K/wDVwJHKUiEs5xyzBcybxnLLRMHnAEofkk3MsrXku551uiQTO\n PfvrT9S7dO6Tghr8xHxudZRYYjEf/Zs=", "X-MC-Unique": "eZXR0pF_MKqnysy0nIhaYw-1", "X-Mimecast-MFC-AGG-ID": "eZXR0pF_MKqnysy0nIhaYw_1774612132", "From": "Mohammadfaiz Bawa <mbawa@redhat.com>", "To": "qemu-devel@nongnu.org", "Cc": "stefanb@linux.vnet.ibm.com, pierrick.bouvier@linaro.org,\n \"Michael S . Tsirkin\" <mst@redhat.com>, imammedo@redhat.com,\n anisinha@redhat.com, peter.maydell@linaro.org, shannon.zhaosl@gmail.com,\n qemu-arm@nongnu.org, mohamed@unpredictable.fr,\n Mohammadfaiz Bawa <mbawa@redhat.com>, Stefan Berger <stefanb@linux.ibm.com>", "Subject": "[PATCH v2 2/3] hw/acpi/tpm: parameterize PPI base address in\n tpm_build_ppi_acpi", "Date": "Fri, 27 Mar 2026 17:18:23 +0530", "Message-ID": "<20260327-tpm-tis-sysbus-ppi-v2-2-d8ec84d25dbc@redhat.com>", "In-Reply-To": "<20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com>", "References": "<20260327-tpm-tis-sysbus-ppi-v2-0-d8ec84d25dbc@redhat.com>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "X-Scanned-By": "MIMEDefang 3.0 on 10.30.177.12", "Received-SPF": "pass client-ip=170.10.133.124; envelope-from=mbawa@redhat.com;\n helo=us-smtp-delivery-124.mimecast.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001,\n RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001,\n SPF_HELO_PASS=-0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a ppi_base parameter to tpm_build_ppi_acpi() instead of\nhardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where\nPPI memory is dynamically allocated by the platform bus and the\naddress is not known at compile time.\n\nUpdate the x86 ISA TIS caller to pass TPM_PPI_ADDR_BASE explicitly.\nNo behavioral change.\n\nReviewed-by: Stefan Berger <stefanb@linux.ibm.com>\nSigned-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>\n---\n hw/acpi/tpm.c | 8 ++++----\n hw/tpm/tpm_tis_isa.c | 2 +-\n include/hw/acpi/tpm.h | 3 ++-\n 3 files changed, 7 insertions(+), 6 deletions(-)", "diff": "diff --git a/hw/acpi/tpm.c b/hw/acpi/tpm.c\nindex cdc022753659af102e56ea4148423b94de1531f6..c4ff2f8cb836c16b00f70865bf55781d5c402aa2 100644\n--- a/hw/acpi/tpm.c\n+++ b/hw/acpi/tpm.c\n@@ -20,7 +20,7 @@\n #include \"qapi/error.h\"\n #include \"hw/acpi/tpm.h\"\n \n-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base)\n {\n Aml *method, *field, *ifctx, *ifctx2, *ifctx3, *func_mask,\n *not_implemented, *pak, *tpm2, *tpm3, *pprm, *pprq, *zero, *one;\n@@ -40,7 +40,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n */\n aml_append(dev,\n aml_operation_region(\"TPP2\", AML_SYSTEM_MEMORY,\n- aml_int(TPM_PPI_ADDR_BASE + 0x100),\n+ aml_int(ppi_base + 0x100),\n 0x5A));\n field = aml_field(\"TPP2\", AML_ANY_ACC, AML_NOLOCK, AML_PRESERVE);\n aml_append(field, aml_named_field(\"PPIN\", 8));\n@@ -56,7 +56,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n aml_append(dev,\n aml_operation_region(\n \"TPP3\", AML_SYSTEM_MEMORY,\n- aml_int(TPM_PPI_ADDR_BASE +\n+ aml_int(ppi_base +\n 0x15a /* movv, docs/specs/tpm.rst */),\n 0x1));\n field = aml_field(\"TPP3\", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);\n@@ -78,7 +78,7 @@ void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev)\n \n aml_append(method,\n aml_operation_region(\"TPP1\", AML_SYSTEM_MEMORY,\n- aml_add(aml_int(TPM_PPI_ADDR_BASE), op, NULL), 0x1));\n+ aml_add(aml_int(ppi_base), op, NULL), 0x1));\n field = aml_field(\"TPP1\", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);\n aml_append(field, aml_named_field(\"TPPF\", 8));\n aml_append(method, field);\ndiff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c\nindex 61e95434f5b824fa99f0a2aff7f151e87ea631ed..e30bef49558673f4c857c02dae059ce3361a1bc7 100644\n--- a/hw/tpm/tpm_tis_isa.c\n+++ b/hw/tpm/tpm_tis_isa.c\n@@ -162,7 +162,7 @@ static void build_tpm_tis_isa_aml(AcpiDevAmlIf *adev, Aml *scope)\n */\n /* aml_append(crs, aml_irq_no_flags(isadev->state.irq_num)); */\n aml_append(dev, aml_name_decl(\"_CRS\", crs));\n- tpm_build_ppi_acpi(ti, dev);\n+ tpm_build_ppi_acpi(ti, dev, TPM_PPI_ADDR_BASE);\n aml_append(scope, dev);\n }\n \ndiff --git a/include/hw/acpi/tpm.h b/include/hw/acpi/tpm.h\nindex d2bf6637c5424b92ad99f5baa938fd6cea3520bf..2ab186a7455593df205a7ffecbea2abdfdbd11d5 100644\n--- a/include/hw/acpi/tpm.h\n+++ b/include/hw/acpi/tpm.h\n@@ -20,6 +20,7 @@\n #include \"hw/core/registerfields.h\"\n #include \"hw/acpi/aml-build.h\"\n #include \"system/tpm.h\"\n+#include \"exec/hwaddr.h\"\n \n #ifdef CONFIG_TPM\n \n@@ -250,7 +251,7 @@ REG32(CRB_DATA_BUFFER, 0x80)\n */\n #define TPM_I2C_INT_ENABLE_MASK 0x0\n \n-void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev);\n+void tpm_build_ppi_acpi(TPMIf *tpm, Aml *dev, hwaddr ppi_base);\n \n #endif /* CONFIG_TPM */\n \n", "prefixes": [ "v2", "2/3" ] }