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GET /api/patches/2216861/?format=api
{ "id": 2216861, "url": "http://patchwork.ozlabs.org/api/patches/2216861/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260327-ad4692-multichannel-sar-adc-driver-v5-2-11f789de47b8@analog.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327-ad4692-multichannel-sar-adc-driver-v5-2-11f789de47b8@analog.com>", "list_archive_url": null, "date": "2026-03-27T11:07:58", "name": "[v5,2/4] iio: adc: ad4691: add initial driver for AD4691 family", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ba7943c8a321f802973297c84a6696f1218d2a3a", "submitter": { "id": 92791, "url": "http://patchwork.ozlabs.org/api/people/92791/?format=api", "name": "Radu Sabau via B4 Relay", "email": "devnull+radu.sabau.analog.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260327-ad4692-multichannel-sar-adc-driver-v5-2-11f789de47b8@analog.com/mbox/", "series": [ { "id": 497747, "url": "http://patchwork.ozlabs.org/api/series/497747/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=497747", "date": "2026-03-27T11:07:57", "name": "iio: adc: ad4691: add driver for AD4691 multichannel SAR ADC family", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497747/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216861/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216861/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-34258-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Tn8g09xa;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-34258-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"Tn8g09xa\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhyc839Ddz1y1j\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 22:10:32 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 248F43055C93\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 11:08:48 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 623F53E7160;\n\tFri, 27 Mar 2026 11:08:11 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 827463E6DE0;\n\tFri, 27 Mar 2026 11:08:08 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id 61602C2BCB2;\n\tFri, 27 Mar 2026 11:08:07 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id 4877D10ED659;\n\tFri, 27 Mar 2026 11:08:07 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774609688; cv=none;\n b=mYlURsab7bZryiqE15VAYFubjrpwUmQT7auMP3KsE7mEnuBUECp/7bzyKcD24qhX4DYH1QUlpCHIXKGnEHGddHXTPf4ZBjG5YTaxVh8bQA11XjkVdz/TnRWk4pLcE1ro8AJFxOSRqkqKoXVOxRZ1pxcInRQicuWzsSsuMNpU43c=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774609688; c=relaxed/simple;\n\tbh=onsYAPTWUhtWT9aVV6zfjYf4cH1H/ovJJymieQUfvbE=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=S6AJUmcVnc+RzPxAKeah0tgzJvOq1XA4iOYovddEDC82pvzQ0ch7tVZJQfvHMmuDjkdrZLpAq8GveCk/Y7n+PlGddfdahFTwDSj2qpHiZomHYMnOjgT4cVhUzEpeyJJ5s67sEo6+xC7X1XFmebD1cO5ANyaXYHPGBu5rzXvf+Lc=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=Tn8g09xa; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774609687;\n\tbh=onsYAPTWUhtWT9aVV6zfjYf4cH1H/ovJJymieQUfvbE=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=Tn8g09xaS/utieMNxlCPrV1s8zY2SKHUqOkkKAwam3JDvHv55eN5YWHXWnXaoiCzx\n\t bvBKthjUzkbRK5xoIJq7cpOfCUtybYt8Yz9iNhW7EzBRdiwXi0Jk/Io7D4rCeija5x\n\t W78uDZpWuLqb7RGxj/5cQ+Aa/JVJ9MqB5/K9JrJwlTg2KXTi+78BGAGrGc9fxyo3DZ\n\t hpxvSX7fyx5Izs01TnmBtvo4hZntvb1pqObFpegrEmoVr3SDiagYnWi78/HoT6GrMj\n\t QBfS+qUN6rB0Mdjncx8OGqLRVD30IwHhc7gLLczYw4NhTiY1hwBFUEvnyOC0J5fdpH\n\t z68y+E4P90khQ==", "From": "Radu Sabau via B4 Relay <devnull+radu.sabau.analog.com@kernel.org>", "Date": "Fri, 27 Mar 2026 13:07:58 +0200", "Subject": "[PATCH v5 2/4] iio: adc: ad4691: add initial driver for AD4691\n family", "Precedence": "bulk", "X-Mailing-List": "linux-gpio@vger.kernel.org", "List-Id": "<linux-gpio.vger.kernel.org>", "List-Subscribe": "<mailto:linux-gpio+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-gpio+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "\n <20260327-ad4692-multichannel-sar-adc-driver-v5-2-11f789de47b8@analog.com>", "References": "\n <20260327-ad4692-multichannel-sar-adc-driver-v5-0-11f789de47b8@analog.com>", "In-Reply-To": "\n <20260327-ad4692-multichannel-sar-adc-driver-v5-0-11f789de47b8@analog.com>", "To": "Lars-Peter Clausen <lars@metafoo.de>,\n Michael Hennerich <Michael.Hennerich@analog.com>,\n Jonathan Cameron <jic23@kernel.org>, David Lechner <dlechner@baylibre.com>,\n\t=?utf-8?q?Nuno_S=C3=A1?= <nuno.sa@analog.com>,\n Andy Shevchenko <andy@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>,\n =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= <ukleinek@kernel.org>,\n Liam Girdwood <lgirdwood@gmail.com>, Mark Brown <broonie@kernel.org>,\n Linus Walleij <linusw@kernel.org>, Bartosz Golaszewski <brgl@kernel.org>,\n Philipp Zabel <p.zabel@pengutronix.de>, Jonathan Corbet <corbet@lwn.net>,\n Shuah Khan <skhan@linuxfoundation.org>", "Cc": "linux-iio@vger.kernel.org, devicetree@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org,\n linux-gpio@vger.kernel.org, linux-doc@vger.kernel.org,\n Radu Sabau <radu.sabau@analog.com>", "X-Mailer": "b4 0.14.3", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1774609685; l=23140;\n i=radu.sabau@analog.com; s=20260220; h=from:subject:message-id;\n bh=LsrVKbEDtdL9NLrz15mTBDx1r2cqJT7Gw+jONe3xcpo=;\n b=hjQwmqyEO/S6w6iJZtNIFCH41KIAsdFsEKWbXaC2VOR20WXXQdrQW/8izQEhE7Z0YGq/ousyL\n ZTA8/4hZqI9AAVFovFbceOVOqDg7xr55i2JidGAAAUyXyOHtg/KChjN", "X-Developer-Key": "i=radu.sabau@analog.com; a=ed25519;\n pk=lDPQHgn9jTdt0vo58Na9lLxLaE2mb330if71Cn+EvFU=", "X-Endpoint-Received": "by B4 Relay for radu.sabau@analog.com/20260220 with\n auth_id=642", "X-Original-From": "Radu Sabau <radu.sabau@analog.com>", "Reply-To": "radu.sabau@analog.com" }, "content": "From: Radu Sabau <radu.sabau@analog.com>\n\nAdd support for the Analog Devices AD4691 family of high-speed,\nlow-power multichannel SAR ADCs: AD4691 (16-ch, 500 kSPS),\nAD4692 (16-ch, 1 MSPS), AD4693 (8-ch, 500 kSPS) and\nAD4694 (8-ch, 1 MSPS).\n\nThe driver implements a custom regmap layer over raw SPI to handle the\ndevice's mixed 1/2/3/4-byte register widths and uses the standard IIO\nread_raw/write_raw interface for single-channel reads.\n\nThe chip idles in Autonomous Mode so that single-shot read_raw can use\nthe internal oscillator without disturbing the hardware configuration.\n\nThree voltage supply domains are managed: avdd (required), vio, and a\nreference supply on either the REF pin (ref-supply, external buffer)\nor the REFIN pin (refin-supply, uses the on-chip reference buffer;\nREFBUF_EN is set accordingly). Hardware reset is performed via\nthe reset controller framework; a software reset through SPI_CONFIG_A\nis used as fallback when no hardware reset is available.\n\nAccumulator channel masking for single-shot reads uses ACC_MASK_REG via\nan ADDR_DESCENDING SPI write, which covers both mask bytes in a single\n16-bit transfer.\n\nSigned-off-by: Radu Sabau <radu.sabau@analog.com>\n---\n MAINTAINERS | 1 +\n drivers/iio/adc/Kconfig | 11 +\n drivers/iio/adc/Makefile | 1 +\n drivers/iio/adc/ad4691.c | 690 +++++++++++++++++++++++++++++++++++++++++++++++\n 4 files changed, 703 insertions(+)", "diff": "diff --git a/MAINTAINERS b/MAINTAINERS\nindex 438ca850fa1c..24e4502b8292 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -1490,6 +1490,7 @@ L:\tlinux-iio@vger.kernel.org\n S:\tSupported\n W:\thttps://ez.analog.com/linux-software-drivers\n F:\tDocumentation/devicetree/bindings/iio/adc/adi,ad4691.yaml\n+F:\tdrivers/iio/adc/ad4691.c\n \n ANALOG DEVICES INC AD4695 DRIVER\n M:\tMichael Hennerich <michael.hennerich@analog.com>\ndiff --git a/drivers/iio/adc/Kconfig b/drivers/iio/adc/Kconfig\nindex 60038ae8dfc4..3685a03aa8dc 100644\n--- a/drivers/iio/adc/Kconfig\n+++ b/drivers/iio/adc/Kconfig\n@@ -139,6 +139,17 @@ config AD4170_4\n \t To compile this driver as a module, choose M here: the module will be\n \t called ad4170-4.\n \n+config AD4691\n+\ttristate \"Analog Devices AD4691 Family ADC Driver\"\n+\tdepends on SPI\n+\tselect REGMAP\n+\thelp\n+\t Say yes here to build support for Analog Devices AD4691 Family MuxSAR\n+\t SPI analog to digital converters (ADC).\n+\n+\t To compile this driver as a module, choose M here: the module will be\n+\t called ad4691.\n+\n config AD4695\n \ttristate \"Analog Device AD4695 ADC Driver\"\n \tdepends on SPI\ndiff --git a/drivers/iio/adc/Makefile b/drivers/iio/adc/Makefile\nindex c76550415ff1..4ac1ea09d773 100644\n--- a/drivers/iio/adc/Makefile\n+++ b/drivers/iio/adc/Makefile\n@@ -16,6 +16,7 @@ obj-$(CONFIG_AD4080) += ad4080.o\n obj-$(CONFIG_AD4130) += ad4130.o\n obj-$(CONFIG_AD4134) += ad4134.o\n obj-$(CONFIG_AD4170_4) += ad4170-4.o\n+obj-$(CONFIG_AD4691) += ad4691.o\n obj-$(CONFIG_AD4695) += ad4695.o\n obj-$(CONFIG_AD4851) += ad4851.o\n obj-$(CONFIG_AD7091R) += ad7091r-base.o\ndiff --git a/drivers/iio/adc/ad4691.c b/drivers/iio/adc/ad4691.c\nnew file mode 100644\nindex 000000000000..f930efdb9d8c\n--- /dev/null\n+++ b/drivers/iio/adc/ad4691.c\n@@ -0,0 +1,690 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (C) 2024-2026 Analog Devices, Inc.\n+ * Author: Radu Sabau <radu.sabau@analog.com>\n+ */\n+#include <linux/bitfield.h>\n+#include <linux/bitops.h>\n+#include <linux/cleanup.h>\n+#include <linux/delay.h>\n+#include <linux/device.h>\n+#include <linux/err.h>\n+#include <linux/math.h>\n+#include <linux/module.h>\n+#include <linux/mod_devicetable.h>\n+#include <linux/regmap.h>\n+#include <linux/regulator/consumer.h>\n+#include <linux/reset.h>\n+#include <linux/spi/spi.h>\n+#include <linux/units.h>\n+#include <linux/unaligned.h>\n+\n+#include <linux/iio/iio.h>\n+\n+#define AD4691_VREF_uV_MIN\t\t\t2400000\n+#define AD4691_VREF_uV_MAX\t\t\t5250000\n+#define AD4691_VREF_2P5_uV_MAX\t\t\t2750000\n+#define AD4691_VREF_3P0_uV_MAX\t\t\t3250000\n+#define AD4691_VREF_3P3_uV_MAX\t\t\t3750000\n+#define AD4691_VREF_4P096_uV_MAX\t\t4500000\n+\n+#define AD4691_SPI_CONFIG_A_REG\t\t\t0x000\n+#define AD4691_SW_RESET\t\t\t\t(BIT(7) | BIT(0))\n+\n+#define AD4691_STATUS_REG\t\t\t0x014\n+#define AD4691_CLAMP_STATUS1_REG\t\t0x01A\n+#define AD4691_CLAMP_STATUS2_REG\t\t0x01B\n+#define AD4691_DEVICE_SETUP\t\t\t0x020\n+#define AD4691_LDO_EN\t\t\t\tBIT(4)\n+#define AD4691_REF_CTRL\t\t\t\t0x021\n+#define AD4691_REF_CTRL_MASK\t\t\tGENMASK(4, 2)\n+#define AD4691_REFBUF_EN\t\t\tBIT(0)\n+#define AD4691_OSC_FREQ_REG\t\t\t0x023\n+#define AD4691_OSC_FREQ_MASK\t\t\tGENMASK(3, 0)\n+#define AD4691_STD_SEQ_CONFIG\t\t\t0x025\n+#define AD4691_SPARE_CONTROL\t\t\t0x02A\n+\n+#define AD4691_OSC_EN_REG\t\t\t0x180\n+#define AD4691_STATE_RESET_REG\t\t\t0x181\n+#define AD4691_STATE_RESET_ALL\t\t\t0x01\n+#define AD4691_ADC_SETUP\t\t\t0x182\n+#define AD4691_ADC_MODE_MASK\t\t\tGENMASK(1, 0)\n+#define AD4691_AUTONOMOUS_MODE\t\t\t0x02\n+/*\n+ * ACC_MASK_REG covers both mask bytes via ADDR_DESCENDING SPI: writing a\n+ * 16-bit BE value to 0x185 auto-decrements to 0x184 for the second byte.\n+ */\n+#define AD4691_ACC_MASK_REG\t\t\t0x185\n+#define AD4691_ACC_DEPTH_IN(n)\t\t\t(0x186 + (n))\n+#define AD4691_GPIO_MODE1_REG\t\t\t0x196\n+#define AD4691_GPIO_MODE2_REG\t\t\t0x197\n+#define AD4691_GPIO_READ\t\t\t0x1A0\n+#define AD4691_ACC_STATUS_FULL1_REG\t\t0x1B0\n+#define AD4691_ACC_STATUS_FULL2_REG\t\t0x1B1\n+#define AD4691_ACC_STATUS_OVERRUN1_REG\t\t0x1B2\n+#define AD4691_ACC_STATUS_OVERRUN2_REG\t\t0x1B3\n+#define AD4691_ACC_STATUS_SAT1_REG\t\t0x1B4\n+#define AD4691_ACC_STATUS_SAT2_REG\t\t0x1BE\n+#define AD4691_ACC_SAT_OVR_REG(n)\t\t(0x1C0 + (n))\n+#define AD4691_AVG_IN(n)\t\t\t(0x201 + (2 * (n)))\n+#define AD4691_AVG_STS_IN(n)\t\t\t(0x222 + (3 * (n)))\n+#define AD4691_ACC_IN(n)\t\t\t(0x252 + (3 * (n)))\n+#define AD4691_ACC_STS_DATA(n)\t\t\t(0x283 + (4 * (n)))\n+\n+enum ad4691_ref_ctrl {\n+\tAD4691_VREF_2P5 = 0,\n+\tAD4691_VREF_3P0 = 1,\n+\tAD4691_VREF_3P3 = 2,\n+\tAD4691_VREF_4P096 = 3,\n+\tAD4691_VREF_5P0 = 4,\n+};\n+\n+struct ad4691_chip_info {\n+\tconst struct iio_chan_spec *channels;\n+\tconst char *name;\n+\tunsigned int num_channels;\n+\tunsigned int max_rate;\n+};\n+\n+#define AD4691_CHANNEL(ch)\t\t\t\t\t\t\\\n+\t{\t\t\t\t\t\t\t\t\\\n+\t\t.type = IIO_VOLTAGE,\t\t\t\t\t\\\n+\t\t.indexed = 1,\t\t\t\t\t\t\\\n+\t\t.info_mask_separate = BIT(IIO_CHAN_INFO_RAW)\t\t\\\n+\t\t\t\t | BIT(IIO_CHAN_INFO_SAMP_FREQ),\t\\\n+\t\t.info_mask_separate_available =\t\t\t\t\\\n+\t\t\t\t BIT(IIO_CHAN_INFO_SAMP_FREQ),\t\\\n+\t\t.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE),\t\\\n+\t\t.channel = ch,\t\t\t\t\t\t\\\n+\t\t.scan_index = ch,\t\t\t\t\t\\\n+\t\t.scan_type = {\t\t\t\t\t\t\\\n+\t\t\t.sign = 'u',\t\t\t\t\t\\\n+\t\t\t.realbits = 16,\t\t\t\t\t\\\n+\t\t\t.storagebits = 16,\t\t\t\t\\\n+\t\t},\t\t\t\t\t\t\t\\\n+\t}\n+\n+static const struct iio_chan_spec ad4691_channels[] = {\n+\tAD4691_CHANNEL(0),\n+\tAD4691_CHANNEL(1),\n+\tAD4691_CHANNEL(2),\n+\tAD4691_CHANNEL(3),\n+\tAD4691_CHANNEL(4),\n+\tAD4691_CHANNEL(5),\n+\tAD4691_CHANNEL(6),\n+\tAD4691_CHANNEL(7),\n+\tAD4691_CHANNEL(8),\n+\tAD4691_CHANNEL(9),\n+\tAD4691_CHANNEL(10),\n+\tAD4691_CHANNEL(11),\n+\tAD4691_CHANNEL(12),\n+\tAD4691_CHANNEL(13),\n+\tAD4691_CHANNEL(14),\n+\tAD4691_CHANNEL(15),\n+};\n+\n+static const struct iio_chan_spec ad4693_channels[] = {\n+\tAD4691_CHANNEL(0),\n+\tAD4691_CHANNEL(1),\n+\tAD4691_CHANNEL(2),\n+\tAD4691_CHANNEL(3),\n+\tAD4691_CHANNEL(4),\n+\tAD4691_CHANNEL(5),\n+\tAD4691_CHANNEL(6),\n+\tAD4691_CHANNEL(7),\n+};\n+\n+/*\n+ * Internal oscillator frequency table. Index is the OSC_FREQ_REG[3:0] value.\n+ * Index 0 (1 MHz) is only valid for AD4692/AD4694; AD4691/AD4693 support\n+ * up to 500 kHz and use index 1 as their highest valid rate.\n+ */\n+static const int ad4691_osc_freqs[] = {\n+\t1000000,\t/* 0x0: 1 MHz */\n+\t500000,\t\t/* 0x1: 500 kHz */\n+\t400000,\t\t/* 0x2: 400 kHz */\n+\t250000,\t\t/* 0x3: 250 kHz */\n+\t200000,\t\t/* 0x4: 200 kHz */\n+\t167000,\t\t/* 0x5: 167 kHz */\n+\t133000,\t\t/* 0x6: 133 kHz */\n+\t125000,\t\t/* 0x7: 125 kHz */\n+\t100000,\t\t/* 0x8: 100 kHz */\n+\t50000,\t\t/* 0x9: 50 kHz */\n+\t25000,\t\t/* 0xA: 25 kHz */\n+\t12500,\t\t/* 0xB: 12.5 kHz */\n+\t10000,\t\t/* 0xC: 10 kHz */\n+\t5000,\t\t/* 0xD: 5 kHz */\n+\t2500,\t\t/* 0xE: 2.5 kHz */\n+\t1250,\t\t/* 0xF: 1.25 kHz */\n+};\n+\n+static const struct ad4691_chip_info ad4691_chip_info = {\n+\t.channels = ad4691_channels,\n+\t.name = \"ad4691\",\n+\t.num_channels = ARRAY_SIZE(ad4691_channels),\n+\t.max_rate = 500 * HZ_PER_KHZ,\n+};\n+\n+static const struct ad4691_chip_info ad4692_chip_info = {\n+\t.channels = ad4691_channels,\n+\t.name = \"ad4692\",\n+\t.num_channels = ARRAY_SIZE(ad4691_channels),\n+\t.max_rate = 1 * HZ_PER_MHZ,\n+};\n+\n+static const struct ad4691_chip_info ad4693_chip_info = {\n+\t.channels = ad4693_channels,\n+\t.name = \"ad4693\",\n+\t.num_channels = ARRAY_SIZE(ad4693_channels),\n+\t.max_rate = 500 * HZ_PER_KHZ,\n+};\n+\n+static const struct ad4691_chip_info ad4694_chip_info = {\n+\t.channels = ad4693_channels,\n+\t.name = \"ad4694\",\n+\t.num_channels = ARRAY_SIZE(ad4693_channels),\n+\t.max_rate = 1 * HZ_PER_MHZ,\n+};\n+\n+struct ad4691_state {\n+\tconst struct ad4691_chip_info *info;\n+\tstruct regmap *regmap;\n+\tint vref_uV;\n+\tbool refbuf_en;\n+\tbool ldo_en;\n+\t/*\n+\t * Synchronize access to members of the driver state, and ensure\n+\t * atomicity of consecutive SPI operations.\n+\t */\n+\tstruct mutex lock;\n+};\n+\n+static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *val)\n+{\n+\tstruct spi_device *spi = context;\n+\tu8 tx[2], rx[4];\n+\tint ret;\n+\n+\t/* Set bit 15 to mark the operation as READ. */\n+\tput_unaligned_be16(0x8000 | reg, tx);\n+\n+\tswitch (reg) {\n+\tcase 0 ... AD4691_OSC_FREQ_REG:\n+\tcase AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15):\n+\t\tret = spi_write_then_read(spi, tx, 2, rx, 1);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\t*val = rx[0];\n+\t\treturn 0;\n+\tcase AD4691_STD_SEQ_CONFIG:\n+\tcase AD4691_AVG_IN(0) ... AD4691_AVG_IN(15):\n+\t\tret = spi_write_then_read(spi, tx, 2, rx, 2);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\t*val = get_unaligned_be16(rx);\n+\t\treturn 0;\n+\tcase AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15):\n+\tcase AD4691_ACC_IN(0) ... AD4691_ACC_IN(15):\n+\t\tret = spi_write_then_read(spi, tx, 2, rx, 3);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\t*val = get_unaligned_be24(rx);\n+\t\treturn 0;\n+\tcase AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15):\n+\t\tret = spi_write_then_read(spi, tx, 2, rx, 4);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\t\t*val = get_unaligned_be32(rx);\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int ad4691_reg_write(void *context, unsigned int reg, unsigned int val)\n+{\n+\tstruct spi_device *spi = context;\n+\tu8 tx[4];\n+\n+\tput_unaligned_be16(reg, tx);\n+\n+\tswitch (reg) {\n+\tcase 0 ... AD4691_OSC_FREQ_REG:\n+\tcase AD4691_SPARE_CONTROL ... AD4691_ACC_MASK_REG - 1:\n+\tcase AD4691_ACC_MASK_REG + 1 ... AD4691_GPIO_MODE2_REG:\n+\t\tif (val > 0xFF)\n+\t\t\treturn -EINVAL;\n+\t\ttx[2] = val;\n+\t\treturn spi_write_then_read(spi, tx, 3, NULL, 0);\n+\tcase AD4691_ACC_MASK_REG:\n+\tcase AD4691_STD_SEQ_CONFIG:\n+\t\tif (val > 0xFFFF)\n+\t\t\treturn -EINVAL;\n+\t\tput_unaligned_be16(val, &tx[2]);\n+\t\treturn spi_write_then_read(spi, tx, 4, NULL, 0);\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static bool ad4691_volatile_reg(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase AD4691_STATUS_REG:\n+\tcase AD4691_CLAMP_STATUS1_REG:\n+\tcase AD4691_CLAMP_STATUS2_REG:\n+\tcase AD4691_GPIO_READ:\n+\tcase AD4691_ACC_STATUS_FULL1_REG ... AD4691_ACC_STATUS_SAT2_REG:\n+\tcase AD4691_ACC_SAT_OVR_REG(0) ... AD4691_ACC_SAT_OVR_REG(15):\n+\tcase AD4691_AVG_IN(0) ... AD4691_AVG_IN(15):\n+\tcase AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15):\n+\tcase AD4691_ACC_IN(0) ... AD4691_ACC_IN(15):\n+\tcase AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15):\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+static bool ad4691_readable_reg(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase 0 ... AD4691_OSC_FREQ_REG:\n+\tcase AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15):\n+\tcase AD4691_STD_SEQ_CONFIG:\n+\tcase AD4691_AVG_IN(0) ... AD4691_AVG_IN(15):\n+\tcase AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15):\n+\tcase AD4691_ACC_IN(0) ... AD4691_ACC_IN(15):\n+\tcase AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15):\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+static bool ad4691_writeable_reg(struct device *dev, unsigned int reg)\n+{\n+\tswitch (reg) {\n+\tcase 0 ... AD4691_OSC_FREQ_REG:\n+\tcase AD4691_STD_SEQ_CONFIG:\n+\tcase AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG:\n+\t\treturn true;\n+\tdefault:\n+\t\treturn false;\n+\t}\n+}\n+\n+static const struct regmap_config ad4691_regmap_config = {\n+\t.reg_bits = 16,\n+\t.val_bits = 32,\n+\t.reg_read = ad4691_reg_read,\n+\t.reg_write = ad4691_reg_write,\n+\t.volatile_reg = ad4691_volatile_reg,\n+\t.readable_reg = ad4691_readable_reg,\n+\t.writeable_reg = ad4691_writeable_reg,\n+\t.max_register = AD4691_ACC_STS_DATA(15),\n+\t.cache_type = REGCACHE_MAPLE,\n+};\n+\n+static int ad4691_get_sampling_freq(struct ad4691_state *st, int *val)\n+{\n+\tunsigned int reg_val;\n+\tint ret;\n+\n+\tret = regmap_read(st->regmap, AD4691_OSC_FREQ_REG, ®_val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*val = ad4691_osc_freqs[FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val)];\n+\treturn IIO_VAL_INT;\n+}\n+\n+static int ad4691_set_sampling_freq(struct iio_dev *indio_dev, int freq)\n+{\n+\tstruct ad4691_state *st = iio_priv(indio_dev);\n+\tunsigned int start = (st->info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1;\n+\tunsigned int i;\n+\n+\tIIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);\n+\tif (IIO_DEV_ACQUIRE_FAILED(claim))\n+\t\treturn -EBUSY;\n+\n+\tfor (i = start; i < ARRAY_SIZE(ad4691_osc_freqs); i++) {\n+\t\tif (ad4691_osc_freqs[i] != freq)\n+\t\t\tcontinue;\n+\t\treturn regmap_update_bits(st->regmap, AD4691_OSC_FREQ_REG,\n+\t\t\t\t\t AD4691_OSC_FREQ_MASK, i);\n+\t}\n+\n+\treturn -EINVAL;\n+}\n+\n+static int ad4691_read_avail(struct iio_dev *indio_dev,\n+\t\t\t struct iio_chan_spec const *chan,\n+\t\t\t const int **vals, int *type,\n+\t\t\t int *length, long mask)\n+{\n+\tstruct ad4691_state *st = iio_priv(indio_dev);\n+\tunsigned int start = (st->info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1;\n+\n+\tswitch (mask) {\n+\tcase IIO_CHAN_INFO_SAMP_FREQ:\n+\t\t*vals = &ad4691_osc_freqs[start];\n+\t\t*type = IIO_VAL_INT;\n+\t\t*length = ARRAY_SIZE(ad4691_osc_freqs) - start;\n+\t\treturn IIO_AVAIL_LIST;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int ad4691_single_shot_read(struct iio_dev *indio_dev,\n+\t\t\t\t struct iio_chan_spec const *chan, int *val)\n+{\n+\tstruct ad4691_state *st = iio_priv(indio_dev);\n+\tunsigned int reg_val;\n+\tint ret;\n+\n+\tguard(mutex)(&st->lock);\n+\n+\t/*\n+\t * Use AUTONOMOUS mode for single-shot reads.\n+\t */\n+\tret = regmap_write(st->regmap, AD4691_STATE_RESET_REG,\n+\t\t\t AD4691_STATE_RESET_ALL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG,\n+\t\t\t BIT(chan->channel));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_write(st->regmap, AD4691_ACC_MASK_REG,\n+\t\t\t (u16)~BIT(chan->channel));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_read(st->regmap, AD4691_OSC_FREQ_REG, ®_val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 1);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t/*\n+\t * Wait for at least 2 internal oscillator periods for the\n+\t * conversion to complete.\n+\t */\n+\tfsleep(DIV_ROUND_UP(2 * USEC_PER_SEC, ad4691_osc_freqs[FIELD_GET(AD4691_OSC_FREQ_MASK, reg_val)]));\n+\n+\tret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 0);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = regmap_read(st->regmap, AD4691_AVG_IN(chan->channel), ®_val);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\t*val = reg_val;\n+\n+\tret = regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn IIO_VAL_INT;\n+}\n+\n+static int ad4691_read_raw(struct iio_dev *indio_dev,\n+\t\t\t struct iio_chan_spec const *chan, int *val,\n+\t\t\t int *val2, long info)\n+{\n+\tstruct ad4691_state *st = iio_priv(indio_dev);\n+\n+\tswitch (info) {\n+\tcase IIO_CHAN_INFO_RAW: {\n+\t\tIIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);\n+\t\tif (IIO_DEV_ACQUIRE_FAILED(claim))\n+\t\t\treturn -EBUSY;\n+\n+\t\treturn ad4691_single_shot_read(indio_dev, chan, val);\n+\t}\n+\tcase IIO_CHAN_INFO_SAMP_FREQ:\n+\t\treturn ad4691_get_sampling_freq(st, val);\n+\tcase IIO_CHAN_INFO_SCALE:\n+\t\t*val = st->vref_uV / (MICRO / MILLI);\n+\t\t*val2 = chan->scan_type.realbits;\n+\t\treturn IIO_VAL_FRACTIONAL_LOG2;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int ad4691_write_raw(struct iio_dev *indio_dev,\n+\t\t\t struct iio_chan_spec const *chan,\n+\t\t\t int val, int val2, long mask)\n+{\n+\tswitch (mask) {\n+\tcase IIO_CHAN_INFO_SAMP_FREQ:\n+\t\treturn ad4691_set_sampling_freq(indio_dev, val);\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int ad4691_reg_access(struct iio_dev *indio_dev, unsigned int reg,\n+\t\t\t unsigned int writeval, unsigned int *readval)\n+{\n+\tstruct ad4691_state *st = iio_priv(indio_dev);\n+\n+\tguard(mutex)(&st->lock);\n+\n+\tif (readval)\n+\t\treturn regmap_read(st->regmap, reg, readval);\n+\n+\treturn regmap_write(st->regmap, reg, writeval);\n+}\n+\n+static const struct iio_info ad4691_info = {\n+\t.read_raw = &ad4691_read_raw,\n+\t.write_raw = &ad4691_write_raw,\n+\t.read_avail = &ad4691_read_avail,\n+\t.debugfs_reg_access = &ad4691_reg_access,\n+};\n+\n+static int ad4691_regulator_setup(struct ad4691_state *st)\n+{\n+\tstruct device *dev = regmap_get_device(st->regmap);\n+\tint ret;\n+\n+\tret = devm_regulator_get_enable(dev, \"avdd\");\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to get and enable AVDD\\n\");\n+\n+\tret = devm_regulator_get_enable(dev, \"vio\");\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to get and enable VIO\\n\");\n+\n+\tret = devm_regulator_get_enable(dev, \"ldo-in\");\n+\tif (ret == -ENODEV)\n+\t\tst->ldo_en = true;\n+\telse if (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to get and enable LDO-IN\\n\");\n+\n+\tst->vref_uV = devm_regulator_get_enable_read_voltage(dev, \"ref\");\n+\tif (st->vref_uV == -ENODEV) {\n+\t\tst->vref_uV = devm_regulator_get_enable_read_voltage(dev, \"refin\");\n+\t\tst->refbuf_en = true;\n+\t}\n+\tif (st->vref_uV < 0)\n+\t\treturn dev_err_probe(dev, st->vref_uV,\n+\t\t\t\t \"Failed to get reference supply\\n\");\n+\n+\tif (st->vref_uV < AD4691_VREF_uV_MIN || st->vref_uV > AD4691_VREF_uV_MAX)\n+\t\treturn dev_err_probe(dev, -EINVAL,\n+\t\t\t\t \"vref(%d) must be in the range [%u...%u]\\n\",\n+\t\t\t\t st->vref_uV, AD4691_VREF_uV_MIN,\n+\t\t\t\t AD4691_VREF_uV_MAX);\n+\n+\treturn 0;\n+}\n+\n+static int ad4691_reset(struct ad4691_state *st)\n+{\n+\tstruct device *dev = regmap_get_device(st->regmap);\n+\tstruct reset_control *rst;\n+\n+\trst = devm_reset_control_get_optional_exclusive(dev, NULL);\n+\tif (IS_ERR(rst))\n+\t\treturn dev_err_probe(dev, PTR_ERR(rst), \"Failed to get reset\\n\");\n+\n+\tif (rst) {\n+\t\t/*\n+\t\t * The GPIO is already asserted by reset_gpio_probe (GPIOD_OUT_HIGH).\n+\t\t * Wait for the reset pulse width required by the chip. See datasheet Table 5.\n+\t\t */\n+\t\tfsleep(300);\n+\t\treturn reset_control_deassert(rst);\n+\t}\n+\n+\t/* No hardware reset available, fall back to software reset. */\n+\treturn regmap_write(st->regmap, AD4691_SPI_CONFIG_A_REG,\n+\t\t\t AD4691_SW_RESET);\n+}\n+\n+static int ad4691_config(struct ad4691_state *st)\n+{\n+\tstruct device *dev = regmap_get_device(st->regmap);\n+\tenum ad4691_ref_ctrl ref_val;\n+\tint ret;\n+\n+\tswitch (st->vref_uV) {\n+\tcase AD4691_VREF_uV_MIN ... AD4691_VREF_2P5_uV_MAX:\n+\t\tref_val = AD4691_VREF_2P5;\n+\t\tbreak;\n+\tcase AD4691_VREF_2P5_uV_MAX + 1 ... AD4691_VREF_3P0_uV_MAX:\n+\t\tref_val = AD4691_VREF_3P0;\n+\t\tbreak;\n+\tcase AD4691_VREF_3P0_uV_MAX + 1 ... AD4691_VREF_3P3_uV_MAX:\n+\t\tref_val = AD4691_VREF_3P3;\n+\t\tbreak;\n+\tcase AD4691_VREF_3P3_uV_MAX + 1 ... AD4691_VREF_4P096_uV_MAX:\n+\t\tref_val = AD4691_VREF_4P096;\n+\t\tbreak;\n+\tcase AD4691_VREF_4P096_uV_MAX + 1 ... AD4691_VREF_uV_MAX:\n+\t\tref_val = AD4691_VREF_5P0;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn dev_err_probe(dev, -EINVAL,\n+\t\t\t\t \"Unsupported vref voltage: %d uV\\n\",\n+\t\t\t\t st->vref_uV);\n+\t}\n+\n+\tret = regmap_update_bits(st->regmap, AD4691_REF_CTRL,\n+\t\t\t\t AD4691_REF_CTRL_MASK | AD4691_REFBUF_EN,\n+\t\t\t\t FIELD_PREP(AD4691_REF_CTRL_MASK, ref_val) |\n+\t\t\t\t (st->refbuf_en ? AD4691_REFBUF_EN : 0));\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to write REF_CTRL\\n\");\n+\n+\tret = regmap_assign_bits(st->regmap, AD4691_DEVICE_SETUP,\n+\t\t\t\t AD4691_LDO_EN, st->ldo_en);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to write DEVICE_SETUP\\n\");\n+\n+\t/*\n+\t * Set the internal oscillator to the highest rate this chip supports.\n+\t * Index 0 (1 MHz) exceeds the 500 kHz max of AD4691/AD4693, so those\n+\t * chips start at index 1 (500 kHz).\n+\t */\n+\tret = regmap_update_bits(st->regmap, AD4691_OSC_FREQ_REG,\n+\t\t\t\t AD4691_OSC_FREQ_MASK,\n+\t\t\t\t (st->info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to write OSC_FREQ\\n\");\n+\n+\tret = regmap_update_bits(st->regmap, AD4691_ADC_SETUP,\n+\t\t\t\t AD4691_ADC_MODE_MASK, AD4691_AUTONOMOUS_MODE);\n+\tif (ret)\n+\t\treturn dev_err_probe(dev, ret, \"Failed to write ADC_SETUP\\n\");\n+\n+\treturn 0;\n+}\n+\n+static int ad4691_probe(struct spi_device *spi)\n+{\n+\tstruct device *dev = &spi->dev;\n+\tstruct iio_dev *indio_dev;\n+\tstruct ad4691_state *st;\n+\tint ret;\n+\n+\tindio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));\n+\tif (!indio_dev)\n+\t\treturn -ENOMEM;\n+\n+\tst = iio_priv(indio_dev);\n+\tst->info = spi_get_device_match_data(spi);\n+\n+\tret = devm_mutex_init(dev, &st->lock);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tst->regmap = devm_regmap_init(dev, NULL, spi, &ad4691_regmap_config);\n+\tif (IS_ERR(st->regmap))\n+\t\treturn dev_err_probe(dev, PTR_ERR(st->regmap),\n+\t\t\t\t \"Failed to initialize regmap\\n\");\n+\n+\tret = ad4691_regulator_setup(st);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ad4691_reset(st);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = ad4691_config(st);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tindio_dev->name = st->info->name;\n+\tindio_dev->info = &ad4691_info;\n+\tindio_dev->modes = INDIO_DIRECT_MODE;\n+\n+\tindio_dev->channels = st->info->channels;\n+\tindio_dev->num_channels = st->info->num_channels;\n+\n+\treturn devm_iio_device_register(dev, indio_dev);\n+}\n+\n+static const struct of_device_id ad4691_of_match[] = {\n+\t{ .compatible = \"adi,ad4691\", .data = &ad4691_chip_info },\n+\t{ .compatible = \"adi,ad4692\", .data = &ad4692_chip_info },\n+\t{ .compatible = \"adi,ad4693\", .data = &ad4693_chip_info },\n+\t{ .compatible = \"adi,ad4694\", .data = &ad4694_chip_info },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(of, ad4691_of_match);\n+\n+static const struct spi_device_id ad4691_id[] = {\n+\t{ \"ad4691\", (kernel_ulong_t)&ad4691_chip_info },\n+\t{ \"ad4692\", (kernel_ulong_t)&ad4692_chip_info },\n+\t{ \"ad4693\", (kernel_ulong_t)&ad4693_chip_info },\n+\t{ \"ad4694\", (kernel_ulong_t)&ad4694_chip_info },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(spi, ad4691_id);\n+\n+static struct spi_driver ad4691_driver = {\n+\t.driver = {\n+\t\t.name = \"ad4691\",\n+\t\t.of_match_table = ad4691_of_match,\n+\t},\n+\t.probe = ad4691_probe,\n+\t.id_table = ad4691_id,\n+};\n+module_spi_driver(ad4691_driver);\n+\n+MODULE_AUTHOR(\"Radu Sabau <radu.sabau@analog.com>\");\n+MODULE_DESCRIPTION(\"Analog Devices AD4691 Family ADC Driver\");\n+MODULE_LICENSE(\"GPL\");\n", "prefixes": [ "v5", "2/4" ] }