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GET /api/patches/2216793/?format=api
{ "id": 2216793, "url": "http://patchwork.ozlabs.org/api/patches/2216793/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260327072236.129802-3-aleksandr.loktionov@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327072236.129802-3-aleksandr.loktionov@intel.com>", "list_archive_url": null, "date": "2026-03-27T07:22:34", "name": "[iwl-next] ice: check cross-timestamp timeout bits", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "34a13d1e7479c8b07ea1268df16954917a6c411e", "submitter": { "id": 75597, "url": "http://patchwork.ozlabs.org/api/people/75597/?format=api", "name": "Loktionov, Aleksandr", "email": "aleksandr.loktionov@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260327072236.129802-3-aleksandr.loktionov@intel.com/mbox/", "series": [ { "id": 497702, "url": "http://patchwork.ozlabs.org/api/series/497702/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=497702", "date": "2026-03-27T07:22:34", "name": "[iwl-next] ice: check cross-timestamp timeout bits", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497702/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216793/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216793/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", 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t=1774596163;\n\tbh=sZ7xR3HoNQH6K+iAZyaEK0+hiE5rMrnu/Tn/iSpht/w=;\n\th=From:To:Cc:Date:In-Reply-To:References:Subject:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t From;\n\tb=3t1xOhYj4Tv5pGP1/qU3fl1dRnH63aR1EplWsOAfJQuRwWWxe5ZDUwe1mlCskDj2Z\n\t fiQm6BcLxwq7GeV2GKiBTj+Dxg5mzI2y3KRM677Wyt3NPEUUj7ZD8ub/bgzctg6y07\n\t n9w7Z/bNwASbmn9cwJFENU3vuLDU6d0k9OBYHx5rxQJm7YRy1XR6AyHOxR+Dyzmndb\n\t 9jd7+w0Jsj9110G0pe8Bxvvx2JYcyErVNl44ho0HjvrArZewk5K0Jr9PgYeHe7MOk8\n\t rUd2Io3G9+ZYV1qGCGOGeYY4QQjc7f0LlcM0sSA+3/iVHkqYOFVxP61a0H7ZVi5hnU\n\t S/0Gs4is7IIMA==", "Received-SPF": "Pass (mailfrom) identity=mailfrom; client-ip=192.198.163.18;\n helo=mgamail.intel.com; envelope-from=aleksandr.loktionov@intel.com;\n receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp3.osuosl.org 3849961246", "X-CSE-ConnectionGUID": [ "nvNsZOv+SmCcMzgnPQjaTg==", "53a4fqgwSO+6KlqFPtqoqQ==" ], "X-CSE-MsgGUID": [ "tkH+uQN9Q3iC+L3z3YqUHQ==", "pm6Mj2bZQZ+vkoomyH63yw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"74848618\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"74848618\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"222359496\"" ], "X-ExtLoop1": "1", "From": "Aleksandr Loktionov <aleksandr.loktionov@intel.com>", "To": "intel-wired-lan@lists.osuosl.org, anthony.l.nguyen@intel.com,\n aleksandr.loktionov@intel.com", "Cc": "netdev@vger.kernel.org", "Date": "Fri, 27 Mar 2026 08:22:34 +0100", "Message-ID": "<20260327072236.129802-3-aleksandr.loktionov@intel.com>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260327072236.129802-1-aleksandr.loktionov@intel.com>", "References": "<20260327072236.129802-1-aleksandr.loktionov@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774596161; x=1806132161;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=UG0TXdzOm7/f9TplyZuK66CItEUmN3gfFSEbWaZGIk4=;\n b=AMW2oAzn1kjb91j/wAqp4tv7Qo6hKCwI99EJblt9FRhU5IByFk8abDAi\n 7WS3fRH2Xuia2D88NodQQDLtFbW6O/VjL1EVyurMoZ2Q5qQauryRhocO9\n WQq6/zK8g4qbrPRTl3hNH/oSEn11qzsL18yhIlJT1SjuFMDDfZGytMNCA\n m+FSIobsLkC4iEJdWGyTFWF8qTLXcNu0pJN3jdc5xamQdks3uxmg5EDYz\n HlxWFvl2x+js4hI5T0Xudtdbc8JR3g2fRKPHBOtvCjiEXCQ8hUE05nMK9\n CtbIdzmWzWco4EBj7fltdNgilIHE85f67QXSJxVemBCvZzRtSsnKw190E\n Q==;", "X-Mailman-Original-Authentication-Results": [ "smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com", "smtp3.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=AMW2oAzn" ], "Subject": "[Intel-wired-lan] [PATCH iwl-next] ice: check cross-timestamp\n timeout bits", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "From: Karol Kolacinski <karol.kolacinski@intel.com>\n\nPolling for cross-timestamp active bit depends on HW scheduling and\nactual timeout may happen before the driver finishes polling.\n\nCheck cross-timestamp timeout bits to ensure that the driver finishes\nthe operation earlier when HW indicates timeout.\n\nFixes: 92456e795ac6 (\"ice: Add unified ice_capture_crosststamp\")\nSigned-off-by: Karol Kolacinski <karol.kolacinski@intel.com>\nSigned-off-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>\n---\n\n drivers/net/ethernet/intel/ice/ice_hw_autogen.h | 3 +++\n drivers/net/ethernet/intel/ice/ice_ptp.c | 12 ++++++++++--\n 2 files changed, 13 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\nindex 082ad33..8b4884e 100644\n--- a/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n+++ b/drivers/net/ethernet/intel/ice/ice_hw_autogen.h\n@@ -499,6 +499,8 @@\n #define PRTRPB_RDPC\t\t\t\t0x000AC260\n #define GLHH_ART_CTL\t\t\t\t0x000A41D4\n #define GLHH_ART_CTL_ACTIVE_M\t\t\tBIT(0)\n+#define GLHH_ART_CTL_TIME_OUT1_M\t\tBIT(1)\n+#define GLHH_ART_CTL_TIME_OUT2_M\t\tBIT(2)\n #define GLHH_ART_TIME_H\t\t\t\t0x000A41D8\n #define GLHH_ART_TIME_L\t\t\t\t0x000A41DC\n #define GLTSYN_AUX_IN_0(_i)\t\t\t(0x000889D8 + ((_i) * 4))\n@@ -564,6 +566,7 @@\n #define E830_PRTTSYN_TXTIME_L(_i)\t\t(0x001E5000 + ((_i) * 32))\n #define E830_GLPTM_ART_CTL\t\t\t0x00088B50\n #define E830_GLPTM_ART_CTL_ACTIVE_M\t\tBIT(0)\n+#define E830_GLPTM_ART_CTL_TIME_OUT_M\t\tBIT(1)\n #define E830_GLPTM_ART_TIME_H\t\t\t0x00088B54\n #define E830_GLPTM_ART_TIME_L\t\t\t0x00088B58\n #define E830_GLTSYN_PTMTIME_H(_i)\t\t(0x00088B48 + ((_i) * 4))\ndiff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c\nindex 6848b1c..8b0530b 100644\n--- a/drivers/net/ethernet/intel/ice/ice_ptp.c\n+++ b/drivers/net/ethernet/intel/ice/ice_ptp.c\n@@ -2011,6 +2011,7 @@ static int ice_ptp_adjtime(struct ptp_clock_info *info, s64 delta)\n * @lock_busy: Bit in the semaphore lock indicating the lock is busy\n * @ctl_reg: The hardware register to request cross timestamp\n * @ctl_active: Bit in the control register to request cross timestamp\n+ * @ctl_timeout: Bits in the control register to indicate HW timeout\n * @art_time_l: Lower 32-bits of ART system time\n * @art_time_h: Upper 32-bits of ART system time\n * @dev_time_l: Lower 32-bits of device time (per timer index)\n@@ -2024,6 +2025,7 @@ struct ice_crosststamp_cfg {\n \t/* Capture control register */\n \tu32 ctl_reg;\n \tu32 ctl_active;\n+\tu32 ctl_timeout;\n \n \t/* Time storage */\n \tu32 art_time_l;\n@@ -2037,6 +2039,7 @@ static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e82x = {\n \t.lock_busy = PFHH_SEM_BUSY_M,\n \t.ctl_reg = GLHH_ART_CTL,\n \t.ctl_active = GLHH_ART_CTL_ACTIVE_M,\n+\t.ctl_timeout = GLHH_ART_CTL_TIME_OUT1_M | GLHH_ART_CTL_TIME_OUT2_M,\n \t.art_time_l = GLHH_ART_TIME_L,\n \t.art_time_h = GLHH_ART_TIME_H,\n \t.dev_time_l[0] = GLTSYN_HHTIME_L(0),\n@@ -2051,6 +2054,7 @@ static const struct ice_crosststamp_cfg ice_crosststamp_cfg_e830 = {\n \t.lock_busy = E830_PFPTM_SEM_BUSY_M,\n \t.ctl_reg = E830_GLPTM_ART_CTL,\n \t.ctl_active = E830_GLPTM_ART_CTL_ACTIVE_M,\n+\t.ctl_timeout = E830_GLPTM_ART_CTL_TIME_OUT_M,\n \t.art_time_l = E830_GLPTM_ART_TIME_L,\n \t.art_time_h = E830_GLPTM_ART_TIME_H,\n \t.dev_time_l[0] = E830_GLTSYN_PTMTIME_L(0),\n@@ -2123,9 +2127,13 @@ static int ice_capture_crosststamp(ktime_t *device,\n \tctl |= cfg->ctl_active;\n \twr32(hw, cfg->ctl_reg, ctl);\n \n-\t/* Poll until hardware completes the capture */\n-\terr = rd32_poll_timeout(hw, cfg->ctl_reg, ctl, !(ctl & cfg->ctl_active),\n+\t/* Poll until hardware completes the capture or timeout occurs */\n+\terr = rd32_poll_timeout(hw, cfg->ctl_reg, ctl,\n+\t\t\t\t!(ctl & cfg->ctl_active) ||\n+\t\t\t\t(ctl & cfg->ctl_timeout),\n \t\t\t\t5, 20 * USEC_PER_MSEC);\n+\tif (ctl & cfg->ctl_timeout)\n+\t\terr = -ETIMEDOUT;\n \tif (err)\n \t\tgoto err_timeout;\n \n", "prefixes": [ "iwl-next" ] }