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GET /api/patches/2216758/?format=api
{ "id": 2216758, "url": "http://patchwork.ozlabs.org/api/patches/2216758/?format=api", "web_url": "http://patchwork.ozlabs.org/project/sparclinux/patch/20260327061704.3707577-17-hch@lst.de/", "project": { "id": 10, "url": "http://patchwork.ozlabs.org/api/projects/10/?format=api", "name": "Linux SPARC Development ", "link_name": "sparclinux", "list_id": "sparclinux.vger.kernel.org", "list_email": "sparclinux@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327061704.3707577-17-hch@lst.de>", "list_archive_url": null, "date": "2026-03-27T06:16:48", "name": "[16/28] riscv: move the XOR code to lib/raid/", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b26a8d13ca8e4983ab59bcf5498f9981211c0258", "submitter": { "id": 82, "url": "http://patchwork.ozlabs.org/api/people/82/?format=api", "name": "Christoph Hellwig", "email": "hch@lst.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/sparclinux/patch/20260327061704.3707577-17-hch@lst.de/mbox/", "series": [ { "id": 497694, "url": "http://patchwork.ozlabs.org/api/series/497694/?format=api", "web_url": "http://patchwork.ozlabs.org/project/sparclinux/list/?series=497694", "date": "2026-03-27T06:16:33", "name": "[01/28] xor: assert that xor_blocks is not call from interrupt context", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497694/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216758/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216758/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <SRS0=2v1p=B3=vger.kernel.org=sparclinux+bounces-6591-patchwork-incoming=ozlabs.org@ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "sparclinux@vger.kernel.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "patchwork-incoming@ozlabs.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256\n header.s=bombadil.20210309 header.b=aed6jKJc;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=ozlabs.org\n (client-ip=2404:9400:2221:ea00::3; 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arc=none smtp.client-ip=198.137.202.133" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding:\n\tMIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender\n\t:Reply-To:Content-Type:Content-ID:Content-Description;\n\tbh=07vOovAtUwNz4Cgfu6Afqnyvj7rNswjLnNiipxDT/U4=; b=aed6jKJcLCu5fJRdTzJeZY25hh\n\tXpWddSPrI15qej790N97vFD3kOvT4ej/lzCKLysqzsiCN3plXuP+Jp1wmp6DQwcK1jDP0HkNH2vcv\n\ttSAKjp/Fqhg6/FVNn47O+YCuQVRYFSDh7Bmt2eOdQIH1b4bA2Iwn/dxj0Vqg1b8j8fBp4yYOWLSE0\n\t0cb150u28VLIBD7reCDQzvgwo59zo2eRXofTfTH2MOr67IMiyi9pS7BHEzkL9CvauXyUtnnY+Maz4\n\trHjo58GaHJReTsDmH6a+tmSdxxSXvjJUwoEwc+xjS8qixXQBq2TStfg3xC3LeNyqWTU4Wlt5eVzBD\n\tnJ/M8cog==;", "From": "Christoph Hellwig <hch@lst.de>", "To": "Andrew Morton <akpm@linux-foundation.org>", "Cc": "Richard Henderson <richard.henderson@linaro.org>,\n\tMatt Turner <mattst88@gmail.com>,\n\tMagnus Lindholm <linmag7@gmail.com>,\n\tRussell King <linux@armlinux.org.uk>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will@kernel.org>,\n\tArd Biesheuvel <ardb@kernel.org>,\n\tHuacai Chen <chenhuacai@kernel.org>,\n\tWANG Xuerui <kernel@xen0n.name>,\n\tMadhavan Srinivasan <maddy@linux.ibm.com>,\n\tMichael Ellerman <mpe@ellerman.id.au>,\n\tNicholas Piggin <npiggin@gmail.com>,\n\t\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>,\n\tPaul Walmsley <pjw@kernel.org>,\n\tPalmer Dabbelt <palmer@dabbelt.com>,\n\tAlbert Ou <aou@eecs.berkeley.edu>,\n\tAlexandre Ghiti <alex@ghiti.fr>,\n\tHeiko Carstens <hca@linux.ibm.com>,\n\tVasily Gorbik <gor@linux.ibm.com>,\n\tAlexander Gordeev <agordeev@linux.ibm.com>,\n\tChristian Borntraeger <borntraeger@linux.ibm.com>,\n\tSven Schnelle <svens@linux.ibm.com>,\n\t\"David S. Miller\" <davem@davemloft.net>,\n\tAndreas Larsson <andreas@gaisler.com>,\n\tRichard Weinberger <richard@nod.at>,\n\tAnton Ivanov <anton.ivanov@cambridgegreys.com>,\n\tJohannes Berg <johannes@sipsolutions.net>,\n\tThomas Gleixner <tglx@kernel.org>,\n\tIngo Molnar <mingo@redhat.com>,\n\tBorislav Petkov <bp@alien8.de>,\n\tDave Hansen <dave.hansen@linux.intel.com>,\n\tx86@kernel.org,\n\t\"H. Peter Anvin\" <hpa@zytor.com>,\n\tHerbert Xu <herbert@gondor.apana.org.au>,\n\tDan Williams <dan.j.williams@intel.com>,\n\tChris Mason <clm@fb.com>,\n\tDavid Sterba <dsterba@suse.com>,\n\tArnd Bergmann <arnd@arndb.de>,\n\tSong Liu <song@kernel.org>,\n\tYu Kuai <yukuai@fnnas.com>,\n\tLi Nan <linan122@huawei.com>,\n\t\"Theodore Ts'o\" <tytso@mit.edu>,\n\t\"Jason A. Donenfeld\" <Jason@zx2c4.com>,\n\tlinux-alpha@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tloongarch@lists.linux.dev,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-riscv@lists.infradead.org,\n\tlinux-s390@vger.kernel.org,\n\tsparclinux@vger.kernel.org,\n\tlinux-um@lists.infradead.org,\n\tlinux-crypto@vger.kernel.org,\n\tlinux-btrfs@vger.kernel.org,\n\tlinux-arch@vger.kernel.org,\n\tlinux-raid@vger.kernel.org", "Subject": "[PATCH 16/28] riscv: move the XOR code to lib/raid/", "Date": "Fri, 27 Mar 2026 07:16:48 +0100", "Message-ID": "<20260327061704.3707577-17-hch@lst.de>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260327061704.3707577-1-hch@lst.de>", "References": "<20260327061704.3707577-1-hch@lst.de>", "Precedence": "bulk", "X-Mailing-List": "sparclinux@vger.kernel.org", "List-Id": "<sparclinux.vger.kernel.org>", "List-Subscribe": "<mailto:sparclinux+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:sparclinux+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-SRS-Rewrite": "SMTP reverse-path rewritten from <hch@infradead.org> by\n bombadil.infradead.org. See http://www.infradead.org/rpr.html", "X-Spam-Status": "No, score=-0.2 required=5.0 tests=ARC_SIGNED,ARC_VALID,\n\tDKIM_SIGNED,DKIM_VALID,DMARC_NONE,HEADER_FROM_DIFFERENT_DOMAINS,\n\tMAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=disabled\n\tversion=4.0.1", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on gandalf.ozlabs.org" }, "content": "Move the optimized XOR into lib/raid and include it it in xor.ko\ninstead of always building it into the main kernel image.\n\nSigned-off-by: Christoph Hellwig <hch@lst.de>\n---\n arch/riscv/include/asm/xor.h | 54 +------------------\n arch/riscv/lib/Makefile | 1 -\n lib/raid/xor/Makefile | 1 +\n lib/raid/xor/riscv/xor-glue.c | 56 ++++++++++++++++++++\n {arch/riscv/lib => lib/raid/xor/riscv}/xor.S | 4 --\n 5 files changed, 59 insertions(+), 57 deletions(-)\n create mode 100644 lib/raid/xor/riscv/xor-glue.c\n rename {arch/riscv/lib => lib/raid/xor/riscv}/xor.S (92%)", "diff": "diff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h\nindex ed5f27903efc..614d9209d078 100644\n--- a/arch/riscv/include/asm/xor.h\n+++ b/arch/riscv/include/asm/xor.h\n@@ -2,60 +2,10 @@\n /*\n * Copyright (C) 2021 SiFive\n */\n-\n-#include <linux/hardirq.h>\n-#include <asm-generic/xor.h>\n-#ifdef CONFIG_RISCV_ISA_V\n #include <asm/vector.h>\n-#include <asm/switch_to.h>\n-#include <asm/asm-prototypes.h>\n-\n-static void xor_vector_2(unsigned long bytes, unsigned long *__restrict p1,\n-\t\t\t const unsigned long *__restrict p2)\n-{\n-\tkernel_vector_begin();\n-\txor_regs_2_(bytes, p1, p2);\n-\tkernel_vector_end();\n-}\n-\n-static void xor_vector_3(unsigned long bytes, unsigned long *__restrict p1,\n-\t\t\t const unsigned long *__restrict p2,\n-\t\t\t const unsigned long *__restrict p3)\n-{\n-\tkernel_vector_begin();\n-\txor_regs_3_(bytes, p1, p2, p3);\n-\tkernel_vector_end();\n-}\n-\n-static void xor_vector_4(unsigned long bytes, unsigned long *__restrict p1,\n-\t\t\t const unsigned long *__restrict p2,\n-\t\t\t const unsigned long *__restrict p3,\n-\t\t\t const unsigned long *__restrict p4)\n-{\n-\tkernel_vector_begin();\n-\txor_regs_4_(bytes, p1, p2, p3, p4);\n-\tkernel_vector_end();\n-}\n-\n-static void xor_vector_5(unsigned long bytes, unsigned long *__restrict p1,\n-\t\t\t const unsigned long *__restrict p2,\n-\t\t\t const unsigned long *__restrict p3,\n-\t\t\t const unsigned long *__restrict p4,\n-\t\t\t const unsigned long *__restrict p5)\n-{\n-\tkernel_vector_begin();\n-\txor_regs_5_(bytes, p1, p2, p3, p4, p5);\n-\tkernel_vector_end();\n-}\n+#include <asm-generic/xor.h>\n \n-static struct xor_block_template xor_block_rvv = {\n-\t.name = \"rvv\",\n-\t.do_2 = xor_vector_2,\n-\t.do_3 = xor_vector_3,\n-\t.do_4 = xor_vector_4,\n-\t.do_5 = xor_vector_5\n-};\n-#endif /* CONFIG_RISCV_ISA_V */\n+extern struct xor_block_template xor_block_rvv;\n \n #define arch_xor_init arch_xor_init\n static __always_inline void __init arch_xor_init(void)\ndiff --git a/arch/riscv/lib/Makefile b/arch/riscv/lib/Makefile\nindex bbc031124974..e220c35764eb 100644\n--- a/arch/riscv/lib/Makefile\n+++ b/arch/riscv/lib/Makefile\n@@ -16,5 +16,4 @@ lib-$(CONFIG_MMU)\t+= uaccess.o\n lib-$(CONFIG_64BIT)\t+= tishift.o\n lib-$(CONFIG_RISCV_ISA_ZICBOZ)\t+= clear_page.o\n obj-$(CONFIG_FUNCTION_ERROR_INJECTION) += error-inject.o\n-lib-$(CONFIG_RISCV_ISA_V)\t+= xor.o\n lib-$(CONFIG_RISCV_ISA_V)\t+= riscv_v_helpers.o\ndiff --git a/lib/raid/xor/Makefile b/lib/raid/xor/Makefile\nindex 006b44ce46bf..9e729b50e775 100644\n--- a/lib/raid/xor/Makefile\n+++ b/lib/raid/xor/Makefile\n@@ -17,6 +17,7 @@ xor-$(CONFIG_ARM64)\t\t+= arm64/xor-neon.o arm64/xor-neon-glue.o\n xor-$(CONFIG_CPU_HAS_LSX)\t+= loongarch/xor_simd.o\n xor-$(CONFIG_CPU_HAS_LSX)\t+= loongarch/xor_simd_glue.o\n xor-$(CONFIG_ALTIVEC)\t\t+= powerpc/xor_vmx.o powerpc/xor_vmx_glue.o\n+xor-$(CONFIG_RISCV_ISA_V)\t+= riscv/xor.o riscv/xor-glue.o\n \n \n CFLAGS_arm/xor-neon.o\t\t+= $(CC_FLAGS_FPU)\ndiff --git a/lib/raid/xor/riscv/xor-glue.c b/lib/raid/xor/riscv/xor-glue.c\nnew file mode 100644\nindex 000000000000..11666a4b6b68\n--- /dev/null\n+++ b/lib/raid/xor/riscv/xor-glue.c\n@@ -0,0 +1,56 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (C) 2021 SiFive\n+ */\n+\n+#include <linux/raid/xor_impl.h>\n+#include <asm/vector.h>\n+#include <asm/switch_to.h>\n+#include <asm/asm-prototypes.h>\n+#include <asm/xor.h>\n+\n+static void xor_vector_2(unsigned long bytes, unsigned long *__restrict p1,\n+\t\t\t const unsigned long *__restrict p2)\n+{\n+\tkernel_vector_begin();\n+\txor_regs_2_(bytes, p1, p2);\n+\tkernel_vector_end();\n+}\n+\n+static void xor_vector_3(unsigned long bytes, unsigned long *__restrict p1,\n+\t\t\t const unsigned long *__restrict p2,\n+\t\t\t const unsigned long *__restrict p3)\n+{\n+\tkernel_vector_begin();\n+\txor_regs_3_(bytes, p1, p2, p3);\n+\tkernel_vector_end();\n+}\n+\n+static void xor_vector_4(unsigned long bytes, unsigned long *__restrict p1,\n+\t\t\t const unsigned long *__restrict p2,\n+\t\t\t const unsigned long *__restrict p3,\n+\t\t\t const unsigned long *__restrict p4)\n+{\n+\tkernel_vector_begin();\n+\txor_regs_4_(bytes, p1, p2, p3, p4);\n+\tkernel_vector_end();\n+}\n+\n+static void xor_vector_5(unsigned long bytes, unsigned long *__restrict p1,\n+\t\t\t const unsigned long *__restrict p2,\n+\t\t\t const unsigned long *__restrict p3,\n+\t\t\t const unsigned long *__restrict p4,\n+\t\t\t const unsigned long *__restrict p5)\n+{\n+\tkernel_vector_begin();\n+\txor_regs_5_(bytes, p1, p2, p3, p4, p5);\n+\tkernel_vector_end();\n+}\n+\n+struct xor_block_template xor_block_rvv = {\n+\t.name = \"rvv\",\n+\t.do_2 = xor_vector_2,\n+\t.do_3 = xor_vector_3,\n+\t.do_4 = xor_vector_4,\n+\t.do_5 = xor_vector_5\n+};\ndiff --git a/arch/riscv/lib/xor.S b/lib/raid/xor/riscv/xor.S\nsimilarity index 92%\nrename from arch/riscv/lib/xor.S\nrename to lib/raid/xor/riscv/xor.S\nindex b28f2430e52f..56fb7fc1e2cd 100644\n--- a/arch/riscv/lib/xor.S\n+++ b/lib/raid/xor/riscv/xor.S\n@@ -18,7 +18,6 @@ SYM_FUNC_START(xor_regs_2_)\n \tbnez a0, xor_regs_2_\n \tret\n SYM_FUNC_END(xor_regs_2_)\n-EXPORT_SYMBOL(xor_regs_2_)\n \n SYM_FUNC_START(xor_regs_3_)\n \tvsetvli a4, a0, e8, m8, ta, ma\n@@ -35,7 +34,6 @@ SYM_FUNC_START(xor_regs_3_)\n \tbnez a0, xor_regs_3_\n \tret\n SYM_FUNC_END(xor_regs_3_)\n-EXPORT_SYMBOL(xor_regs_3_)\n \n SYM_FUNC_START(xor_regs_4_)\n \tvsetvli a5, a0, e8, m8, ta, ma\n@@ -55,7 +53,6 @@ SYM_FUNC_START(xor_regs_4_)\n \tbnez a0, xor_regs_4_\n \tret\n SYM_FUNC_END(xor_regs_4_)\n-EXPORT_SYMBOL(xor_regs_4_)\n \n SYM_FUNC_START(xor_regs_5_)\n \tvsetvli a6, a0, e8, m8, ta, ma\n@@ -78,4 +75,3 @@ SYM_FUNC_START(xor_regs_5_)\n \tbnez a0, xor_regs_5_\n \tret\n SYM_FUNC_END(xor_regs_5_)\n-EXPORT_SYMBOL(xor_regs_5_)\n", "prefixes": [ "16/28" ] }