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GET /api/patches/2216720/?format=api
{ "id": 2216720, "url": "http://patchwork.ozlabs.org/api/patches/2216720/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260327061704.3707577-16-hch@lst.de/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20260327061704.3707577-16-hch@lst.de>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20260327061704.3707577-16-hch@lst.de/", "date": "2026-03-27T06:16:47", "name": "[15/28] powerpc: move the XOR code to lib/raid/", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "b61516c4e9422a2ff1b60df6d0a434a852b0579a", "submitter": { "id": 82, "url": "http://patchwork.ozlabs.org/api/people/82/?format=api", "name": "Christoph Hellwig", "email": "hch@lst.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260327061704.3707577-16-hch@lst.de/mbox/", "series": [ { "id": 497693, "url": "http://patchwork.ozlabs.org/api/series/497693/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=497693", "date": "2026-03-27T06:16:33", "name": "[01/28] xor: assert that xor_blocks is not call from interrupt context", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497693/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216720/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216720/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev+bounces-18885-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256\n header.s=bombadil.20210309 header.b=JS2Fu46O;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=112.213.38.117; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding:\n\tMIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender\n\t:Reply-To:Content-Type:Content-ID:Content-Description;\n\tbh=VU1JeGqI6k2uvXecj1efLpuQZv7vmGIDPw6I2na0LZU=; b=JS2Fu46O1tnrljzebI8oIVG7HC\n\twEeWlxq684ElYXvTTNbX61KKoSygqlE+wmDYJHfyib36ewfzBMnlxNeRCPAosQMiE6jNPIDVFaM04\n\tFHiT5qnjp6YLfJsXEBaVbxQt2iMrRco2qemTa6QX9xJ9hGOracLbWLR1A12ukaHH+rph1FAIeqGbA\n\tA1i5ZoowqSt3bC9xxv49DWQgajcb8SWk7sIFxLRPOG1d+t0CF7FxLcHLgRzSdwB4MoZnqvRXO7Ix/\n\tJV06AGQN4g1REQ7FmYLZK0bvuwjWfnV2+AL3MjujKhVmwDHwzLPs1vKEMMGQnSwNcdSQo5JkNm+qE\n\tibKvBXyw==;", "From": "Christoph Hellwig <hch@lst.de>", "To": "Andrew Morton <akpm@linux-foundation.org>", "Cc": "Richard Henderson <richard.henderson@linaro.org>,\n\tMatt Turner <mattst88@gmail.com>,\n\tMagnus Lindholm <linmag7@gmail.com>,\n\tRussell King <linux@armlinux.org.uk>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will@kernel.org>,\n\tArd Biesheuvel <ardb@kernel.org>,\n\tHuacai Chen <chenhuacai@kernel.org>,\n\tWANG Xuerui <kernel@xen0n.name>,\n\tMadhavan Srinivasan <maddy@linux.ibm.com>,\n\tMichael Ellerman <mpe@ellerman.id.au>,\n\tNicholas Piggin <npiggin@gmail.com>,\n\t\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>,\n\tPaul Walmsley <pjw@kernel.org>,\n\tPalmer Dabbelt <palmer@dabbelt.com>,\n\tAlbert Ou <aou@eecs.berkeley.edu>,\n\tAlexandre Ghiti <alex@ghiti.fr>,\n\tHeiko Carstens <hca@linux.ibm.com>,\n\tVasily Gorbik <gor@linux.ibm.com>,\n\tAlexander Gordeev <agordeev@linux.ibm.com>,\n\tChristian Borntraeger <borntraeger@linux.ibm.com>,\n\tSven Schnelle <svens@linux.ibm.com>,\n\t\"David S. Miller\" <davem@davemloft.net>,\n\tAndreas Larsson <andreas@gaisler.com>,\n\tRichard Weinberger <richard@nod.at>,\n\tAnton Ivanov <anton.ivanov@cambridgegreys.com>,\n\tJohannes Berg <johannes@sipsolutions.net>,\n\tThomas Gleixner <tglx@kernel.org>,\n\tIngo Molnar <mingo@redhat.com>,\n\tBorislav Petkov <bp@alien8.de>,\n\tDave Hansen <dave.hansen@linux.intel.com>,\n\tx86@kernel.org,\n\t\"H. Peter Anvin\" <hpa@zytor.com>,\n\tHerbert Xu <herbert@gondor.apana.org.au>,\n\tDan Williams <dan.j.williams@intel.com>,\n\tChris Mason <clm@fb.com>,\n\tDavid Sterba <dsterba@suse.com>,\n\tArnd Bergmann <arnd@arndb.de>,\n\tSong Liu <song@kernel.org>,\n\tYu Kuai <yukuai@fnnas.com>,\n\tLi Nan <linan122@huawei.com>,\n\t\"Theodore Ts'o\" <tytso@mit.edu>,\n\t\"Jason A. Donenfeld\" <Jason@zx2c4.com>,\n\tlinux-alpha@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tloongarch@lists.linux.dev,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-riscv@lists.infradead.org,\n\tlinux-s390@vger.kernel.org,\n\tsparclinux@vger.kernel.org,\n\tlinux-um@lists.infradead.org,\n\tlinux-crypto@vger.kernel.org,\n\tlinux-btrfs@vger.kernel.org,\n\tlinux-arch@vger.kernel.org,\n\tlinux-raid@vger.kernel.org", "Subject": "[PATCH 15/28] powerpc: move the XOR code to lib/raid/", "Date": "Fri, 27 Mar 2026 07:16:47 +0100", "Message-ID": "<20260327061704.3707577-16-hch@lst.de>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260327061704.3707577-1-hch@lst.de>", "References": "<20260327061704.3707577-1-hch@lst.de>", "X-Mailing-List": "linuxppc-dev@lists.ozlabs.org", "List-Id": "<linuxppc-dev.lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev+help@lists.ozlabs.org>", "List-Owner": "<mailto:linuxppc-dev+owner@lists.ozlabs.org>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linuxppc-dev/>,\n <https://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Subscribe": "<mailto:linuxppc-dev+subscribe@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-digest@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linuxppc-dev+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-SRS-Rewrite": "SMTP reverse-path rewritten from <hch@infradead.org> by\n bombadil.infradead.org. See http://www.infradead.org/rpr.html", "X-Spam-Status": "No, score=0.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID,\n\tHEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE,SPF_NONE\n\tautolearn=disabled version=4.0.1 OzLabs 8", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "Move the optimized XOR into lib/raid and include it it in xor.ko\ninstead of always building it into the main kernel image.\n\nSigned-off-by: Christoph Hellwig <hch@lst.de>\n---\n arch/powerpc/include/asm/xor.h | 17 +----\n arch/powerpc/include/asm/xor_altivec.h | 22 ------\n arch/powerpc/lib/Makefile | 5 --\n arch/powerpc/lib/xor_vmx_glue.c | 63 -----------------\n lib/raid/xor/Makefile | 5 ++\n .../lib => lib/raid/xor/powerpc}/xor_vmx.c | 0\n .../lib => lib/raid/xor/powerpc}/xor_vmx.h | 0\n lib/raid/xor/powerpc/xor_vmx_glue.c | 67 +++++++++++++++++++\n 8 files changed, 74 insertions(+), 105 deletions(-)\n delete mode 100644 arch/powerpc/include/asm/xor_altivec.h\n delete mode 100644 arch/powerpc/lib/xor_vmx_glue.c\n rename {arch/powerpc/lib => lib/raid/xor/powerpc}/xor_vmx.c (100%)\n rename {arch/powerpc/lib => lib/raid/xor/powerpc}/xor_vmx.h (100%)\n create mode 100644 lib/raid/xor/powerpc/xor_vmx_glue.c", "diff": "diff --git a/arch/powerpc/include/asm/xor.h b/arch/powerpc/include/asm/xor.h\nindex 30224c5279c4..3293ac87181c 100644\n--- a/arch/powerpc/include/asm/xor.h\n+++ b/arch/powerpc/include/asm/xor.h\n@@ -8,24 +8,11 @@\n #ifndef _ASM_POWERPC_XOR_H\n #define _ASM_POWERPC_XOR_H\n \n-#ifdef CONFIG_ALTIVEC\n-\n-#include <asm/cputable.h>\n #include <asm/cpu_has_feature.h>\n-#include <asm/xor_altivec.h>\n-\n-static struct xor_block_template xor_block_altivec = {\n-\t.name = \"altivec\",\n-\t.do_2 = xor_altivec_2,\n-\t.do_3 = xor_altivec_3,\n-\t.do_4 = xor_altivec_4,\n-\t.do_5 = xor_altivec_5,\n-};\n-#endif /* CONFIG_ALTIVEC */\n-\n-/* Also try the generic routines. */\n #include <asm-generic/xor.h>\n \n+extern struct xor_block_template xor_block_altivec;\n+\n #define arch_xor_init arch_xor_init\n static __always_inline void __init arch_xor_init(void)\n {\ndiff --git a/arch/powerpc/include/asm/xor_altivec.h b/arch/powerpc/include/asm/xor_altivec.h\ndeleted file mode 100644\nindex 294620a25f80..000000000000\n--- a/arch/powerpc/include/asm/xor_altivec.h\n+++ /dev/null\n@@ -1,22 +0,0 @@\n-/* SPDX-License-Identifier: GPL-2.0 */\n-#ifndef _ASM_POWERPC_XOR_ALTIVEC_H\n-#define _ASM_POWERPC_XOR_ALTIVEC_H\n-\n-#ifdef CONFIG_ALTIVEC\n-void xor_altivec_2(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2);\n-void xor_altivec_3(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2,\n-\t\t const unsigned long * __restrict p3);\n-void xor_altivec_4(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2,\n-\t\t const unsigned long * __restrict p3,\n-\t\t const unsigned long * __restrict p4);\n-void xor_altivec_5(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2,\n-\t\t const unsigned long * __restrict p3,\n-\t\t const unsigned long * __restrict p4,\n-\t\t const unsigned long * __restrict p5);\n-\n-#endif\n-#endif /* _ASM_POWERPC_XOR_ALTIVEC_H */\ndiff --git a/arch/powerpc/lib/Makefile b/arch/powerpc/lib/Makefile\nindex f14ecab674a3..002edc3f01d5 100644\n--- a/arch/powerpc/lib/Makefile\n+++ b/arch/powerpc/lib/Makefile\n@@ -73,9 +73,4 @@ obj-$(CONFIG_PPC_LIB_RHEAP) += rheap.o\n \n obj-$(CONFIG_FTR_FIXUP_SELFTEST) += feature-fixups-test.o\n \n-obj-$(CONFIG_ALTIVEC)\t+= xor_vmx.o xor_vmx_glue.o\n-CFLAGS_xor_vmx.o += -mhard-float -maltivec $(call cc-option,-mabi=altivec)\n-# Enable <altivec.h>\n-CFLAGS_xor_vmx.o += -isystem $(shell $(CC) -print-file-name=include)\n-\n obj-$(CONFIG_PPC64) += $(obj64-y)\ndiff --git a/arch/powerpc/lib/xor_vmx_glue.c b/arch/powerpc/lib/xor_vmx_glue.c\ndeleted file mode 100644\nindex 35d917ece4d1..000000000000\n--- a/arch/powerpc/lib/xor_vmx_glue.c\n+++ /dev/null\n@@ -1,63 +0,0 @@\n-// SPDX-License-Identifier: GPL-2.0-or-later\n-/*\n- * Altivec XOR operations\n- *\n- * Copyright 2017 IBM Corp.\n- */\n-\n-#include <linux/preempt.h>\n-#include <linux/export.h>\n-#include <linux/sched.h>\n-#include <asm/switch_to.h>\n-#include <asm/xor_altivec.h>\n-#include \"xor_vmx.h\"\n-\n-void xor_altivec_2(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2)\n-{\n-\tpreempt_disable();\n-\tenable_kernel_altivec();\n-\t__xor_altivec_2(bytes, p1, p2);\n-\tdisable_kernel_altivec();\n-\tpreempt_enable();\n-}\n-EXPORT_SYMBOL(xor_altivec_2);\n-\n-void xor_altivec_3(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2,\n-\t\t const unsigned long * __restrict p3)\n-{\n-\tpreempt_disable();\n-\tenable_kernel_altivec();\n-\t__xor_altivec_3(bytes, p1, p2, p3);\n-\tdisable_kernel_altivec();\n-\tpreempt_enable();\n-}\n-EXPORT_SYMBOL(xor_altivec_3);\n-\n-void xor_altivec_4(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2,\n-\t\t const unsigned long * __restrict p3,\n-\t\t const unsigned long * __restrict p4)\n-{\n-\tpreempt_disable();\n-\tenable_kernel_altivec();\n-\t__xor_altivec_4(bytes, p1, p2, p3, p4);\n-\tdisable_kernel_altivec();\n-\tpreempt_enable();\n-}\n-EXPORT_SYMBOL(xor_altivec_4);\n-\n-void xor_altivec_5(unsigned long bytes, unsigned long * __restrict p1,\n-\t\t const unsigned long * __restrict p2,\n-\t\t const unsigned long * __restrict p3,\n-\t\t const unsigned long * __restrict p4,\n-\t\t const unsigned long * __restrict p5)\n-{\n-\tpreempt_disable();\n-\tenable_kernel_altivec();\n-\t__xor_altivec_5(bytes, p1, p2, p3, p4, p5);\n-\tdisable_kernel_altivec();\n-\tpreempt_enable();\n-}\n-EXPORT_SYMBOL(xor_altivec_5);\ndiff --git a/lib/raid/xor/Makefile b/lib/raid/xor/Makefile\nindex e8868f5fc396..006b44ce46bf 100644\n--- a/lib/raid/xor/Makefile\n+++ b/lib/raid/xor/Makefile\n@@ -16,6 +16,7 @@ endif\n xor-$(CONFIG_ARM64)\t\t+= arm64/xor-neon.o arm64/xor-neon-glue.o\n xor-$(CONFIG_CPU_HAS_LSX)\t+= loongarch/xor_simd.o\n xor-$(CONFIG_CPU_HAS_LSX)\t+= loongarch/xor_simd_glue.o\n+xor-$(CONFIG_ALTIVEC)\t\t+= powerpc/xor_vmx.o powerpc/xor_vmx_glue.o\n \n \n CFLAGS_arm/xor-neon.o\t\t+= $(CC_FLAGS_FPU)\n@@ -23,3 +24,7 @@ CFLAGS_REMOVE_arm/xor-neon.o\t+= $(CC_FLAGS_NO_FPU)\n \n CFLAGS_arm64/xor-neon.o\t\t+= $(CC_FLAGS_FPU)\n CFLAGS_REMOVE_arm64/xor-neon.o\t+= $(CC_FLAGS_NO_FPU)\n+\n+CFLAGS_powerpc/xor_vmx.o\t+= -mhard-float -maltivec \\\n+\t\t\t\t $(call cc-option,-mabi=altivec) \\\n+\t\t\t\t -isystem $(shell $(CC) -print-file-name=include)\ndiff --git a/arch/powerpc/lib/xor_vmx.c b/lib/raid/xor/powerpc/xor_vmx.c\nsimilarity index 100%\nrename from arch/powerpc/lib/xor_vmx.c\nrename to lib/raid/xor/powerpc/xor_vmx.c\ndiff --git a/arch/powerpc/lib/xor_vmx.h b/lib/raid/xor/powerpc/xor_vmx.h\nsimilarity index 100%\nrename from arch/powerpc/lib/xor_vmx.h\nrename to lib/raid/xor/powerpc/xor_vmx.h\ndiff --git a/lib/raid/xor/powerpc/xor_vmx_glue.c b/lib/raid/xor/powerpc/xor_vmx_glue.c\nnew file mode 100644\nindex 000000000000..c41e38340700\n--- /dev/null\n+++ b/lib/raid/xor/powerpc/xor_vmx_glue.c\n@@ -0,0 +1,67 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Altivec XOR operations\n+ *\n+ * Copyright 2017 IBM Corp.\n+ */\n+\n+#include <linux/preempt.h>\n+#include <linux/sched.h>\n+#include <linux/raid/xor_impl.h>\n+#include <asm/switch_to.h>\n+#include <asm/xor.h>\n+#include \"xor_vmx.h\"\n+\n+static void xor_altivec_2(unsigned long bytes, unsigned long * __restrict p1,\n+\t\tconst unsigned long * __restrict p2)\n+{\n+\tpreempt_disable();\n+\tenable_kernel_altivec();\n+\t__xor_altivec_2(bytes, p1, p2);\n+\tdisable_kernel_altivec();\n+\tpreempt_enable();\n+}\n+\n+static void xor_altivec_3(unsigned long bytes, unsigned long * __restrict p1,\n+\t\tconst unsigned long * __restrict p2,\n+\t\tconst unsigned long * __restrict p3)\n+{\n+\tpreempt_disable();\n+\tenable_kernel_altivec();\n+\t__xor_altivec_3(bytes, p1, p2, p3);\n+\tdisable_kernel_altivec();\n+\tpreempt_enable();\n+}\n+\n+static void xor_altivec_4(unsigned long bytes, unsigned long * __restrict p1,\n+\t\tconst unsigned long * __restrict p2,\n+\t\tconst unsigned long * __restrict p3,\n+\t\tconst unsigned long * __restrict p4)\n+{\n+\tpreempt_disable();\n+\tenable_kernel_altivec();\n+\t__xor_altivec_4(bytes, p1, p2, p3, p4);\n+\tdisable_kernel_altivec();\n+\tpreempt_enable();\n+}\n+\n+static void xor_altivec_5(unsigned long bytes, unsigned long * __restrict p1,\n+\t\tconst unsigned long * __restrict p2,\n+\t\tconst unsigned long * __restrict p3,\n+\t\tconst unsigned long * __restrict p4,\n+\t\tconst unsigned long * __restrict p5)\n+{\n+\tpreempt_disable();\n+\tenable_kernel_altivec();\n+\t__xor_altivec_5(bytes, p1, p2, p3, p4, p5);\n+\tdisable_kernel_altivec();\n+\tpreempt_enable();\n+}\n+\n+struct xor_block_template xor_block_altivec = {\n+\t.name = \"altivec\",\n+\t.do_2 = xor_altivec_2,\n+\t.do_3 = xor_altivec_3,\n+\t.do_4 = xor_altivec_4,\n+\t.do_5 = xor_altivec_5,\n+};\n", "prefixes": [ "15/28" ] }