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GET /api/patches/2216707/?format=api
{ "id": 2216707, "url": "http://patchwork.ozlabs.org/api/patches/2216707/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260327061704.3707577-10-hch@lst.de/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<20260327061704.3707577-10-hch@lst.de>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/20260327061704.3707577-10-hch@lst.de/", "date": "2026-03-27T06:16:41", "name": "[09/28] xor: remove macro abuse for XOR implementation registrations", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "b44039eb4e03905be854d354708f10922ee25fe8", "submitter": { "id": 82, "url": "http://patchwork.ozlabs.org/api/people/82/?format=api", "name": "Christoph Hellwig", "email": "hch@lst.de" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/20260327061704.3707577-10-hch@lst.de/mbox/", "series": [ { "id": 497693, "url": "http://patchwork.ozlabs.org/api/series/497693/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/list/?series=497693", "date": "2026-03-27T06:16:33", "name": "[01/28] xor: assert that xor_blocks is not call from interrupt context", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497693/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216707/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216707/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linuxppc-dev+bounces-18879-incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=infradead.org header.i=@infradead.org header.a=rsa-sha256\n header.s=bombadil.20210309 header.b=AobrlijQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ozlabs.org\n (client-ip=2404:9400:21b9:f100::1; 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a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=infradead.org; s=bombadil.20210309; h=Content-Transfer-Encoding:\n\tMIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From:Sender\n\t:Reply-To:Content-Type:Content-ID:Content-Description;\n\tbh=16iHVwlcEuXCxr3ygbaZQxjphufSruBj8SyX5330Ihs=; b=AobrlijQ56fLAd4ilWD6+FhQtv\n\tH1p4IGpjuM3eHHxBgat8Nez/HU812HWESIKDXAt09lr7skDa9YoEIZmzD9O85Pc6MwTq/OcDRe+9R\n\tFg9lADaXTl/s76laNZJU5Tx/CX2GEzIRKniDS2CIShA0X444ota3EWURNQqWPv7gwEnC0yR54kelM\n\twCx6l8i8QutE1R3ZHDkQRAofzGotIiZkwNI4WqDrEBNrgwhE2pFRIuto1p1oeRuNePhnR5ch6WKkm\n\tKYZQxaMTMbjBWdllC1OgfdgwEEgbk/W75ze1OW0KoukKeivTlAaYMgWO9ZSPUWTHfEnS+yF7Uz6ZK\n\tRYYV6eBQ==;", "From": "Christoph Hellwig <hch@lst.de>", "To": "Andrew Morton <akpm@linux-foundation.org>", "Cc": "Richard Henderson <richard.henderson@linaro.org>,\n\tMatt Turner <mattst88@gmail.com>,\n\tMagnus Lindholm <linmag7@gmail.com>,\n\tRussell King <linux@armlinux.org.uk>,\n\tCatalin Marinas <catalin.marinas@arm.com>,\n\tWill Deacon <will@kernel.org>,\n\tArd Biesheuvel <ardb@kernel.org>,\n\tHuacai Chen <chenhuacai@kernel.org>,\n\tWANG Xuerui <kernel@xen0n.name>,\n\tMadhavan Srinivasan <maddy@linux.ibm.com>,\n\tMichael Ellerman <mpe@ellerman.id.au>,\n\tNicholas Piggin <npiggin@gmail.com>,\n\t\"Christophe Leroy (CS GROUP)\" <chleroy@kernel.org>,\n\tPaul Walmsley <pjw@kernel.org>,\n\tPalmer Dabbelt <palmer@dabbelt.com>,\n\tAlbert Ou <aou@eecs.berkeley.edu>,\n\tAlexandre Ghiti <alex@ghiti.fr>,\n\tHeiko Carstens <hca@linux.ibm.com>,\n\tVasily Gorbik <gor@linux.ibm.com>,\n\tAlexander Gordeev <agordeev@linux.ibm.com>,\n\tChristian Borntraeger <borntraeger@linux.ibm.com>,\n\tSven Schnelle <svens@linux.ibm.com>,\n\t\"David S. Miller\" <davem@davemloft.net>,\n\tAndreas Larsson <andreas@gaisler.com>,\n\tRichard Weinberger <richard@nod.at>,\n\tAnton Ivanov <anton.ivanov@cambridgegreys.com>,\n\tJohannes Berg <johannes@sipsolutions.net>,\n\tThomas Gleixner <tglx@kernel.org>,\n\tIngo Molnar <mingo@redhat.com>,\n\tBorislav Petkov <bp@alien8.de>,\n\tDave Hansen <dave.hansen@linux.intel.com>,\n\tx86@kernel.org,\n\t\"H. Peter Anvin\" <hpa@zytor.com>,\n\tHerbert Xu <herbert@gondor.apana.org.au>,\n\tDan Williams <dan.j.williams@intel.com>,\n\tChris Mason <clm@fb.com>,\n\tDavid Sterba <dsterba@suse.com>,\n\tArnd Bergmann <arnd@arndb.de>,\n\tSong Liu <song@kernel.org>,\n\tYu Kuai <yukuai@fnnas.com>,\n\tLi Nan <linan122@huawei.com>,\n\t\"Theodore Ts'o\" <tytso@mit.edu>,\n\t\"Jason A. Donenfeld\" <Jason@zx2c4.com>,\n\tlinux-alpha@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org,\n\tloongarch@lists.linux.dev,\n\tlinuxppc-dev@lists.ozlabs.org,\n\tlinux-riscv@lists.infradead.org,\n\tlinux-s390@vger.kernel.org,\n\tsparclinux@vger.kernel.org,\n\tlinux-um@lists.infradead.org,\n\tlinux-crypto@vger.kernel.org,\n\tlinux-btrfs@vger.kernel.org,\n\tlinux-arch@vger.kernel.org,\n\tlinux-raid@vger.kernel.org", "Subject": "[PATCH 09/28] xor: remove macro abuse for XOR implementation\n registrations", "Date": "Fri, 27 Mar 2026 07:16:41 +0100", "Message-ID": "<20260327061704.3707577-10-hch@lst.de>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260327061704.3707577-1-hch@lst.de>", "References": "<20260327061704.3707577-1-hch@lst.de>", "X-Mailing-List": "linuxppc-dev@lists.ozlabs.org", "List-Id": "<linuxppc-dev.lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev+help@lists.ozlabs.org>", "List-Owner": "<mailto:linuxppc-dev+owner@lists.ozlabs.org>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Archive": "<https://lore.kernel.org/linuxppc-dev/>,\n <https://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Subscribe": "<mailto:linuxppc-dev+subscribe@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-digest@lists.ozlabs.org>,\n <mailto:linuxppc-dev+subscribe-nomail@lists.ozlabs.org>", "List-Unsubscribe": "<mailto:linuxppc-dev+unsubscribe@lists.ozlabs.org>", "Precedence": "list", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-SRS-Rewrite": "SMTP reverse-path rewritten from <hch@infradead.org> by\n bombadil.infradead.org. See http://www.infradead.org/rpr.html", "X-Spam-Status": "No, score=0.0 required=3.0 tests=DKIM_SIGNED,DKIM_VALID,\n\tHEADER_FROM_DIFFERENT_DOMAINS,SPF_HELO_NONE,SPF_NONE\n\tautolearn=disabled version=4.0.1 OzLabs 8", "X-Spam-Checker-Version": "SpamAssassin 4.0.1 (2024-03-25) on lists.ozlabs.org" }, "content": "Drop the pretty confusing historic XOR_TRY_TEMPLATES and\nXOR_SELECT_TEMPLATE, and instead let the architectures provide a\narch_xor_init that calls either xor_register to register candidates\nor xor_force to force a specific implementation.\n\nSigned-off-by: Christoph Hellwig <hch@lst.de>\n---\n arch/alpha/include/asm/xor.h | 29 ++++++++++++----------\n arch/arm/include/asm/xor.h | 25 +++++++++----------\n arch/arm64/include/asm/xor.h | 18 +++++++-------\n arch/loongarch/include/asm/xor.h | 42 ++++++++++++--------------------\n arch/powerpc/include/asm/xor.h | 31 ++++++++++-------------\n arch/riscv/include/asm/xor.h | 19 ++++++++-------\n arch/s390/include/asm/xor.h | 12 ++++-----\n arch/sparc/include/asm/xor_32.h | 14 +++++------\n arch/sparc/include/asm/xor_64.h | 31 +++++++++++------------\n arch/x86/include/asm/xor.h | 3 ---\n arch/x86/include/asm/xor_32.h | 36 ++++++++++++++-------------\n arch/x86/include/asm/xor_64.h | 18 ++++++++------\n arch/x86/include/asm/xor_avx.h | 9 -------\n include/asm-generic/xor.h | 8 ------\n include/linux/raid/xor_impl.h | 5 ++++\n lib/raid/xor/xor-core.c | 41 +++++++++++++++++++++++--------\n 16 files changed, 168 insertions(+), 173 deletions(-)", "diff": "diff --git a/arch/alpha/include/asm/xor.h b/arch/alpha/include/asm/xor.h\nindex e0de0c233ab9..4c8085711df1 100644\n--- a/arch/alpha/include/asm/xor.h\n+++ b/arch/alpha/include/asm/xor.h\n@@ -851,16 +851,19 @@ static struct xor_block_template xor_block_alpha_prefetch = {\n /* For grins, also test the generic routines. */\n #include <asm-generic/xor.h>\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\\\n-\t\txor_speed(&xor_block_8regs);\t\t\\\n-\t\txor_speed(&xor_block_32regs);\t\t\\\n-\t\txor_speed(&xor_block_alpha);\t\t\\\n-\t\txor_speed(&xor_block_alpha_prefetch);\t\\\n-\t} while (0)\n-\n-/* Force the use of alpha_prefetch if EV6, as it is significantly\n- faster in the cold cache case. */\n-#define XOR_SELECT_TEMPLATE(FASTEST) \\\n-\t(implver() == IMPLVER_EV6 ? &xor_block_alpha_prefetch : FASTEST)\n+/*\n+ * Force the use of alpha_prefetch if EV6, as it is significantly faster in the\n+ * cold cache case.\n+ */\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\tif (implver() == IMPLVER_EV6) {\n+\t\txor_force(&xor_block_alpha_prefetch);\n+\t} else {\n+\t\txor_register(&xor_block_8regs);\n+\t\txor_register(&xor_block_32regs);\n+\t\txor_register(&xor_block_alpha);\n+\t\txor_register(&xor_block_alpha_prefetch);\n+\t}\n+}\ndiff --git a/arch/arm/include/asm/xor.h b/arch/arm/include/asm/xor.h\nindex bca2a6514746..b2dcd49186e2 100644\n--- a/arch/arm/include/asm/xor.h\n+++ b/arch/arm/include/asm/xor.h\n@@ -138,15 +138,6 @@ static struct xor_block_template xor_block_arm4regs = {\n \t.do_5\t= xor_arm4regs_5,\n };\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\\\n-\tdo {\t\t\t\t\t\\\n-\t\txor_speed(&xor_block_arm4regs);\t\\\n-\t\txor_speed(&xor_block_8regs);\t\\\n-\t\txor_speed(&xor_block_32regs);\t\\\n-\t\tNEON_TEMPLATES;\t\t\t\\\n-\t} while (0)\n-\n #ifdef CONFIG_KERNEL_MODE_NEON\n \n extern struct xor_block_template const xor_block_neon_inner;\n@@ -201,8 +192,16 @@ static struct xor_block_template xor_block_neon = {\n \t.do_5\t= xor_neon_5\n };\n \n-#define NEON_TEMPLATES\t\\\n-\tdo { if (cpu_has_neon()) xor_speed(&xor_block_neon); } while (0)\n-#else\n-#define NEON_TEMPLATES\n+#endif /* CONFIG_KERNEL_MODE_NEON */\n+\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\txor_register(&xor_block_arm4regs);\n+\txor_register(&xor_block_8regs);\n+\txor_register(&xor_block_32regs);\n+#ifdef CONFIG_KERNEL_MODE_NEON\n+\tif (cpu_has_neon())\n+\t\txor_register(&xor_block_neon);\n #endif\n+}\ndiff --git a/arch/arm64/include/asm/xor.h b/arch/arm64/include/asm/xor.h\nindex bb7428d4ebc6..3cee1eb86371 100644\n--- a/arch/arm64/include/asm/xor.h\n+++ b/arch/arm64/include/asm/xor.h\n@@ -60,14 +60,14 @@ static struct xor_block_template xor_block_arm64 = {\n \t.do_4 = xor_neon_4,\n \t.do_5\t= xor_neon_5\n };\n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES \\\n-\tdo { \\\n-\t\txor_speed(&xor_block_8regs); \\\n-\t\txor_speed(&xor_block_32regs); \\\n-\t\tif (cpu_has_neon()) { \\\n-\t\t\txor_speed(&xor_block_arm64);\\\n-\t\t} \\\n-\t} while (0)\n+\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\txor_register(&xor_block_8regs);\n+\txor_register(&xor_block_32regs);\n+\tif (cpu_has_neon())\n+\t\txor_register(&xor_block_arm64);\n+}\n \n #endif /* ! CONFIG_KERNEL_MODE_NEON */\ndiff --git a/arch/loongarch/include/asm/xor.h b/arch/loongarch/include/asm/xor.h\nindex 12467fffee46..d17c0e3b047f 100644\n--- a/arch/loongarch/include/asm/xor.h\n+++ b/arch/loongarch/include/asm/xor.h\n@@ -16,14 +16,6 @@ static struct xor_block_template xor_block_lsx = {\n \t.do_4 = xor_lsx_4,\n \t.do_5 = xor_lsx_5,\n };\n-\n-#define XOR_SPEED_LSX()\t\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\\\n-\t\tif (cpu_has_lsx)\t\t\t\\\n-\t\t\txor_speed(&xor_block_lsx);\t\\\n-\t} while (0)\n-#else /* CONFIG_CPU_HAS_LSX */\n-#define XOR_SPEED_LSX()\n #endif /* CONFIG_CPU_HAS_LSX */\n \n #ifdef CONFIG_CPU_HAS_LASX\n@@ -34,14 +26,6 @@ static struct xor_block_template xor_block_lasx = {\n \t.do_4 = xor_lasx_4,\n \t.do_5 = xor_lasx_5,\n };\n-\n-#define XOR_SPEED_LASX()\t\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\t\\\n-\t\tif (cpu_has_lasx)\t\t\t\t\\\n-\t\t\txor_speed(&xor_block_lasx);\t\t\\\n-\t} while (0)\n-#else /* CONFIG_CPU_HAS_LASX */\n-#define XOR_SPEED_LASX()\n #endif /* CONFIG_CPU_HAS_LASX */\n \n /*\n@@ -54,15 +38,21 @@ static struct xor_block_template xor_block_lasx = {\n */\n #include <asm-generic/xor.h>\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\t\\\n-do {\t\t\t\t\t\t\t\\\n-\txor_speed(&xor_block_8regs);\t\t\t\\\n-\txor_speed(&xor_block_8regs_p);\t\t\t\\\n-\txor_speed(&xor_block_32regs);\t\t\t\\\n-\txor_speed(&xor_block_32regs_p);\t\t\t\\\n-\tXOR_SPEED_LSX();\t\t\t\t\\\n-\tXOR_SPEED_LASX();\t\t\t\t\\\n-} while (0)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\txor_register(&xor_block_8regs);\n+\txor_register(&xor_block_8regs_p);\n+\txor_register(&xor_block_32regs);\n+\txor_register(&xor_block_32regs_p);\n+#ifdef CONFIG_CPU_HAS_LSX\n+\tif (cpu_has_lsx)\n+\t\txor_register(&xor_block_lsx);\n+#endif\n+#ifdef CONFIG_CPU_HAS_LASX\n+\tif (cpu_has_lasx)\n+\t\txor_register(&xor_block_lasx);\n+#endif\n+}\n \n #endif /* _ASM_LOONGARCH_XOR_H */\ndiff --git a/arch/powerpc/include/asm/xor.h b/arch/powerpc/include/asm/xor.h\nindex 37d05c11d09c..30224c5279c4 100644\n--- a/arch/powerpc/include/asm/xor.h\n+++ b/arch/powerpc/include/asm/xor.h\n@@ -21,27 +21,22 @@ static struct xor_block_template xor_block_altivec = {\n \t.do_4 = xor_altivec_4,\n \t.do_5 = xor_altivec_5,\n };\n-\n-#define XOR_SPEED_ALTIVEC()\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\\\n-\t\tif (cpu_has_feature(CPU_FTR_ALTIVEC))\t\\\n-\t\t\txor_speed(&xor_block_altivec);\t\\\n-\t} while (0)\n-#else\n-#define XOR_SPEED_ALTIVEC()\n-#endif\n+#endif /* CONFIG_ALTIVEC */\n \n /* Also try the generic routines. */\n #include <asm-generic/xor.h>\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\t\\\n-do {\t\t\t\t\t\t\t\\\n-\txor_speed(&xor_block_8regs);\t\t\t\\\n-\txor_speed(&xor_block_8regs_p);\t\t\t\\\n-\txor_speed(&xor_block_32regs);\t\t\t\\\n-\txor_speed(&xor_block_32regs_p);\t\t\t\\\n-\tXOR_SPEED_ALTIVEC();\t\t\t\t\\\n-} while (0)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\txor_register(&xor_block_8regs);\n+\txor_register(&xor_block_8regs_p);\n+\txor_register(&xor_block_32regs);\n+\txor_register(&xor_block_32regs_p);\n+#ifdef CONFIG_ALTIVEC\n+\tif (cpu_has_feature(CPU_FTR_ALTIVEC))\n+\t\txor_register(&xor_block_altivec);\n+#endif\n+}\n \n #endif /* _ASM_POWERPC_XOR_H */\ndiff --git a/arch/riscv/include/asm/xor.h b/arch/riscv/include/asm/xor.h\nindex 96011861e46b..ed5f27903efc 100644\n--- a/arch/riscv/include/asm/xor.h\n+++ b/arch/riscv/include/asm/xor.h\n@@ -55,14 +55,15 @@ static struct xor_block_template xor_block_rvv = {\n \t.do_4 = xor_vector_4,\n \t.do_5 = xor_vector_5\n };\n+#endif /* CONFIG_RISCV_ISA_V */\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES \\\n-\tdo { \\\n-\t\txor_speed(&xor_block_8regs); \\\n-\t\txor_speed(&xor_block_32regs); \\\n-\t\tif (has_vector()) { \\\n-\t\t\txor_speed(&xor_block_rvv);\\\n-\t\t} \\\n-\t} while (0)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\txor_register(&xor_block_8regs);\n+\txor_register(&xor_block_32regs);\n+#ifdef CONFIG_RISCV_ISA_V\n+\tif (has_vector())\n+\t\txor_register(&xor_block_rvv);\n #endif\n+}\ndiff --git a/arch/s390/include/asm/xor.h b/arch/s390/include/asm/xor.h\nindex 857d6759b67f..4e2233f64da9 100644\n--- a/arch/s390/include/asm/xor.h\n+++ b/arch/s390/include/asm/xor.h\n@@ -10,12 +10,10 @@\n \n extern struct xor_block_template xor_block_xc;\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\t\\\n-do {\t\t\t\t\t\t\t\\\n-\txor_speed(&xor_block_xc);\t\t\t\\\n-} while (0)\n-\n-#define XOR_SELECT_TEMPLATE(FASTEST)\t(&xor_block_xc)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\txor_force(&xor_block_xc);\n+}\n \n #endif /* _ASM_S390_XOR_H */\ndiff --git a/arch/sparc/include/asm/xor_32.h b/arch/sparc/include/asm/xor_32.h\nindex 0351813cf3af..8fbf0c07ec28 100644\n--- a/arch/sparc/include/asm/xor_32.h\n+++ b/arch/sparc/include/asm/xor_32.h\n@@ -259,10 +259,10 @@ static struct xor_block_template xor_block_SPARC = {\n /* For grins, also test the generic routines. */\n #include <asm-generic/xor.h>\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\\\n-\t\txor_speed(&xor_block_8regs);\t\t\\\n-\t\txor_speed(&xor_block_32regs);\t\t\\\n-\t\txor_speed(&xor_block_SPARC);\t\t\\\n-\t} while (0)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\txor_register(&xor_block_8regs);\n+\txor_register(&xor_block_32regs);\n+\txor_register(&xor_block_SPARC);\n+}\ndiff --git a/arch/sparc/include/asm/xor_64.h b/arch/sparc/include/asm/xor_64.h\nindex caaddea8ad79..e0482ecc0a68 100644\n--- a/arch/sparc/include/asm/xor_64.h\n+++ b/arch/sparc/include/asm/xor_64.h\n@@ -60,20 +60,17 @@ static struct xor_block_template xor_block_niagara = {\n .do_5\t= xor_niagara_5,\n };\n \n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\t\\\n-\tdo {\t\t\t\t\t\t\\\n-\t\txor_speed(&xor_block_VIS);\t\t\\\n-\t\txor_speed(&xor_block_niagara);\t\t\\\n-\t} while (0)\n-\n-/* For VIS for everything except Niagara. */\n-#define XOR_SELECT_TEMPLATE(FASTEST) \\\n-\t((tlb_type == hypervisor && \\\n-\t (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 || \\\n-\t sun4v_chip_type == SUN4V_CHIP_NIAGARA2 || \\\n-\t sun4v_chip_type == SUN4V_CHIP_NIAGARA3 || \\\n-\t sun4v_chip_type == SUN4V_CHIP_NIAGARA4 || \\\n-\t sun4v_chip_type == SUN4V_CHIP_NIAGARA5)) ? \\\n-\t &xor_block_niagara : \\\n-\t &xor_block_VIS)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\t/* Force VIS for everything except Niagara. */\n+\tif (tlb_type == hypervisor &&\n+\t (sun4v_chip_type == SUN4V_CHIP_NIAGARA1 ||\n+\t sun4v_chip_type == SUN4V_CHIP_NIAGARA2 ||\n+\t sun4v_chip_type == SUN4V_CHIP_NIAGARA3 ||\n+\t sun4v_chip_type == SUN4V_CHIP_NIAGARA4 ||\n+\t sun4v_chip_type == SUN4V_CHIP_NIAGARA5))\n+\t\txor_force(&xor_block_niagara);\n+\telse\n+\t\txor_force(&xor_block_VIS);\n+}\ndiff --git a/arch/x86/include/asm/xor.h b/arch/x86/include/asm/xor.h\nindex 7b0307acc410..33f5620d8d69 100644\n--- a/arch/x86/include/asm/xor.h\n+++ b/arch/x86/include/asm/xor.h\n@@ -496,7 +496,4 @@ static struct xor_block_template xor_block_sse_pf64 = {\n # include <asm/xor_64.h>\n #endif\n \n-#define XOR_SELECT_TEMPLATE(FASTEST) \\\n-\tAVX_SELECT(FASTEST)\n-\n #endif /* _ASM_X86_XOR_H */\ndiff --git a/arch/x86/include/asm/xor_32.h b/arch/x86/include/asm/xor_32.h\nindex 7a6b9474591e..ee32d08c27bc 100644\n--- a/arch/x86/include/asm/xor_32.h\n+++ b/arch/x86/include/asm/xor_32.h\n@@ -552,22 +552,24 @@ static struct xor_block_template xor_block_pIII_sse = {\n /* We force the use of the SSE xor block because it can write around L2.\n We may also be able to load into the L1 only depending on how the cpu\n deals with a load to a line that is being prefetched. */\n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\t\\\n-do {\t\t\t\t\t\t\t\\\n-\tAVX_XOR_SPEED;\t\t\t\t\t\\\n-\tif (boot_cpu_has(X86_FEATURE_XMM)) {\t\t\t\t\\\n-\t\txor_speed(&xor_block_pIII_sse);\t\t\\\n-\t\txor_speed(&xor_block_sse_pf64);\t\t\\\n-\t} else if (boot_cpu_has(X86_FEATURE_MMX)) {\t\\\n-\t\txor_speed(&xor_block_pII_mmx);\t\t\\\n-\t\txor_speed(&xor_block_p5_mmx);\t\t\\\n-\t} else {\t\t\t\t\t\\\n-\t\txor_speed(&xor_block_8regs);\t\t\\\n-\t\txor_speed(&xor_block_8regs_p);\t\t\\\n-\t\txor_speed(&xor_block_32regs);\t\t\\\n-\t\txor_speed(&xor_block_32regs_p);\t\t\\\n-\t}\t\t\t\t\t\t\\\n-} while (0)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\tif (boot_cpu_has(X86_FEATURE_AVX) &&\n+\t boot_cpu_has(X86_FEATURE_OSXSAVE)) {\n+\t\txor_force(&xor_block_avx);\n+\t} else if (boot_cpu_has(X86_FEATURE_XMM)) {\n+\t\txor_register(&xor_block_pIII_sse);\n+\t\txor_register(&xor_block_sse_pf64);\n+\t} else if (boot_cpu_has(X86_FEATURE_MMX)) {\n+\t\txor_register(&xor_block_pII_mmx);\n+\t\txor_register(&xor_block_p5_mmx);\n+\t} else {\n+\t\txor_register(&xor_block_8regs);\n+\t\txor_register(&xor_block_8regs_p);\n+\t\txor_register(&xor_block_32regs);\n+\t\txor_register(&xor_block_32regs_p);\n+\t}\n+}\n \n #endif /* _ASM_X86_XOR_32_H */\ndiff --git a/arch/x86/include/asm/xor_64.h b/arch/x86/include/asm/xor_64.h\nindex 0307e4ec5044..2d2ceb241866 100644\n--- a/arch/x86/include/asm/xor_64.h\n+++ b/arch/x86/include/asm/xor_64.h\n@@ -17,12 +17,16 @@ static struct xor_block_template xor_block_sse = {\n /* We force the use of the SSE xor block because it can write around L2.\n We may also be able to load into the L1 only depending on how the cpu\n deals with a load to a line that is being prefetched. */\n-#undef XOR_TRY_TEMPLATES\n-#define XOR_TRY_TEMPLATES\t\t\t\\\n-do {\t\t\t\t\t\t\\\n-\tAVX_XOR_SPEED;\t\t\t\t\\\n-\txor_speed(&xor_block_sse_pf64);\t\t\\\n-\txor_speed(&xor_block_sse);\t\t\\\n-} while (0)\n+#define arch_xor_init arch_xor_init\n+static __always_inline void __init arch_xor_init(void)\n+{\n+\tif (boot_cpu_has(X86_FEATURE_AVX) &&\n+\t boot_cpu_has(X86_FEATURE_OSXSAVE)) {\n+\t\txor_force(&xor_block_avx);\n+\t} else {\n+\t\txor_register(&xor_block_sse_pf64);\n+\t\txor_register(&xor_block_sse);\n+\t}\n+}\n \n #endif /* _ASM_X86_XOR_64_H */\ndiff --git a/arch/x86/include/asm/xor_avx.h b/arch/x86/include/asm/xor_avx.h\nindex 7f81dd5897f4..c600888436bb 100644\n--- a/arch/x86/include/asm/xor_avx.h\n+++ b/arch/x86/include/asm/xor_avx.h\n@@ -166,13 +166,4 @@ static struct xor_block_template xor_block_avx = {\n \t.do_5 = xor_avx_5,\n };\n \n-#define AVX_XOR_SPEED \\\n-do { \\\n-\tif (boot_cpu_has(X86_FEATURE_AVX) && boot_cpu_has(X86_FEATURE_OSXSAVE)) \\\n-\t\txor_speed(&xor_block_avx); \\\n-} while (0)\n-\n-#define AVX_SELECT(FASTEST) \\\n-\t(boot_cpu_has(X86_FEATURE_AVX) && boot_cpu_has(X86_FEATURE_OSXSAVE) ? &xor_block_avx : FASTEST)\n-\n #endif\ndiff --git a/include/asm-generic/xor.h b/include/asm-generic/xor.h\nindex 44509d48fca2..79c0096aa9d9 100644\n--- a/include/asm-generic/xor.h\n+++ b/include/asm-generic/xor.h\n@@ -728,11 +728,3 @@ static struct xor_block_template xor_block_32regs_p __maybe_unused = {\n \t.do_4 = xor_32regs_p_4,\n \t.do_5 = xor_32regs_p_5,\n };\n-\n-#define XOR_TRY_TEMPLATES\t\t\t\\\n-\tdo {\t\t\t\t\t\\\n-\t\txor_speed(&xor_block_8regs);\t\\\n-\t\txor_speed(&xor_block_8regs_p);\t\\\n-\t\txor_speed(&xor_block_32regs);\t\\\n-\t\txor_speed(&xor_block_32regs_p);\t\\\n-\t} while (0)\ndiff --git a/include/linux/raid/xor_impl.h b/include/linux/raid/xor_impl.h\nindex a1890cd66812..6ed4c445ab24 100644\n--- a/include/linux/raid/xor_impl.h\n+++ b/include/linux/raid/xor_impl.h\n@@ -2,6 +2,8 @@\n #ifndef _XOR_IMPL_H\n #define _XOR_IMPL_H\n \n+#include <linux/init.h>\n+\n struct xor_block_template {\n \tstruct xor_block_template *next;\n \tconst char *name;\n@@ -22,4 +24,7 @@ struct xor_block_template {\n \t\t const unsigned long * __restrict);\n };\n \n+void __init xor_register(struct xor_block_template *tmpl);\n+void __init xor_force(struct xor_block_template *tmpl);\n+\n #endif /* _XOR_IMPL_H */\ndiff --git a/lib/raid/xor/xor-core.c b/lib/raid/xor/xor-core.c\nindex db1824011a12..93608b5fece9 100644\n--- a/lib/raid/xor/xor-core.c\n+++ b/lib/raid/xor/xor-core.c\n@@ -14,10 +14,6 @@\n #include <linux/preempt.h>\n #include <asm/xor.h>\n \n-#ifndef XOR_SELECT_TEMPLATE\n-#define XOR_SELECT_TEMPLATE(x) (x)\n-#endif\n-\n /* The xor routines to use. */\n static struct xor_block_template *active_template;\n \n@@ -55,12 +51,33 @@ EXPORT_SYMBOL(xor_blocks);\n static struct xor_block_template *__initdata template_list;\n static bool __initdata xor_forced = false;\n \n-static void __init do_xor_register(struct xor_block_template *tmpl)\n+/**\n+ * xor_register - register a XOR template\n+ * @tmpl:\ttemplate to register\n+ *\n+ * Register a XOR implementation with the core. Registered implementations\n+ * will be measured by a trivial benchmark, and the fastest one is chosen\n+ * unless an implementation is forced using xor_force().\n+ */\n+void __init xor_register(struct xor_block_template *tmpl)\n {\n \ttmpl->next = template_list;\n \ttemplate_list = tmpl;\n }\n \n+/**\n+ * xor_force - force use of a XOR template\n+ * @tmpl:\ttemplate to register\n+ *\n+ * Register a XOR implementation with the core and force using it. Forcing\n+ * an implementation will make the core ignore any template registered using\n+ * xor_register(), or any previous implementation forced using xor_force().\n+ */\n+void __init xor_force(struct xor_block_template *tmpl)\n+{\n+\tactive_template = tmpl;\n+}\n+\n #define BENCH_SIZE\t4096\n #define REPS\t\t800U\n \n@@ -126,11 +143,19 @@ static int __init calibrate_xor_blocks(void)\n \n static int __init xor_init(void)\n {\n+#ifdef arch_xor_init\n+\tarch_xor_init();\n+#else\n+\txor_register(&xor_block_8regs);\n+\txor_register(&xor_block_8regs_p);\n+\txor_register(&xor_block_32regs);\n+\txor_register(&xor_block_32regs_p);\n+#endif\n+\n \t/*\n \t * If this arch/cpu has a short-circuited selection, don't loop through\n \t * all the possible functions, just use the best one.\n \t */\n-\tactive_template = XOR_SELECT_TEMPLATE(NULL);\n \tif (active_template) {\n \t\tpr_info(\"xor: automatically using best checksumming function %-10s\\n\",\n \t\t\tactive_template->name);\n@@ -138,10 +163,6 @@ static int __init xor_init(void)\n \t\treturn 0;\n \t}\n \n-#define xor_speed\tdo_xor_register\n-\tXOR_TRY_TEMPLATES;\n-#undef xor_speed\n-\n #ifdef MODULE\n \treturn calibrate_xor_blocks();\n #else\n", "prefixes": [ "09/28" ] }