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GET /api/patches/2216663/?format=api
{ "id": 2216663, "url": "http://patchwork.ozlabs.org/api/patches/2216663/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-2-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327025228.474257-2-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-27T02:52:23", "name": "[1/5] backends/iommufd: Introduce iommufd_backend_alloc_faultq", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f8d2a87df69049008e1855be02f933e7b1f7b06a", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-2-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497680, "url": "http://patchwork.ozlabs.org/api/series/497680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497680", "date": "2026-03-27T02:52:22", "name": "intel_iommu: Enable PRQ support for passthrough device", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216663/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216663/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=M1paV1vQ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhlb24cYwz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 13:53:50 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5xJY-0005Xc-Ir; Thu, 26 Mar 2026 22:52:48 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJU-0005Wa-Nq\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 22:52:45 -0400", "from mgamail.intel.com ([192.198.163.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJT-00083T-1k\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 22:52:44 -0400", "from fmviesa007.fm.intel.com ([10.60.135.147])\n by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:42 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:38 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774579963; x=1806115963;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=w5vSF8KYox0CHnA35X/HlNBRury1CbOEj6ktSvWYxDg=;\n b=M1paV1vQkF+G/CDgyTbT1vn/NSBmRnQc8lAnTnYaqQLXEyHsFByWo0UH\n 2oDGqIb+PuOoGEt7BPibqb/WIUpKxK4NvJFnGjIrSiDfmReVF4qgZSMlF\n k0KhR0ct1/4s0YISoXaIhmcXpKFN0DBnsNcbQqnj8sqw41EzPX5nsD07z\n udJQSeZbr6iQoQ7NM5yziGWSQItXnF/RkNNZDyZdZvwFxxp+ccNgEHV7W\n 22SoxOVzzlUn+9Re0aL8ko3SJwKnsOvbidoUWp3RYsrZ/PxxLVMEyg8Mn\n vvAF3WTOMl13mOCW1We2jZkldAWhWpVJWFnqZ3NqOcKcOP0M1KxK9gfMF Q==;", "X-CSE-ConnectionGUID": [ "FZ0KGynHSdmlRgIdzW0NbA==", "KyFET4/UQgmFgo1t+CeniA==" ], "X-CSE-MsgGUID": [ "/jCtXBf2SfCaTvyZi6X92g==", "hJ5UlfSaQ/Kwxe02QtYgjg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"75719878\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"75719878\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"221874380\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH 1/5] backends/iommufd: Introduce iommufd_backend_alloc_faultq", "Date": "Thu, 26 Mar 2026 22:52:23 -0400", "Message-ID": "<20260327025228.474257-2-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "References": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=192.198.163.14;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Add a new helper for IOMMU_FAULT_QUEUE_ALLOC ioctl to allocate a fault\nhandling object which will be used in hwpt allocation.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n include/system/iommufd.h | 3 +++\n backends/iommufd.c | 21 +++++++++++++++++++++\n backends/trace-events | 1 +\n 3 files changed, 25 insertions(+)", "diff": "diff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex 45a9e87cb0..d4ba8434a5 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -100,6 +100,9 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n uint32_t *out_veventq_id,\n uint32_t *out_veventq_fd, Error **errp);\n \n+bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *fault_id,\n+ uint32_t *fault_fd, Error **errp);\n+\n bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be, uint32_t hwpt_id,\n bool start, Error **errp);\n bool iommufd_backend_get_dirty_bitmap(IOMMUFDBackend *be, uint32_t hwpt_id,\ndiff --git a/backends/iommufd.c b/backends/iommufd.c\nindex ab612e4874..9496377a25 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -337,6 +337,27 @@ bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,\n return true;\n }\n \n+bool iommufd_backend_alloc_faultq(IOMMUFDBackend *be, uint32_t *fault_id,\n+ uint32_t *fault_fd, Error **errp)\n+{\n+ int ret, fd = be->fd;\n+ struct iommu_fault_alloc cmd = {\n+ .size = sizeof(cmd),\n+ };\n+\n+ ret = ioctl(fd, IOMMU_FAULT_QUEUE_ALLOC, &cmd);\n+ trace_iommufd_backend_alloc_faultq(fd, cmd.out_fault_id, cmd.out_fault_fd,\n+ ret);\n+ if (ret) {\n+ error_setg_errno(errp, errno, \"Failed to allocate fault queue\");\n+ return false;\n+ }\n+\n+ *fault_id = cmd.out_fault_id;\n+ *fault_fd = cmd.out_fault_fd;\n+ return true;\n+}\n+\n bool iommufd_backend_set_dirty_tracking(IOMMUFDBackend *be,\n uint32_t hwpt_id, bool start,\n Error **errp)\ndiff --git a/backends/trace-events b/backends/trace-events\nindex b9365113e7..6820a9939e 100644\n--- a/backends/trace-events\n+++ b/backends/trace-events\n@@ -17,6 +17,7 @@ iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t ioas, uint64_t iova, u\n iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint64_t size, int ret) \" iommufd=%d ioas=%d iova=0x%\"PRIx64\" size=0x%\"PRIx64\" (%d)\"\n iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) \" iommufd=%d ioas=%d\"\n iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_t out_hwpt_id, int ret) \" iommufd=%d dev_id=%u pt_id=%u flags=0x%x hwpt_type=%u len=%u data_ptr=0x%\"PRIx64\" out_hwpt=%u (%d)\"\n+iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t fault_fd, int ret) \" iommufd=%d fault_id=%d fault_fd=%d (%d)\"\n iommufd_backend_free_id(int iommufd, uint32_t id, int ret) \" iommufd=%d id=%d (%d)\"\n iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int ret) \" iommufd=%d hwpt=%u enable=%d (%d)\"\n iommufd_backend_get_dirty_bitmap(int iommufd, uint32_t hwpt_id, uint64_t iova, uint64_t size, uint64_t flags, uint64_t page_size, int ret) \" iommufd=%d hwpt=%u iova=0x%\"PRIx64\" size=0x%\"PRIx64\" flags=0x%\"PRIx64\" page_size=0x%\"PRIx64\" (%d)\"\n", "prefixes": [ "1/5" ] }