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GET /api/patches/2216662/?format=api
{ "id": 2216662, "url": "http://patchwork.ozlabs.org/api/patches/2216662/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-6-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327025228.474257-6-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-27T02:52:27", "name": "[5/5] intel_iommu_accel: teardown FAULTQ resources in bottom half", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3b149356f05e963bfdf15f9b687398cad2273b72", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-6-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497680, "url": "http://patchwork.ozlabs.org/api/series/497680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497680", "date": "2026-03-27T02:52:22", "name": "intel_iommu: Enable PRQ support for passthrough device", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216662/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216662/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=LwR7h1Q4;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhlZt6Jcqz1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 13:53:42 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5xJk-0005b5-Hx; Thu, 26 Mar 2026 22:53:00 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJi-0005ax-Ng\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 22:52:58 -0400", "from mgamail.intel.com ([192.198.163.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJg-00084r-PF\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 22:52:58 -0400", "from fmviesa007.fm.intel.com ([10.60.135.147])\n by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:56 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:53 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774579977; x=1806115977;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=gk5YKDTXHBRElQkSDgWIK91hDMH8PgkY/KFjKATXZEI=;\n b=LwR7h1Q4ceHX+luppnq4l39936UNYUIiSf70avJjZF6nng+eVqx4Sfu0\n JrjULOMSQ7nrmRlBWzPatZptiOmrXxM+xAfbeG4QN3jvBS+QeYNV3/aFp\n iLdIELGeaDTzOmUWGDnlZkvWjaDgWx31X1rpcGOdakVrK4qJsTJ/QJ0yM\n hBPBwomF1ODQIpEhvisFOO6fJ1Ryd221sW2XzACdbfWR1jS+MFI+u0drx\n GuNKYzf8ZcjgpKD9mRChgA1hQwEG4IBD1ujmaVwm2/t0vH+DYXOYxUFAo\n e2+F0LsE6WeKXiaF27Qt6KMlbVYTGu8vpzDXp1VwcF0d9Z+8z9HKG6wnd Q==;", "X-CSE-ConnectionGUID": [ "CYfhNV8hTuWX3nCydpZ1xg==", "I+Me9fTLR9aAjQ582pARFQ==" ], "X-CSE-MsgGUID": [ "HbBaUWXXSdGXhKhYRphHgA==", "eLxTD4IHTxCeN0RKJXe8cQ==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"75719916\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"75719916\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"221874395\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH 5/5] intel_iommu_accel: teardown FAULTQ resources in bottom\n half", "Date": "Thu, 26 Mar 2026 22:52:27 -0400", "Message-ID": "<20260327025228.474257-6-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "References": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=192.198.163.14;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "When a pasid entry becomes invalid, we need to release all resources\nallocated for that entry including FAULTQ object and fault_fd.\n\nWe call qemu_set_fd_handler() to detach fault_fd's io_read handler and\nwakes up main thread from poll(), but there could still be a small\nwindow we call iommufd_backend_free_id(fault_id) before poll() exit\nand release fault_id file reference. In this rare case, FAULTQ object\nfree return -EBUSY because opened fault_id file keeps reference of\nFAULTQ object.\n\nTeardown FAULTQ resources in bottom half to ensure poll() has released\nfault_id file reference.\n\nSuggested-by: Shameer Kolothum <skolothumtho@nvidia.com>\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n hw/i386/intel_iommu_accel.c | 31 +++++++++++++++++++++++++++++--\n 1 file changed, 29 insertions(+), 2 deletions(-)", "diff": "diff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex 44af534c55..fdc376c070 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -267,16 +267,43 @@ free_faultq:\n return false;\n }\n \n+typedef struct IOMMUFaultQueue {\n+ IOMMUFDBackend *iommufd;\n+ uint32_t id;\n+ int fd;\n+} IOMMUFaultQueue;\n+\n+static void faultq_teardown_bh(void *opaque)\n+{\n+ IOMMUFaultQueue *fq = opaque;\n+\n+ qemu_set_fd_handler(fq->fd, NULL, NULL, NULL);\n+ close(fq->fd);\n+ iommufd_backend_free_id(fq->iommufd, fq->id);\n+\n+ g_free(fq);\n+}\n+\n+\n static void vtd_destroy_old_fs_faultq(VTDHostIOMMUDevice *vtd_hiod,\n VTDAccelPASIDCacheEntry *vtd_pce)\n {\n+ HostIOMMUDeviceIOMMUFD *idev = HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod);\n+\n if (!vtd_pce->fault_id) {\n return;\n }\n \n vtd_pce->pri_notifier = NULL;\n- qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL);\n- vtd_destroy_fs_faultq(vtd_hiod, vtd_pce->fault_id, vtd_pce->fault_fd);\n+\n+ IOMMUFaultQueue *fq = g_malloc(sizeof(IOMMUFaultQueue));\n+ fq->iommufd = idev->iommufd;\n+ fq->fd = vtd_pce->fault_fd;\n+ fq->id = vtd_pce->fault_id;\n+\n+ aio_bh_schedule_oneshot(iohandler_get_aio_context(),\n+ faultq_teardown_bh, fq);\n+\n vtd_pce->fault_id = 0;\n vtd_pce->fault_fd = -1;\n }\n", "prefixes": [ "5/5" ] }