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GET /api/patches/2216660/?format=api
{ "id": 2216660, "url": "http://patchwork.ozlabs.org/api/patches/2216660/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-3-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327025228.474257-3-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-27T02:52:24", "name": "[2/5] backends/iommufd: Extend iommufd_backend_alloc_hwpt() with fault_id", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "43b4ab691de643869e19c8bd66d5929db8fb120f", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-3-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497680, "url": "http://patchwork.ozlabs.org/api/series/497680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497680", "date": "2026-03-27T02:52:22", "name": "intel_iommu: Enable PRQ support for passthrough device", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216660/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216660/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=RXHcKMo5;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhlZq2Nr0z1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 13:53:39 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5xJb-0005Yq-2J; Thu, 26 Mar 2026 22:52:51 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJZ-0005Xk-GY; Thu, 26 Mar 2026 22:52:49 -0400", "from mgamail.intel.com ([192.198.163.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJX-00083n-Kg; Thu, 26 Mar 2026 22:52:49 -0400", "from fmviesa007.fm.intel.com ([10.60.135.147])\n by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:45 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:42 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774579968; x=1806115968;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=9of5pivnPhQUXMSB+06b0S6dhtFK7zmVDYOCgP/18KA=;\n b=RXHcKMo5KoMDqLTPjzQZTqNtdNjfPjFMfzwuoubwLXeS1IdcEdOQEtsi\n etuz3kobSKXifO8fLwyplB859MQ1R3vc9t4Y0AklOCGxJ51rBkM9EsI1O\n 3kn8WOtr1Oh2m61zCe0GEaBfr215V+YmQN4KaJNOdnzGTDy4+j4gp63s6\n vKkGDTwdl2o0mb8RK6DPALfWL2SIrNKXu5Vjcj8iMhTma5FzyOD6eA3rM\n FCDkQ9BVxhpiRCc6vJ6v2m9Fa3JUu+qXdZajizYMLLv6mqMOZQnJzxptI\n 7mNrZAKUiB5q77OwzkbFhNUour+7sT4FGHl6Q+YTptnvcQptzqGt4ODb6 A==;", "X-CSE-ConnectionGUID": [ "lAqDTJLIQI+MKZjBxHPnLQ==", "1T5l6teDQhOXaTgXMGB6xQ==" ], "X-CSE-MsgGUID": [ "MjayH4rXTi+CA7C3vg1MKQ==", "1aLT35MvQT+jNqkaSBk2Yg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"75719887\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"75719887\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"221874383\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>,\n qemu-arm@nongnu.org", "Subject": "[PATCH 2/5] backends/iommufd: Extend iommufd_backend_alloc_hwpt()\n with fault_id", "Date": "Thu, 26 Mar 2026 22:52:24 -0400", "Message-ID": "<20260327025228.474257-3-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "References": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=192.198.163.14;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "No need to force caller to set IOMMU_HWPT_FAULT_ID_VALID, we take it\nby checking fault_id nonzero.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n include/system/iommufd.h | 4 ++--\n backends/iommufd.c | 13 +++++++++----\n hw/arm/smmuv3-accel.c | 6 +++---\n hw/i386/intel_iommu_accel.c | 2 +-\n hw/vfio/iommufd.c | 2 +-\n backends/trace-events | 2 +-\n 6 files changed, 17 insertions(+), 12 deletions(-)", "diff": "diff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex d4ba8434a5..f753bfaf69 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -85,8 +85,8 @@ bool iommufd_backend_get_device_info(IOMMUFDBackend *be, uint32_t devid,\n bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,\n uint32_t pt_id, uint32_t flags,\n uint32_t data_type, uint32_t data_len,\n- void *data_ptr, uint32_t *out_hwpt,\n- Error **errp);\n+ void *data_ptr, uint32_t fault_id,\n+ uint32_t *out_hwpt, Error **errp);\n bool iommufd_backend_alloc_viommu(IOMMUFDBackend *be, uint32_t dev_id,\n uint32_t viommu_type, uint32_t hwpt_id,\n uint32_t *out_hwpt, Error **errp);\ndiff --git a/backends/iommufd.c b/backends/iommufd.c\nindex 9496377a25..fe64badea0 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -310,23 +310,28 @@ int iommufd_backend_unmap_dma(IOMMUFDBackend *be, uint32_t ioas_id,\n bool iommufd_backend_alloc_hwpt(IOMMUFDBackend *be, uint32_t dev_id,\n uint32_t pt_id, uint32_t flags,\n uint32_t data_type, uint32_t data_len,\n- void *data_ptr, uint32_t *out_hwpt,\n- Error **errp)\n+ void *data_ptr, uint32_t fault_id,\n+ uint32_t *out_hwpt, Error **errp)\n {\n int ret, fd = be->fd;\n struct iommu_hwpt_alloc alloc_hwpt = {\n .size = sizeof(struct iommu_hwpt_alloc),\n- .flags = flags,\n .dev_id = dev_id,\n .pt_id = pt_id,\n .data_type = data_type,\n .data_len = data_len,\n .data_uptr = (uintptr_t)data_ptr,\n+ .fault_id = fault_id,\n };\n \n+ if (fault_id) {\n+ flags |= IOMMU_HWPT_FAULT_ID_VALID;\n+ }\n+ alloc_hwpt.flags = flags;\n+\n ret = ioctl(fd, IOMMU_HWPT_ALLOC, &alloc_hwpt);\n trace_iommufd_backend_alloc_hwpt(fd, dev_id, pt_id, flags, data_type,\n- data_len, (uintptr_t)data_ptr,\n+ data_len, (uintptr_t)data_ptr, fault_id,\n alloc_hwpt.out_hwpt_id, ret);\n if (ret) {\n error_setg_errno(errp, errno, \"Failed to allocate hwpt\");\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 0af6b3296d..1e2fb1e748 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -224,7 +224,7 @@ smmuv3_accel_dev_alloc_translate(SMMUv3AccelDevice *accel_dev, STE *ste,\n accel->viommu->viommu_id, flags,\n IOMMU_HWPT_DATA_ARM_SMMUV3,\n sizeof(nested_data), &nested_data,\n- &hwpt_id, errp)) {\n+ 0, &hwpt_id, errp)) {\n return NULL;\n }\n \n@@ -558,14 +558,14 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id,\n 0, IOMMU_HWPT_DATA_ARM_SMMUV3,\n sizeof(abort_data), &abort_data,\n- &accel->abort_hwpt_id, errp)) {\n+ 0, &accel->abort_hwpt_id, errp)) {\n goto free_viommu;\n }\n \n if (!iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, viommu_id,\n 0, IOMMU_HWPT_DATA_ARM_SMMUV3,\n sizeof(bypass_data), &bypass_data,\n- &accel->bypass_hwpt_id, errp)) {\n+ 0, &accel->bypass_hwpt_id, errp)) {\n goto free_abort_hwpt;\n }\n \ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex e73695ff83..32cca7672a 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -115,7 +115,7 @@ static bool vtd_create_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod,\n \n return iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, idev->hwpt_id,\n flags, IOMMU_HWPT_DATA_VTD_S1,\n- sizeof(vtd), &vtd, fs_hwpt_id, errp);\n+ sizeof(vtd), &vtd, 0, fs_hwpt_id, errp);\n }\n \n static void vtd_destroy_old_fs_hwpt(VTDHostIOMMUDevice *vtd_hiod,\ndiff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c\nindex dce4e4ce72..e4e8b266ab 100644\n--- a/hw/vfio/iommufd.c\n+++ b/hw/vfio/iommufd.c\n@@ -444,7 +444,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vbasedev,\n if (!iommufd_backend_alloc_hwpt(iommufd, vbasedev->devid,\n container->ioas_id, flags,\n IOMMU_HWPT_DATA_NONE, 0, NULL,\n- &hwpt_id, errp)) {\n+ 0, &hwpt_id, errp)) {\n return false;\n }\n \ndiff --git a/backends/trace-events b/backends/trace-events\nindex 6820a9939e..8a204fcb73 100644\n--- a/backends/trace-events\n+++ b/backends/trace-events\n@@ -16,7 +16,7 @@ iommufd_backend_map_file_dma(int iommufd, uint32_t ioas, uint64_t iova, uint64_t\n iommufd_backend_unmap_dma_non_exist(int iommufd, uint32_t ioas, uint64_t iova, uint64_t size, int ret) \" Unmap nonexistent mapping: iommufd=%d ioas=%d iova=0x%\"PRIx64\" size=0x%\"PRIx64\" (%d)\"\n iommufd_backend_unmap_dma(int iommufd, uint32_t ioas, uint64_t iova, uint64_t size, int ret) \" iommufd=%d ioas=%d iova=0x%\"PRIx64\" size=0x%\"PRIx64\" (%d)\"\n iommufd_backend_alloc_ioas(int iommufd, uint32_t ioas) \" iommufd=%d ioas=%d\"\n-iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_t out_hwpt_id, int ret) \" iommufd=%d dev_id=%u pt_id=%u flags=0x%x hwpt_type=%u len=%u data_ptr=0x%\"PRIx64\" out_hwpt=%u (%d)\"\n+iommufd_backend_alloc_hwpt(int iommufd, uint32_t dev_id, uint32_t pt_id, uint32_t flags, uint32_t hwpt_type, uint32_t len, uint64_t data_ptr, uint32_t fault_id, uint32_t out_hwpt_id, int ret) \" iommufd=%d dev_id=%u pt_id=%u flags=0x%x hwpt_type=%u len=%u data_ptr=0x%\"PRIx64\" fault_id=%u out_hwpt=%u (%d)\"\n iommufd_backend_alloc_faultq(int iommufd, uint32_t fault_id, uint32_t fault_fd, int ret) \" iommufd=%d fault_id=%d fault_fd=%d (%d)\"\n iommufd_backend_free_id(int iommufd, uint32_t id, int ret) \" iommufd=%d id=%d (%d)\"\n iommufd_backend_set_dirty(int iommufd, uint32_t hwpt_id, bool start, int ret) \" iommufd=%d hwpt=%u enable=%d (%d)\"\n", "prefixes": [ "2/5" ] }