Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/2216659/?format=api
{ "id": 2216659, "url": "http://patchwork.ozlabs.org/api/patches/2216659/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-5-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260327025228.474257-5-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-27T02:52:26", "name": "[4/5] intel_iommu_accel: Accept PRQ response for passthrough device", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c79b63ea325abb344f72d007a6b350ea6e26490e", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260327025228.474257-5-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497680, "url": "http://patchwork.ozlabs.org/api/series/497680/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497680", "date": "2026-03-27T02:52:22", "name": "intel_iommu: Enable PRQ support for passthrough device", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497680/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216659/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216659/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=Z1m6Ud2/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhlZp27g4z1xy1\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 13:53:38 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5xJh-0005ar-Um; Thu, 26 Mar 2026 22:52:57 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJf-0005aO-W0\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 22:52:56 -0400", "from mgamail.intel.com ([192.198.163.14])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5xJd-00084r-W0\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 22:52:55 -0400", "from fmviesa007.fm.intel.com ([10.60.135.147])\n by fmvoesa108.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:53 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 19:52:49 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774579974; x=1806115974;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=2NHqSXESvD6JPIlwczaZ1cD/lSOgxjXB8JfRBi7E928=;\n b=Z1m6Ud2/hA9+9V2WMd3yjkJTbYYHymRmWyQO6wd5olOpC4h20DgXh/dg\n SGEblmQqUEx+sdkZJti93JQ4XtFWxBTOr2H63ZW6XOtfW22fpNCRcxLVz\n WMj7rJNqjc/I/tkdd1qudysRi9302Y+hQRrDh8X8kJkaprqzFGSa+Yhak\n JiD9pxOMj4c0ji2VwS5LsnjS3wDdrw25qo/p2dwvIj9ZFtpqJu/g2RCI0\n lC8oTEzggGAZyY96VQV4Q2dckMCQRIhh1YwX8sjJgidbfGbUuF8WOvpy3\n Wv+wWJhbRifEaYVhci9P6DOBXmAvi5UE8sjXU19zrtr0h8ZwKOleILzHv Q==;", "X-CSE-ConnectionGUID": [ "EZXbEOsFR0mAAXHPHU00Rw==", "AWgkCBLDTRubp9msX1uCow==" ], "X-CSE-MsgGUID": [ "dKQXmQQiQY+sts71CyTsrg==", "FCal3sZ8QWKziI/LNLR9+A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"75719908\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"75719908\"", "E=Sophos;i=\"6.23,143,1770624000\"; d=\"scan'208\";a=\"221874391\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH 4/5] intel_iommu_accel: Accept PRQ response for passthrough\n device", "Date": "Thu, 26 Mar 2026 22:52:26 -0400", "Message-ID": "<20260327025228.474257-5-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "References": "<20260327025228.474257-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=192.198.163.14;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Propagate guest's PRQ response to host by writing to fault_fd.\nCreate a new VTDPRQEntry to cache cookie for each fault group,\nthis cookie is used to mark the fault group on host side.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n hw/i386/intel_iommu_accel.h | 14 ++++++++\n include/hw/i386/intel_iommu.h | 6 ++++\n hw/i386/intel_iommu.c | 4 +++\n hw/i386/intel_iommu_accel.c | 65 +++++++++++++++++++++++++++++++++++\n hw/i386/trace-events | 1 +\n 5 files changed, 90 insertions(+)", "diff": "diff --git a/hw/i386/intel_iommu_accel.h b/hw/i386/intel_iommu_accel.h\nindex 10e6ee5722..b46c7126f7 100644\n--- a/hw/i386/intel_iommu_accel.h\n+++ b/hw/i386/intel_iommu_accel.h\n@@ -19,6 +19,9 @@ typedef struct VTDAccelPASIDCacheEntry {\n uint32_t fs_hwpt_id;\n uint32_t fault_id;\n int fault_fd;\n+ QLIST_HEAD(, VTDPRQEntry) vtd_prq_list;\n+ IOMMUPRINotifier pri_notifier_entry;\n+ IOMMUPRINotifier *pri_notifier;\n QLIST_ENTRY(VTDAccelPASIDCacheEntry) next;\n } VTDAccelPASIDCacheEntry;\n \n@@ -31,6 +34,9 @@ void vtd_flush_host_piotlb_all_accel(IntelIOMMUState *s, uint16_t domain_id,\n uint64_t npages, bool ih);\n void vtd_pasid_cache_sync_accel(IntelIOMMUState *s, VTDPASIDCacheInfo *pc_info);\n void vtd_pasid_cache_reset_accel(IntelIOMMUState *s);\n+bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s,\n+ uint16_t rid, uint32_t pasid,\n+ IOMMUPRIResponse *response);\n void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops);\n #else\n static inline bool vtd_check_hiod_accel(IntelIOMMUState *s,\n@@ -69,6 +75,14 @@ static inline void vtd_pasid_cache_reset_accel(IntelIOMMUState *s)\n {\n }\n \n+static inline\n+bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s,\n+ uint16_t rid, uint32_t pasid,\n+ IOMMUPRIResponse *response)\n+{\n+ return false;\n+}\n+\n static inline void vtd_iommu_ops_update_accel(PCIIOMMUOps *ops)\n {\n }\ndiff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h\nindex 1842ba5840..5d44eac0ed 100644\n--- a/include/hw/i386/intel_iommu.h\n+++ b/include/hw/i386/intel_iommu.h\n@@ -100,6 +100,12 @@ typedef struct VTDPASIDCacheEntry {\n bool valid;\n } VTDPASIDCacheEntry;\n \n+typedef struct VTDPRQEntry {\n+ uint32_t grpid;\n+ uint32_t cookie;\n+ QLIST_ENTRY(VTDPRQEntry) next;\n+} VTDPRQEntry;\n+\n struct VTDAddressSpace {\n PCIBus *bus;\n uint8_t devfn;\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex 96b4102ab9..d670a0377b 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -3390,6 +3390,10 @@ static bool vtd_process_page_group_response_desc(IntelIOMMUState *s,\n response.response_code = IOMMU_PRI_RESP_FAILURE;\n }\n \n+ if (vtd_propagate_page_group_response_accel(s, rid, pasid, &response)) {\n+ return true;\n+ }\n+\n if (vtd_dev_as->pri_notifier) {\n vtd_dev_as->pri_notifier->notify(vtd_dev_as->pri_notifier, &response);\n }\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex 0fce62ff75..44af534c55 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -102,6 +102,30 @@ VTDHostIOMMUDevice *vtd_find_hiod_iommufd(VTDAddressSpace *as)\n return NULL;\n }\n \n+bool vtd_propagate_page_group_response_accel(IntelIOMMUState *s,\n+ uint16_t rid, uint32_t pasid,\n+ IOMMUPRIResponse *response)\n+{\n+ VTDAddressSpace *vtd_as = vtd_get_as_by_sid(s, rid);\n+ VTDAccelPASIDCacheEntry *vtd_pce;\n+ VTDHostIOMMUDevice *vtd_hiod = vtd_find_hiod_iommufd(vtd_as);\n+\n+ if (!vtd_hiod) {\n+ return false;\n+ }\n+\n+ QLIST_FOREACH(vtd_pce, &vtd_hiod->pasid_cache_list, next) {\n+ if (vtd_pce->pasid == pasid) {\n+ if (vtd_pce->pri_notifier) {\n+ vtd_pce->pri_notifier->notify(vtd_pce->pri_notifier, response);\n+ }\n+ return true;\n+ }\n+ }\n+\n+ return false;\n+}\n+\n static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce,\n struct iommu_hwpt_pgfault *fault, int cnt)\n {\n@@ -117,6 +141,13 @@ static void vtd_prq_report_fault(VTDAccelPASIDCacheEntry *vtd_pce,\n fault->addr, last_page, fault->grpid,\n fault->perm & IOMMU_PGFAULT_PERM_READ,\n fault->perm & IOMMU_PGFAULT_PERM_WRITE);\n+ if (last_page) {\n+ VTDPRQEntry *prqe = g_malloc0(sizeof(*prqe));\n+\n+ prqe->grpid = fault->grpid;\n+ prqe->cookie = fault->cookie;\n+ QLIST_INSERT_HEAD(&vtd_pce->vtd_prq_list, prqe, next);\n+ }\n }\n }\n \n@@ -150,6 +181,36 @@ static void vtd_prq_read_fault(void *opaque)\n vtd_prq_report_fault(vtd_pce, fault, bytes / sizeof(fault[0]));\n }\n \n+static void vtd_prq_response_notify(struct IOMMUPRINotifier *notifier,\n+ IOMMUPRIResponse *response)\n+{\n+ VTDAccelPASIDCacheEntry *vtd_pce =\n+ container_of(notifier, VTDAccelPASIDCacheEntry, pri_notifier_entry);\n+ uint32_t id = vtd_pce->fault_id, fd = vtd_pce->fault_fd;\n+ struct iommu_hwpt_page_response resp;\n+ VTDPRQEntry *prqe, *tmp;\n+ ssize_t bytes;\n+\n+ QLIST_FOREACH_SAFE(prqe, &vtd_pce->vtd_prq_list, next, tmp) {\n+ if (prqe->grpid != response->prgi) {\n+ continue;\n+ }\n+\n+ resp.cookie = prqe->cookie;\n+ resp.code = response->response_code;\n+ bytes = write(fd, &resp, sizeof(resp));\n+ trace_vtd_prq_response_notify(id, fd, resp.cookie, resp.code, bytes);\n+ if (bytes < 0) {\n+ error_report_once(\"FAULTQ(id %u): write failed \"\n+ \"[cookie 0x%x code 0x%x] (%m)\",\n+ id, resp.cookie, resp.code);\n+ }\n+\n+ QLIST_REMOVE(prqe, next);\n+ g_free(prqe);\n+ }\n+}\n+\n static void vtd_destroy_fs_faultq(VTDHostIOMMUDevice *vtd_hiod,\n uint32_t fault_id, uint32_t fault_fd)\n {\n@@ -213,6 +274,7 @@ static void vtd_destroy_old_fs_faultq(VTDHostIOMMUDevice *vtd_hiod,\n return;\n }\n \n+ vtd_pce->pri_notifier = NULL;\n qemu_set_fd_handler(vtd_pce->fault_fd, NULL, NULL, NULL);\n vtd_destroy_fs_faultq(vtd_hiod, vtd_pce->fault_id, vtd_pce->fault_fd);\n vtd_pce->fault_id = 0;\n@@ -228,6 +290,8 @@ static void vtd_setup_fs_faultq(VTDAccelPASIDCacheEntry *vtd_pce,\n \n vtd_pce->fault_id = fault_id;\n vtd_pce->fault_fd = fault_fd;\n+ vtd_pce->pri_notifier_entry.notify = vtd_prq_response_notify;\n+ vtd_pce->pri_notifier = &vtd_pce->pri_notifier_entry;\n qemu_set_fd_handler(fault_fd, vtd_prq_read_fault, NULL, vtd_pce);\n }\n \n@@ -492,6 +556,7 @@ static void vtd_accel_fill_pc(VTDHostIOMMUDevice *vtd_hiod, uint32_t pasid,\n vtd_pce->vtd_hiod = vtd_hiod;\n vtd_pce->pasid = pasid;\n vtd_pce->pasid_entry = *pe;\n+ QLIST_INIT(&vtd_pce->vtd_prq_list);\n QLIST_INSERT_HEAD(&vtd_hiod->pasid_cache_list, vtd_pce, next);\n \n if (!vtd_device_attach_iommufd(vtd_pce, &local_err)) {\ndiff --git a/hw/i386/trace-events b/hw/i386/trace-events\nindex bf139338f7..52dab0b508 100644\n--- a/hw/i386/trace-events\n+++ b/hw/i386/trace-events\n@@ -78,6 +78,7 @@ vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int re\n vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) \"dev_id %d pasid %d ret: %d\"\n vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, int ret) \"dev_id %d pasid %d hwpt_id %d, ret: %d\"\n vtd_prq_read_fault(uint32_t fault_id, uint32_t fault_fd, ssize_t bytes) \"fault_id %d fault_fd %d ret: %zd\"\n+vtd_prq_response_notify(uint32_t fault_id, uint32_t fault_fd, uint32_t cookie, uint32_t code, ssize_t bytes) \"fault_id %d fault_fd %d cookie %d code %d ret: %zd\"\n \n # amd_iommu.c\n amdvi_evntlog_fail(uint64_t addr, uint32_t head) \"error: fail to write at addr 0x%\"PRIx64\" + offset 0x%\"PRIx32\n", "prefixes": [ "4/5" ] }