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GET /api/patches/2216519/?format=api
{ "id": 2216519, "url": "http://patchwork.ozlabs.org/api/patches/2216519/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260326162832.3135857-2-grzegorz.nitka@intel.com/", "project": { "id": 46, "url": "http://patchwork.ozlabs.org/api/projects/46/?format=api", "name": "Intel Wired Ethernet development", "link_name": "intel-wired-lan", "list_id": "intel-wired-lan.osuosl.org", "list_email": "intel-wired-lan@osuosl.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326162832.3135857-2-grzegorz.nitka@intel.com>", "list_archive_url": null, "date": "2026-03-26T16:28:25", "name": "[v4,net-next,1/8] dpll: add new DPLL type for transmit clock (TXC) usage", "commit_ref": null, "pull_url": null, "state": "handled-elsewhere", "archived": false, "hash": "c799b3e36f5ad318cbacf048a4e2341f7804ed00", "submitter": { "id": 82711, "url": "http://patchwork.ozlabs.org/api/people/82711/?format=api", "name": "Nitka, Grzegorz", "email": "grzegorz.nitka@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/intel-wired-lan/patch/20260326162832.3135857-2-grzegorz.nitka@intel.com/mbox/", "series": [ { "id": 497620, "url": "http://patchwork.ozlabs.org/api/series/497620/?format=api", "web_url": "http://patchwork.ozlabs.org/project/intel-wired-lan/list/?series=497620", "date": "2026-03-26T16:28:24", "name": "dpll/ice: Add TXC DPLL type and full TX reference clock control for E825", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497620/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216519/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216519/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<intel-wired-lan-bounces@osuosl.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "intel-wired-lan@lists.osuosl.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=osuosl.org header.i=@osuosl.org header.a=rsa-sha256\n header.s=default header.b=BRMeAf8j;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=osuosl.org\n (client-ip=2605:bc80:3010::136; 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Thu, 26 Mar 2026 16:32:26 +0000 (UTC)", "from localhost (localhost [127.0.0.1])\n by smtp3.osuosl.org (Postfix) with ESMTP id D7B0160853\n for <intel-wired-lan@lists.osuosl.org>; Thu, 26 Mar 2026 16:32:26 +0000 (UTC)", "from smtp3.osuosl.org ([127.0.0.1])\n by localhost (smtp3.osuosl.org [127.0.0.1]) (amavis, port 10024) with ESMTP\n id Pb5-9hMIQF4G for <intel-wired-lan@lists.osuosl.org>;\n Thu, 26 Mar 2026 16:32:25 +0000 (UTC)", "from mgamail.intel.com (mgamail.intel.com [192.198.163.19])\n by smtp3.osuosl.org (Postfix) with ESMTPS id 1E0B86084C\n for <intel-wired-lan@lists.osuosl.org>; Thu, 26 Mar 2026 16:32:25 +0000 (UTC)", "from orviesa007.jf.intel.com ([10.64.159.147])\n by fmvoesa113.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 09:32:24 -0700", "from gklab-003-001.igk.intel.com ([10.91.173.48])\n by orviesa007.jf.intel.com with ESMTP; 26 Mar 2026 09:32:20 -0700" ], "X-Virus-Scanned": [ "amavis at osuosl.org", "amavis at osuosl.org" ], "X-Comment": "SPF check N/A for local connections - client-ip=140.211.166.142;\n helo=lists1.osuosl.org; envelope-from=intel-wired-lan-bounces@osuosl.org;\n receiver=<UNKNOWN> ", "DKIM-Filter": [ "OpenDKIM Filter v2.11.0 smtp3.osuosl.org 51A0B60853", "OpenDKIM Filter v2.11.0 smtp3.osuosl.org 1E0B86084C" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=osuosl.org;\n\ts=default; t=1774542748;\n\tbh=tRmyZ4Aa8cDa7qvEl6tnZtb4W8ctKZYXHkxtKUVnDek=;\n\th=From:To:Date:In-Reply-To:References:Subject:List-Id:\n\t List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe:\n\t Cc:From;\n\tb=BRMeAf8jcln5AiHamqjKP4vRan70qjl+U+GoHAGDQzoNX8T6AqRpgiCe7Z1omviYV\n\t CD06v56pKwXn58vOpD09JwI/j6arheYi15cX5ge96VCDxiatHOf0s+izOIfVBLCu2p\n\t DGMR4vd1RGJGb5a/AV/O3J0eGYRJ5d2yzDKJmG30PgVGH21EUm5t62k6ovp3IM4EN1\n\t zMbt0/3OjQU57HnjxKGAGHFSB8A/oPdidwTAl2c+ezkWWZhJYAERhO1WXuQVgD/h0V\n\t lKPmyq99AHKPoSNOguU9UQIRYa4NHr2o4aeyYZXvW/br1r34T+VAtdHfm53CwLmyXT\n\t S+RazEhQEaauQ==", "Received-SPF": "Pass (mailfrom) identity=mailfrom; client-ip=192.198.163.19;\n helo=mgamail.intel.com; envelope-from=grzegorz.nitka@intel.com;\n receiver=<UNKNOWN>", "DMARC-Filter": "OpenDMARC Filter v1.4.2 smtp3.osuosl.org 1E0B86084C", "X-CSE-ConnectionGUID": [ "gsUioTshQW6ZWAOhyXLLdw==", "dfd35oV+TCaHZ6HM57vDPw==" ], "X-CSE-MsgGUID": [ "eUyDnY6qSMSL0FbdmFpc2g==", "nmJNRV5ESau2FtC0lmev0A==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11741\"; a=\"74636562\"", "E=Sophos;i=\"6.23,142,1770624000\"; d=\"scan'208\";a=\"74636562\"", "E=Sophos;i=\"6.23,142,1770624000\"; d=\"scan'208\";a=\"225310865\"" ], "X-ExtLoop1": "1", "From": "Grzegorz Nitka <grzegorz.nitka@intel.com>", "To": "netdev@vger.kernel.org", "Date": "Thu, 26 Mar 2026 17:28:25 +0100", "Message-Id": "<20260326162832.3135857-2-grzegorz.nitka@intel.com>", "X-Mailer": "git-send-email 2.39.3", "In-Reply-To": "<20260326162832.3135857-1-grzegorz.nitka@intel.com>", "References": "<20260326162832.3135857-1-grzegorz.nitka@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-Mailman-Original-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774542745; x=1806078745;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=h6SdAt8V/8U61Dau5TYRbsrbBcUy7opyRgE4IDMhs3o=;\n b=d1/c57mxfXE6bURXtrNj9UtoNAvmGpPCyDNbzdOz79PiprjmxQyxlygF\n ffRlqpQnInT7WHr+b4T0yE24Uk8qBXlHxeOGTCSorLw7e3HGAEtm/e4Vo\n tI71hWlT3HvCZBLw0i8AjjFOQb3+6IWpaxe16O7RNPmWyGjxOCgHCGGO+\n Xs9Z71ADnSb7rxkka432YJwCpHddo2WneAQccTHND1/lp7b3qi+fS5JIP\n 2WSoopYfaVTHgg69AeONzUsZuYC1LtbYWvxP4Kh43Rxw4dgD2E6Wpk2gY\n J47CtR4qi0KpeIetrniXLhzYsJHjp+cL3dHEtxFCi2wP/mobeqQnNswup\n A==;", "X-Mailman-Original-Authentication-Results": [ "smtp3.osuosl.org;\n dmarc=pass (p=none dis=none)\n header.from=intel.com", "smtp3.osuosl.org;\n dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.a=rsa-sha256 header.s=Intel header.b=d1/c57mx" ], "Subject": "[Intel-wired-lan] [PATCH v4 net-next 1/8] dpll: add new DPLL type\n for transmit clock (TXC) usage", "X-BeenThere": "intel-wired-lan@osuosl.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Intel Wired Ethernet Linux Kernel Driver Development\n <intel-wired-lan.osuosl.org>", "List-Unsubscribe": "<https://lists.osuosl.org/mailman/options/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=unsubscribe>", "List-Archive": "<http://lists.osuosl.org/pipermail/intel-wired-lan/>", "List-Post": "<mailto:intel-wired-lan@osuosl.org>", "List-Help": "<mailto:intel-wired-lan-request@osuosl.org?subject=help>", "List-Subscribe": "<https://lists.osuosl.org/mailman/listinfo/intel-wired-lan>,\n <mailto:intel-wired-lan-request@osuosl.org?subject=subscribe>", "Cc": "ivecera@redhat.com, vadim.fedorenko@linux.dev, kuba@kernel.org,\n jiri@resnulli.us, edumazet@google.com, przemyslaw.kitszel@intel.com,\n richardcochran@gmail.com, donald.hunter@gmail.com,\n linux-kernel@vger.kernel.org, arkadiusz.kubalewski@intel.com,\n Aleksandr Loktionov <aleksandr.loktionov@intel.com>, andrew+netdev@lunn.ch,\n intel-wired-lan@lists.osuosl.org, horms@kernel.org,\n Prathosh.Satish@microchip.com, anthony.l.nguyen@intel.com, pabeni@redhat.com,\n davem@davemloft.net, Jiri Pirko <jiri@nvidia.com>", "Errors-To": "intel-wired-lan-bounces@osuosl.org", "Sender": "\"Intel-wired-lan\" <intel-wired-lan-bounces@osuosl.org>" }, "content": "Extend the DPLL subsystem with a new DPLL type, DPLL_TYPE_TXC,\nrepresenting devices that drive a transmit reference clock. Certain\nPHYs, MACs and SerDes blocks use a dedicated TX reference clock for\nlink operation, and this clock domain is distinct from PPS- and\nEEC-driven synchronization sources. Defining a dedicated type allows\nuser space and drivers to correctly classify and configure DPLLs\nintended for TX clock generation.\n\nThe corresponding netlink specification is updated to expose \"txc\".\n\nReviewed-by: Jiri Pirko <jiri@nvidia.com>\nReviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>\nReviewed-by: Aleksandr Loktionov <aleksandr.loktionov@intel.com>\nSigned-off-by: Grzegorz Nitka <grzegorz.nitka@intel.com>\n---\n Documentation/netlink/specs/dpll.yaml | 3 +++\n drivers/dpll/dpll_nl.c | 2 +-\n include/uapi/linux/dpll.h | 2 ++\n 3 files changed, 6 insertions(+), 1 deletion(-)", "diff": "diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml\nindex 3dd48a32f783..2a2ee37a1fc0 100644\n--- a/Documentation/netlink/specs/dpll.yaml\n+++ b/Documentation/netlink/specs/dpll.yaml\n@@ -138,6 +138,9 @@ definitions:\n -\n name: eec\n doc: dpll drives the Ethernet Equipment Clock\n+ -\n+ name: txc\n+ doc: dpll drives Tx reference clock\n render-max: true\n -\n type: enum\ndiff --git a/drivers/dpll/dpll_nl.c b/drivers/dpll/dpll_nl.c\nindex a2b22d492114..4182bdbb6dbb 100644\n--- a/drivers/dpll/dpll_nl.c\n+++ b/drivers/dpll/dpll_nl.c\n@@ -34,7 +34,7 @@ const struct nla_policy dpll_reference_sync_nl_policy[DPLL_A_PIN_STATE + 1] = {\n static const struct nla_policy dpll_device_id_get_nl_policy[DPLL_A_TYPE + 1] = {\n \t[DPLL_A_MODULE_NAME] = { .type = NLA_NUL_STRING, },\n \t[DPLL_A_CLOCK_ID] = { .type = NLA_U64, },\n-\t[DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 2),\n+\t[DPLL_A_TYPE] = NLA_POLICY_RANGE(NLA_U32, 1, 3),\n };\n \n /* DPLL_CMD_DEVICE_GET - do */\ndiff --git a/include/uapi/linux/dpll.h b/include/uapi/linux/dpll.h\nindex de0005f28e5c..8f6db5d5bf0c 100644\n--- a/include/uapi/linux/dpll.h\n+++ b/include/uapi/linux/dpll.h\n@@ -109,10 +109,12 @@ enum dpll_clock_quality_level {\n * enum dpll_type - type of dpll, valid values for DPLL_A_TYPE attribute\n * @DPLL_TYPE_PPS: dpll produces Pulse-Per-Second signal\n * @DPLL_TYPE_EEC: dpll drives the Ethernet Equipment Clock\n+ * @DPLL_TYPE_TXC: dpll drives Tx reference clock\n */\n enum dpll_type {\n \tDPLL_TYPE_PPS = 1,\n \tDPLL_TYPE_EEC,\n+\tDPLL_TYPE_TXC,\n \n \t/* private: */\n \t__DPLL_TYPE_MAX,\n", "prefixes": [ "v4", "net-next", "1/8" ] }