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GET /api/patches/2216475/?format=api
{ "id": 2216475, "url": "http://patchwork.ozlabs.org/api/patches/2216475/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/DHCS8PTZ9DOD.DOKQ7ILVGVFW@gmail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<DHCS8PTZ9DOD.DOKQ7ILVGVFW@gmail.com>", "list_archive_url": null, "date": "2026-03-26T14:27:17", "name": "RISC-V: Allow all vector modes during builtin registration. [PR124613]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cb831d59a432227ed0f48a1ddbadcb061e62b6c2", "submitter": { "id": 86205, "url": "http://patchwork.ozlabs.org/api/people/86205/?format=api", "name": "Robin Dapp", "email": "rdapp.gcc@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/DHCS8PTZ9DOD.DOKQ7ILVGVFW@gmail.com/mbox/", "series": [ { "id": 497602, "url": "http://patchwork.ozlabs.org/api/series/497602/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=497602", "date": "2026-03-26T14:27:17", "name": "RISC-V: Allow all vector modes during builtin registration. [PR124613]", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497602/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216475/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216475/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ibmd1xbr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; helo=vm01.sourceware.org;\n envelope-from=gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org;\n receiver=patchwork.ozlabs.org)", "sourceware.org;\n\tdkim=pass (2048-bit key,\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=ibmd1xbr", "sourceware.org;\n dmarc=pass (p=none dis=none) header.from=gmail.com", "sourceware.org; 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charset=UTF-8", "Date": "Thu, 26 Mar 2026 15:27:17 +0100", "Message-Id": "<DHCS8PTZ9DOD.DOKQ7ILVGVFW@gmail.com>", "Subject": "[PATCH] RISC-V: Allow all vector modes during builtin registration.\n [PR124613]", "Cc": "<kito.cheng@gmail.com>, <juzhe.zhong@rivai.ai>, <jeffreyalaw@gmail.com>,\n <pan2.li@intel.com>, <rdapp.gcc@gmail.com>", "To": "\"gcc-patches\" <gcc-patches@gcc.gnu.org>", "From": "\"Robin Dapp\" <rdapp.gcc@gmail.com>", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Hi,\n\nIn r16-7312-gecc37444062b40 we allowed all vector modes for the\nany_target hook. Since then we would ICE in gcc.target/riscv/pr122051.c\nas emit_move_multi_word would choose a fractional vector mode.\n\nThis patch disallows fractional vector modes for xtheadvector in\nriscv_vector_mode_supported_p but makes an exception for builtin\nregistration (through a global variable). During registration we\nneed to have all modes available in order to maintain the registration\norder for LTO streaming.\n\nRegtested on rv64gcv_zvl512b.\n\nRegards\n Robin\n\n\tPR target/124613\n\ngcc/ChangeLog:\n\n\t* config/riscv/riscv-vector-builtins.cc (rvv_switcher::rvv_switcher):\n\tAdd riscv_registering_builtins.\n\t(rvv_switcher::~rvv_switcher): Set riscv_registering_builtins to\n\tfalse.\n\t* config/riscv/riscv.cc (riscv_vector_mode_supported_p): Use\n\triscv_registering_builtins.\n\t* config/riscv/riscv.h: Declare.\n---\n gcc/config/riscv/riscv-vector-builtins.cc | 7 +++++++\n gcc/config/riscv/riscv.cc | 15 ++++++++++++++-\n gcc/config/riscv/riscv.h | 1 +\n 3 files changed, 22 insertions(+), 1 deletion(-)", "diff": "diff --git a/gcc/config/riscv/riscv-vector-builtins.cc b/gcc/config/riscv/riscv-vector-builtins.cc\nindex 92f343c0044..b3bce40e5bf 100644\n--- a/gcc/config/riscv/riscv-vector-builtins.cc\n+++ b/gcc/config/riscv/riscv-vector-builtins.cc\n@@ -3784,6 +3784,11 @@ rvv_switcher::rvv_switcher (bool pollute_flags)\n riscv_option_override ();\n }\n \n+ /* Allow all vector modes during builtin registration so that\n+ vector_mode_supported_p does not reject fractional LMUL modes\n+ for xtheadvector. */\n+ riscv_registering_builtins = true;\n+\n /* Set have_regs_of_mode before targetm.init_builtins (). */\n memcpy (m_old_have_regs_of_mode, have_regs_of_mode,\n \t sizeof (have_regs_of_mode));\n@@ -3803,6 +3808,8 @@ rvv_switcher::rvv_switcher (bool pollute_flags)\n \n rvv_switcher::~rvv_switcher ()\n {\n+ riscv_registering_builtins = false;\n+\n /* Recover back have_regs_of_mode. */\n memcpy (have_regs_of_mode, m_old_have_regs_of_mode,\n \t sizeof (have_regs_of_mode));\ndiff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc\nindex 67b94354c27..816b62236b8 100644\n--- a/gcc/config/riscv/riscv.cc\n+++ b/gcc/config/riscv/riscv.cc\n@@ -356,6 +356,9 @@ poly_uint16 riscv_vector_chunks;\n /* The number of bytes in a vector chunk. */\n unsigned riscv_bytes_per_vector_chunk;\n \n+/* Whether we are currently registering builtins. */\n+bool riscv_registering_builtins;\n+\n /* Index R is the smallest register class that contains register R. */\n const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = {\n GR_REGS,\tGR_REGS,\tGR_REGS,\tGR_REGS,\n@@ -13458,7 +13461,17 @@ static bool\n riscv_vector_mode_supported_p (machine_mode mode)\n {\n if (TARGET_VECTOR)\n- return riscv_vector_mode_p (mode);\n+ {\n+ /* Avoid fractional LMUL modes for xtheadvector with the exception\n+\t of builtin registration time. During registration, all modes\n+\t must be available so the order and numbering is consistent,\n+\t see PR123279. */\n+ if (TARGET_XTHEADVECTOR && !riscv_registering_builtins\n+\t && maybe_lt (GET_MODE_SIZE (mode), BYTES_PER_RISCV_VECTOR))\n+\treturn false;\n+\n+ return riscv_vector_mode_p (mode);\n+ }\n \n return false;\n }\ndiff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h\nindex 195012f216b..26e5e7cd64a 100644\n--- a/gcc/config/riscv/riscv.h\n+++ b/gcc/config/riscv/riscv.h\n@@ -1206,6 +1206,7 @@ extern bool riscv_user_wants_strict_align;\n extern unsigned riscv_stack_boundary;\n extern unsigned riscv_bytes_per_vector_chunk;\n extern poly_uint16 riscv_vector_chunks;\n+extern bool riscv_registering_builtins;\n extern poly_int64 riscv_v_adjust_nunits (enum machine_mode, int);\n extern poly_int64 riscv_v_adjust_nunits (machine_mode, bool, int, int);\n extern poly_int64 riscv_v_adjust_precision (enum machine_mode, int);\n", "prefixes": [] }