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GET /api/patches/2216467/?format=api
{ "id": 2216467, "url": "http://patchwork.ozlabs.org/api/patches/2216467/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326135855.2795149-7-thierry.reding@kernel.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326135855.2795149-7-thierry.reding@kernel.org>", "list_archive_url": null, "date": "2026-03-26T13:58:53", "name": "[v3,6/6] arm64: tegra: Add PCI controllers on Tegra264", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3e2fc4cd2f6f3d1e6492677c79cf76a61d4b8749", "submitter": { "id": 92481, "url": "http://patchwork.ozlabs.org/api/people/92481/?format=api", "name": "Thierry Reding", "email": "thierry.reding@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326135855.2795149-7-thierry.reding@kernel.org/mbox/", "series": [ { "id": 497593, "url": "http://patchwork.ozlabs.org/api/series/497593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497593", "date": "2026-03-26T13:58:47", "name": "PCI: tegra: Add Tegra264 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216467/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216467/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51188-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=qV/ozlqA;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.105.105.114; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-51188-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"qV/ozlqA\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org [172.105.105.114])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhQdv0wRJz1y1x\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 01:10:11 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id CFF2A3127A52\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 14:00:17 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 8205A30CD92;\n\tThu, 26 Mar 2026 13:59:15 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 5F18D303A32;\n\tThu, 26 Mar 2026 13:59:15 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id A4F82C116C6;\n\tThu, 26 Mar 2026 13:59:14 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774533555; cv=none;\n b=eZH/A7PL/8VTfHhUZOi6d6CxgX/Mg5YFaGpqRGA5ku34WvJYrGq4RkMuYrb2OJp0BS0r/r3YDS0grxaETDSEbybjzvFW30nEtU6/0U/5TvF9VtKzgSIXFbtnLzkIsqajf7q+znOdtBaB2c8bZkCyxmaip8wox6xcopzEBwOoebI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774533555; c=relaxed/simple;\n\tbh=dfUcI7HUQvDtnJBH0Hfn5HG5G42nCgckOL/wC8wmnmE=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=cN/BtmtgtaQHoqi39wguFk+enF6yJlfRoJt/sGu0gy8pRycAD1Rlm65z3b5UOsZSVSQuO4yswoornHmeZdMh+E/B2D5ne8kLG+8jZbHPO/0Ll1wvXV1L074AEliw0iSe7K1wSA+R28oBoCbLZAtmva4qZ0nW+wImlIQ5gKW1Bn8=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=qV/ozlqA; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774533555;\n\tbh=dfUcI7HUQvDtnJBH0Hfn5HG5G42nCgckOL/wC8wmnmE=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=qV/ozlqAZE+jswUk/rG2iLcwFaD/XwDkkc8oLZLiGtw5Xv2rdgZeL+oHvvlpdgr9A\n\t 5m9pEoUcq/r30mddB7QIRE1QoaE+7v6BEH4Z9DyOUl6X8wAjbrDkChg/8LCQcbW4+u\n\t xo+dn5UUa0YXd1WglUQp0gNyMdW9E1F0w+W8DCBzmN2W39+2KkFhs440GeUG4DNd1x\n\t 63/77hz+H3ahOWG4ltUQ/AX9czBRlKh0dm82wMR+oq3VdXebyZkd22o/S0j7zWMQfr\n\t D+TOwTGaT+rC7jJQ4n6krw0ufqTZKf22UyXuDnHYbZCGjNiT9AkK/F21+tawgrG4GB\n\t khAl+23hnqJ1Q==", "From": "Thierry Reding <thierry.reding@kernel.org>", "To": "Thierry Reding <thierry.reding@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>", "Cc": "Jon Hunter <jonathanh@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tlinux-pci@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org", "Subject": "[PATCH v3 6/6] arm64: tegra: Add PCI controllers on Tegra264", "Date": "Thu, 26 Mar 2026 14:58:53 +0100", "Message-ID": "<20260326135855.2795149-7-thierry.reding@kernel.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260326135855.2795149-1-thierry.reding@kernel.org>", "References": "<20260326135855.2795149-1-thierry.reding@kernel.org>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nA total of six PCIe controllers can be found on Tegra264. One of them is\nused internally for the integrated GPU while the other five can go to a\nvariety of connectors like full PCIe slots or M.2.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\nChanges in v2:\n- order ECAM \"reg\" entry before others\n\n arch/arm64/boot/dts/nvidia/tegra264.dtsi | 248 ++++++++++++++++++++---\n 1 file changed, 221 insertions(+), 27 deletions(-)", "diff": "diff --git a/arch/arm64/boot/dts/nvidia/tegra264.dtsi b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\nindex 7644a41d5f72..5214cec21204 100644\n--- a/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n+++ b/arch/arm64/boot/dts/nvidia/tegra264.dtsi\n@@ -32,7 +32,7 @@ bus@0 {\n \t\t#address-cells = <2>;\n \t\t#size-cells = <2>;\n \n-\t\tranges = <0x00 0x00000000 0x00 0x00000000 0x01 0x00000000>;\n+\t\tranges = <0x00 0x00000000 0x00 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */\n \n \t\tmisc@100000 {\n \t\t\tcompatible = \"nvidia,tegra234-misc\";\n@@ -3356,9 +3356,10 @@ bus@8100000000 {\n \t\t#address-cells = <2>;\n \t\t#size-cells = <2>;\n \n-\t\tranges = <0x00 0x00000000 0x81 0x00000000 0x01 0x00000000>, /* MMIO */\n-\t\t\t <0x01 0x00000000 0x00 0x20000000 0x00 0x40000000>, /* non-prefetchable memory (32-bit) */\n-\t\t\t <0x02 0x00000000 0xd0 0x00000000 0x08 0x80000000>; /* ECAM, prefetchable memory, I/O */\n+\t\tranges = <0x00 0x00000000 0x81 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */\n+\t\t\t <0x00 0x20000000 0x00 0x20000000 0x00 0x20000000>, /* non-prefetchable memory (32-bit, 512 MiB) */\n+\t\t\t <0x00 0x40000000 0x81 0x40000000 0x00 0x20000000>, /* MMIO (512 MiB) */\n+\t\t\t <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */\n \n \t\tsmmu1: iommu@5000000 {\n \t\t\tcompatible = \"nvidia,tegra264-smmu\", \"arm,smmu-v3\";\n@@ -3402,23 +3403,23 @@ cmdqv2: cmdqv@6200000 {\n \n \t\tmc: memory-controller@8020000 {\n \t\t\tcompatible = \"nvidia,tegra264-mc\";\n-\t\t\treg = <0x00 0x8020000 0x0 0x20000>, /* MC broadcast */\n-\t\t\t <0x00 0x8040000 0x0 0x20000>, /* MC 0 */\n-\t\t\t <0x00 0x8060000 0x0 0x20000>, /* MC 1 */\n-\t\t\t <0x00 0x8080000 0x0 0x20000>, /* MC 2 */\n-\t\t\t <0x00 0x80a0000 0x0 0x20000>, /* MC 3 */\n-\t\t\t <0x00 0x80c0000 0x0 0x20000>, /* MC 4 */\n-\t\t\t <0x00 0x80e0000 0x0 0x20000>, /* MC 5 */\n-\t\t\t <0x00 0x8100000 0x0 0x20000>, /* MC 6 */\n-\t\t\t <0x00 0x8120000 0x0 0x20000>, /* MC 7 */\n-\t\t\t <0x00 0x8140000 0x0 0x20000>, /* MC 8 */\n-\t\t\t <0x00 0x8160000 0x0 0x20000>, /* MC 9 */\n-\t\t\t <0x00 0x8180000 0x0 0x20000>, /* MC 10 */\n-\t\t\t <0x00 0x81a0000 0x0 0x20000>, /* MC 11 */\n-\t\t\t <0x00 0x81c0000 0x0 0x20000>, /* MC 12 */\n-\t\t\t <0x00 0x81e0000 0x0 0x20000>, /* MC 13 */\n-\t\t\t <0x00 0x8200000 0x0 0x20000>, /* MC 14 */\n-\t\t\t <0x00 0x8220000 0x0 0x20000>; /* MC 15 */\n+\t\t\treg = <0x000 0x8020000 0x0 0x20000>, /* MC broadcast */\n+\t\t\t <0x000 0x8040000 0x0 0x20000>, /* MC 0 */\n+\t\t\t <0x000 0x8060000 0x0 0x20000>, /* MC 1 */\n+\t\t\t <0x000 0x8080000 0x0 0x20000>, /* MC 2 */\n+\t\t\t <0x000 0x80a0000 0x0 0x20000>, /* MC 3 */\n+\t\t\t <0x000 0x80c0000 0x0 0x20000>, /* MC 4 */\n+\t\t\t <0x000 0x80e0000 0x0 0x20000>, /* MC 5 */\n+\t\t\t <0x000 0x8100000 0x0 0x20000>, /* MC 6 */\n+\t\t\t <0x000 0x8120000 0x0 0x20000>, /* MC 7 */\n+\t\t\t <0x000 0x8140000 0x0 0x20000>, /* MC 8 */\n+\t\t\t <0x000 0x8160000 0x0 0x20000>, /* MC 9 */\n+\t\t\t <0x000 0x8180000 0x0 0x20000>, /* MC 10 */\n+\t\t\t <0x000 0x81a0000 0x0 0x20000>, /* MC 11 */\n+\t\t\t <0x000 0x81c0000 0x0 0x20000>, /* MC 12 */\n+\t\t\t <0x000 0x81e0000 0x0 0x20000>, /* MC 13 */\n+\t\t\t <0x000 0x8200000 0x0 0x20000>, /* MC 14 */\n+\t\t\t <0x000 0x8220000 0x0 0x20000>; /* MC 15 */\n \t\t\treg-names = \"broadcast\", \"ch0\", \"ch1\", \"ch2\", \"ch3\",\n \t\t\t\t \"ch4\", \"ch5\", \"ch6\", \"ch7\", \"ch8\", \"ch9\",\n \t\t\t\t \"ch10\", \"ch11\", \"ch12\", \"ch13\", \"ch14\",\n@@ -3437,12 +3438,12 @@ mc: memory-controller@8020000 {\n \t\t\t#size-cells = <2>;\n \n \t\t\t/* limit the DMA range for memory clients to [39:0] */\n-\t\t\tdma-ranges = <0x0 0x0 0x0 0x0 0x100 0x0>;\n+\t\t\tdma-ranges = <0x000 0x0 0x000 0x0 0x100 0x0>;\n \n \t\t\temc: external-memory-controller@8800000 {\n \t\t\t\tcompatible = \"nvidia,tegra264-emc\";\n-\t\t\t\treg = <0x00 0x8800000 0x0 0x20000>,\n-\t\t\t\t <0x00 0x8890000 0x0 0x20000>;\n+\t\t\t\treg = <0x000 0x8800000 0x0 0x20000>,\n+\t\t\t\t <0x000 0x8890000 0x0 0x20000>;\n \t\t\t\tinterrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;\n \t\t\t\tclocks = <&bpmp TEGRA264_CLK_EMC>,\n \t\t\t\t\t <&bpmp TEGRA264_CLK_DBB_UPHY0>;\n@@ -3493,6 +3494,38 @@ cmdqv4: cmdqv@b200000 {\n \t\t\tstatus = \"disabled\";\n \t\t};\n \n+\t\tpci@c000000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pcie\";\n+\t\t\treg = <0xd0 0xb0000000 0x0 0x10000000>,\n+\t\t\t <0x00 0x0c000000 0x0 0x00004000>,\n+\t\t\t <0x00 0x0c004000 0x0 0x00001000>,\n+\t\t\t <0x00 0x0c005000 0x0 0x00001000>;\n+\t\t\treg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tlinux,pci-domain = <0x00>;\n+\t\t\t#interrupt-cells = <0x1>;\n+\n+\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t\t<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 IRQ_TYPE_LEVEL_HIGH>;\n+\n+\t\t\tiommu-map = <0x0 &smmu2 0x10000 0x10000>;\n+\t\t\tmsi-map = <0x0 &its 0x210000 0x10000>;\n+\t\t\tdma-coherent;\n+\n+\t\t\tranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>, /* I/O */\n+\t\t\t\t <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>, /* non-prefetchable memory (128 MiB) */\n+\t\t\t\t <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */\n+\t\t\tbus-range = <0x0 0xff>;\n+\n+\t\t\tnvidia,bpmp = <&bpmp 0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n \t\ti2c14: i2c@c410000 {\n \t\t\tcompatible = \"nvidia,tegra264-i2c\";\n \t\t\treg = <0x00 0x0c410000 0x0 0x10000>;\n@@ -3720,7 +3753,7 @@ bus@8800000000 {\n \t\t#address-cells = <2>;\n \t\t#size-cells = <2>;\n \n-\t\tranges = <0x00 0x00000000 0x88 0x00000000 0x01 0x00000000>;\n+\t\tranges = <0x00 0x00000000 0x88 0x00000000 0x00 0x20000000>; /* MMIO (512 MiB) */\n \n \t\tsmmu3: iommu@6000000 {\n \t\t\tcompatible = \"nvidia,tegra264-smmu\", \"arm,smmu-v3\";\n@@ -3765,8 +3798,169 @@ bus@a800000000 {\n \t\t#address-cells = <2>;\n \t\t#size-cells = <2>;\n \n-\t\tranges = <0x00 0x00000000 0xa8 0x00000000 0x40 0x00000000>, /* MMIO, ECAM, prefetchable memory, I/O */\n-\t\t\t <0x80 0x00000000 0x00 0x20000000 0x00 0x40000000>; /* non-prefetchable memory (32-bit) */\n+\t\tranges = <0x00 0x00000000 0xa8 0x00000000 0x00 0x20000000>, /* MMIO (512 MiB) */\n+\t\t\t <0x00 0x20000000 0x00 0x20000000 0x00 0x60000000>, /* non-prefetchable memory (32-bit, 1536 GiB) */\n+\t\t\t <0xa8 0x80000000 0xa8 0x80000000 0x57 0x80000000>; /* I/O, ECAM, prefetchable memory (64-bit) */\n+\n+\t\tpci@8400000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pcie\";\n+\t\t\treg = <0xa8 0xb0000000 0x0 0x10000000>,\n+\t\t\t <0x00 0x08400000 0x0 0x00004000>,\n+\t\t\t <0x00 0x08404000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08405000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08410000 0x0 0x00010000>;\n+\t\t\treg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\", \"xpl\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tlinux,pci-domain = <0x01>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 IRQ_TYPE_LEVEL_HIGH>, /* INTA */\n+\t\t\t\t\t<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 IRQ_TYPE_LEVEL_HIGH>, /* INTB */\n+\t\t\t\t\t<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 IRQ_TYPE_LEVEL_HIGH>, /* INTC */\n+\t\t\t\t\t<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 IRQ_TYPE_LEVEL_HIGH>; /* INTD */\n+\n+\t\t\tiommu-map = <0x0 &smmu1 0x10000 0x10000>;\n+\t\t\tmsi-map = <0x0 &its 0x110000 0x10000>;\n+\t\t\tdma-coherent;\n+\n+\t\t\tranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>, /* I/O */\n+\t\t\t\t <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>, /* non-prefetchable memory */\n+\t\t\t\t <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */\n+\t\t\tbus-range = <0x00 0xff>;\n+\n+\t\t\tnvidia,bpmp = <&bpmp 1>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpci@8420000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pcie\";\n+\t\t\treg = <0xb0 0xb0000000 0x0 0x10000000>,\n+\t\t\t <0x00 0x08420000 0x0 0x00004000>,\n+\t\t\t <0x00 0x08424000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08425000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08430000 0x0 0x00010000>;\n+\t\t\treg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\", \"xpl\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tlinux,pci-domain = <0x02>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 917 IRQ_TYPE_LEVEL_HIGH>, /* INTA */\n+\t\t\t\t\t<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 918 IRQ_TYPE_LEVEL_HIGH>, /* INTB */\n+\t\t\t\t\t<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 919 IRQ_TYPE_LEVEL_HIGH>, /* INTC */\n+\t\t\t\t\t<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 920 IRQ_TYPE_LEVEL_HIGH>; /* INTD */\n+\n+\t\t\tiommu-map = <0x0 &smmu1 0x20000 0x10000>;\n+\t\t\tmsi-map = <0x0 &its 0x120000 0x10000>;\n+\t\t\tdma-coherent;\n+\n+\t\t\tranges = <0x81000000 0x00 0x84000000 0xb0 0x84000000 0x00 0x00200000>, /* I/O */\n+\t\t\t\t <0x82000000 0x00 0x30000000 0x00 0x30000000 0x00 0x08000000>, /* non-prefetchable memory */\n+\t\t\t\t <0xc3000000 0xb0 0xc0000000 0xb0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */\n+\t\t\tbus-range = <0x00 0xff>;\n+\n+\t\t\tnvidia,bpmp = <&bpmp 2>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpci@8440000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pcie\";\n+\t\t\treg = <0xb8 0xb0000000 0x0 0x10000000>,\n+\t\t\t <0x00 0x08440000 0x0 0x00004000>,\n+\t\t\t <0x00 0x08444000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08445000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08450000 0x0 0x00010000>;\n+\t\t\treg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\", \"xpl\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tlinux,pci-domain = <0x03>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 926 IRQ_TYPE_LEVEL_HIGH>, /* INTA */\n+\t\t\t\t\t<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 927 IRQ_TYPE_LEVEL_HIGH>, /* INTB */\n+\t\t\t\t\t<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 928 IRQ_TYPE_LEVEL_HIGH>, /* INTC */\n+\t\t\t\t\t<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 929 IRQ_TYPE_LEVEL_HIGH>; /* INTD */\n+\n+\t\t\tiommu-map = <0x0 &smmu1 0x30000 0x10000>;\n+\t\t\tmsi-map = <0x0 &its 0x130000 0x10000>;\n+\t\t\tdma-coherent;\n+\n+\t\t\tranges = <0x81000000 0x00 0x84000000 0xb8 0x84000000 0x00 0x00200000>, /* I/O */\n+\t\t\t\t <0x82000000 0x00 0x38000000 0x00 0x38000000 0x00 0x08000000>, /* non-prefetchable memory */\n+\t\t\t\t <0xc3000000 0xb8 0xc0000000 0xb8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */\n+\t\t\tbus-range = <0x00 0xff>;\n+\n+\t\t\tnvidia,bpmp = <&bpmp 3>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpci@8460000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pcie\";\n+\t\t\treg = <0xc0 0xb0000000 0x0 0x10000000>,\n+\t\t\t <0x00 0x08460000 0x0 0x00004000>,\n+\t\t\t <0x00 0x08464000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08465000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08470000 0x0 0x00010000>;\n+\t\t\treg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\", \"xpl\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tlinux,pci-domain = <0x04>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 935 IRQ_TYPE_LEVEL_HIGH>, /* INTA */\n+\t\t\t\t\t<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 936 IRQ_TYPE_LEVEL_HIGH>, /* INTB */\n+\t\t\t\t\t<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 937 IRQ_TYPE_LEVEL_HIGH>, /* INTC */\n+\t\t\t\t\t<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 938 IRQ_TYPE_LEVEL_HIGH>; /* INTD */\n+\n+\t\t\tiommu-map = <0x0 &smmu1 0x40000 0x10000>;\n+\t\t\tmsi-map = <0x0 &its 0x140000 0x10000>;\n+\t\t\tdma-coherent;\n+\n+\t\t\tranges = <0x81000000 0x00 0x84000000 0xc0 0x84000000 0x00 0x00200000>, /* I/O */\n+\t\t\t\t <0x82000000 0x00 0x40000000 0x00 0x40000000 0x00 0x08000000>, /* non-prefetchable memory */\n+\t\t\t\t <0xc3000000 0xc0 0xc0000000 0xc0 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */\n+\t\t\tbus-range = <0x00 0xff>;\n+\n+\t\t\tnvidia,bpmp = <&bpmp 4>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tpci@8480000 {\n+\t\t\tcompatible = \"nvidia,tegra264-pcie\";\n+\t\t\treg = <0xc8 0xb0000000 0x0 0x10000000>,\n+\t\t\t <0x00 0x08480000 0x0 0x00004000>,\n+\t\t\t <0x00 0x08484000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08485000 0x0 0x00001000>,\n+\t\t\t <0x00 0x08490000 0x0 0x00010000>;\n+\t\t\treg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\", \"xpl\";\n+\t\t\t#address-cells = <3>;\n+\t\t\t#size-cells = <2>;\n+\t\t\tdevice_type = \"pci\";\n+\t\t\tlinux,pci-domain = <0x05>;\n+\t\t\t#interrupt-cells = <1>;\n+\t\t\tinterrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+\t\t\tinterrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 944 IRQ_TYPE_LEVEL_HIGH>, /* INTA */\n+\t\t\t\t\t<0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 945 IRQ_TYPE_LEVEL_HIGH>, /* INTB */\n+\t\t\t\t\t<0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 946 IRQ_TYPE_LEVEL_HIGH>, /* INTC */\n+\t\t\t\t\t<0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 947 IRQ_TYPE_LEVEL_HIGH>; /* INTD */\n+\n+\t\t\tiommu-map = <0x0 &smmu1 0x50000 0x10000>;\n+\t\t\tmsi-map = <0x0 &its 0x150000 0x10000>;\n+\t\t\tdma-coherent;\n+\n+\t\t\tranges = <0x81000000 0x00 0x84000000 0xc8 0x84000000 0x00 0x00200000>, /* I/O */\n+\t\t\t\t <0x82000000 0x00 0x48000000 0x00 0x48000000 0x00 0x08000000>, /* non-prefetchable memory */\n+\t\t\t\t <0xc3000000 0xc8 0xc0000000 0xc8 0xc0000000 0x07 0xc0000000>; /* prefetchable memory */\n+\t\t\tbus-range = <0x00 0xff>;\n+\n+\t\t\tnvidia,bpmp = <&bpmp 5>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n \t};\n \n \tcpus {\n", "prefixes": [ "v3", "6/6" ] }