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GET /api/patches/2216459/?format=api
{ "id": 2216459, "url": "http://patchwork.ozlabs.org/api/patches/2216459/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260326135855.2795149-4-thierry.reding@kernel.org/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326135855.2795149-4-thierry.reding@kernel.org>", "list_archive_url": null, "date": "2026-03-26T13:58:50", "name": "[v3,3/6] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "4d5c3540f8fbf837ba529f6014dc455a849fe660", "submitter": { "id": 92481, "url": "http://patchwork.ozlabs.org/api/people/92481/?format=api", "name": "Thierry Reding", "email": "thierry.reding@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260326135855.2795149-4-thierry.reding@kernel.org/mbox/", "series": [ { "id": 497592, "url": "http://patchwork.ozlabs.org/api/series/497592/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497592", "date": "2026-03-26T13:58:48", "name": "PCI: tegra: Add Tegra264 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497592/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216459/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216459/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13300-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=pmQfGA8/;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774533547; cv=none;\n b=RMvgD4Sr/mwARiiUfR9vO251n5kI+61ic8UVFlyR4McU190KC33MuLsmydmh+H+mpcOIf6QvZCHE9bpGVZ6icLIZCUbr9YGS+MkrVZY4pg/LroAhjMMcl+VQkZZG7C+FBzidHBCeVHa01/Drwar3KaYXvwME9XvWeDUdBamjlmA=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774533547; c=relaxed/simple;\n\tbh=g/QXgYjycoQKeBbIj4twn3/5eg0y/v9nZ4xct8i23dU=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=Gl9uIsmm/LjkvnhRn4RgnnSCGk30pg8mSBpN+kjofobUhF1R1ETVS1+v8gBcb3Lmsn7avO0JwG0arExpVbibeByQyZ5GEOn3Z12y/PczASKPupJa8aYdZmsyTN0GJBqCZ8rv9+OJLwu/llNAvlw0caCBp7n7V0iDJb/uWYGXzBU=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=pmQfGA8/; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774533547;\n\tbh=g/QXgYjycoQKeBbIj4twn3/5eg0y/v9nZ4xct8i23dU=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=pmQfGA8/csYDnBVobNMKbqRhPmHM7Qnv2t5z49LLcZ9Txu4qE3tkx0ypLhTySXRfj\n\t Tn0ok1fwlghT7sLnOyzejV+ieNjD4NjdpKyp0w0qdIP4Bj2kZrlqmcYjoqm9lP5bPB\n\t aMc+gu0guNtL76mhd/PBpl7wy4neI0HV78iyj9MdM85kUt8H5TP1XlXOidgREIoOgs\n\t 4w2P7/psyys9/k9lBT/cMbsNzMdMVW1rpQF0n/opHQ0/MUmz9YKX5yAU27LsGA0ygQ\n\t JCtjHzr+9JwMLf8UyX5gOX66keO7GJ1FVvvIfbL09/McQ/8YMpQczTq2/NYB41ePuN\n\t bypR5tEEzS07g==", "From": "Thierry Reding <thierry.reding@kernel.org>", "To": "Thierry Reding <thierry.reding@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>", "Cc": "Jon Hunter <jonathanh@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tlinux-pci@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org", "Subject": "[PATCH v3 3/6] dt-bindings: pci: Document the NVIDIA Tegra264 PCIe\n controller", "Date": "Thu, 26 Mar 2026 14:58:50 +0100", "Message-ID": "<20260326135855.2795149-4-thierry.reding@kernel.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260326135855.2795149-1-thierry.reding@kernel.org>", "References": "<20260326135855.2795149-1-thierry.reding@kernel.org>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nThe six PCIe controllers found on Tegra264 are of two types: one is used\nfor the internal GPU and therefore is not connected to a UPHY and the\nremaining five controllers are typically routed to a PCI slot and have\nadditional controls for the physical link.\n\nWhile these controllers can be switched into endpoint mode, this binding\ndescribes the root complex mode only.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\nChanges in v2:\n- move ECAM region first and unify C0 vs. C1-C5\n- move unevaluatedProperties to right before the examples\n- add description to clarify the two types of controllers\n- add examples for C0 and C1-C5\n\n .../bindings/pci/nvidia,tegra264-pcie.yaml | 149 ++++++++++++++++++\n 1 file changed, 149 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml\nnew file mode 100644\nindex 000000000000..dc4f8725c9f5\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra264-pcie.yaml\n@@ -0,0 +1,149 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/nvidia,tegra264-pcie.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: NVIDIA Tegra264 PCIe controller\n+\n+maintainers:\n+ - Thierry Reding <thierry.reding@gmail.com>\n+ - Jon Hunter <jonathanh@nvidia.com>\n+\n+properties:\n+ compatible:\n+ const: nvidia,tegra264-pcie\n+\n+ reg:\n+ description: |\n+ Of the six PCIe controllers found on Tegra264, one (C0) is used for the\n+ internal GPU and the other five (C1-C5) are routed to connectors such as\n+ PCI or M.2 slots. Therefore the UPHY registers (XPL) exist only for C1\n+ through C5, but not for C0.\n+ minItems: 4\n+ items:\n+ - description: ECAM-compatible configuration space\n+ - description: application layer registers\n+ - description: transaction layer registers\n+ - description: privileged transaction layer registers\n+ - description: data link/physical layer registers (not available on C0)\n+\n+ reg-names:\n+ minItems: 4\n+ items:\n+ - const: ecam\n+ - const: xal\n+ - const: xtl\n+ - const: xtl-pri\n+ - const: xpl\n+\n+ interrupts:\n+ minItems: 1\n+ maxItems: 4\n+\n+ dma-coherent: true\n+\n+ nvidia,bpmp:\n+ $ref: /schemas/types.yaml#/definitions/phandle-array\n+ description: |\n+ Must contain a pair of phandle (to the BPMP controller node) and\n+ controller ID. The following are the controller IDs for each controller:\n+\n+ 0: C0\n+ 1: C1\n+ 2: C2\n+ 3: C3\n+ 4: C4\n+ 5: C5\n+ items:\n+ - items:\n+ - description: phandle to the BPMP controller node\n+ - description: PCIe controller ID\n+ maximum: 5\n+\n+required:\n+ - interrupt-map\n+ - interrupt-map-mask\n+ - iommu-map\n+ - msi-map\n+ - nvidia,bpmp\n+\n+allOf:\n+ - $ref: /schemas/pci/pci-host-bridge.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pci@c000000 {\n+ compatible = \"nvidia,tegra264-pcie\";\n+ reg = <0xd0 0xb0000000 0x0 0x10000000>,\n+ <0x00 0x0c000000 0x0 0x00004000>,\n+ <0x00 0x0c004000 0x0 0x00001000>,\n+ <0x00 0x0c005000 0x0 0x00001000>;\n+ reg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\";\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ device_type = \"pci\";\n+ linux,pci-domain = <0x00>;\n+ #interrupt-cells = <0x1>;\n+\n+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 155 4>,\n+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 156 4>,\n+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 157 4>,\n+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 158 4>;\n+\n+ iommu-map = <0x0 &smmu2 0x10000 0x10000>;\n+ msi-map = <0x0 &its 0x210000 0x10000>;\n+ dma-coherent;\n+\n+ ranges = <0x81000000 0x00 0x84000000 0xd0 0x84000000 0x00 0x00200000>,\n+ <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x08000000>,\n+ <0xc3000000 0xd0 0xc0000000 0xd0 0xc0000000 0x07 0xc0000000>;\n+ bus-range = <0x0 0xff>;\n+\n+ nvidia,bpmp = <&bpmp 0>;\n+ };\n+ };\n+\n+ - |\n+ bus {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pci@8400000 {\n+ compatible = \"nvidia,tegra264-pcie\";\n+ reg = <0xa8 0xb0000000 0x0 0x10000000>,\n+ <0x00 0x08400000 0x0 0x00004000>,\n+ <0x00 0x08404000 0x0 0x00001000>,\n+ <0x00 0x08405000 0x0 0x00001000>,\n+ <0x00 0x08410000 0x0 0x00010000>;\n+ reg-names = \"ecam\", \"xal\", \"xtl\", \"xtl-pri\", \"xpl\";\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ device_type = \"pci\";\n+ linux,pci-domain = <0x01>;\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0x0 0x0 0x0 0x7>;\n+ interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0x0 0x0 908 4>,\n+ <0x0 0x0 0x0 0x2 &gic 0x0 0x0 0x0 909 4>,\n+ <0x0 0x0 0x0 0x3 &gic 0x0 0x0 0x0 910 4>,\n+ <0x0 0x0 0x0 0x4 &gic 0x0 0x0 0x0 911 4>;\n+\n+ iommu-map = <0x0 &smmu1 0x10000 0x10000>;\n+ msi-map = <0x0 &its 0x110000 0x10000>;\n+ dma-coherent;\n+\n+ ranges = <0x81000000 0x00 0x84000000 0xa8 0x84000000 0x00 0x00200000>,\n+ <0x82000000 0x00 0x28000000 0x00 0x28000000 0x00 0x08000000>,\n+ <0xc3000000 0xa8 0xc0000000 0xa8 0xc0000000 0x07 0xc0000000>;\n+ bus-range = <0x00 0xff>;\n+\n+ nvidia,bpmp = <&bpmp 1>;\n+ };\n+ };\n", "prefixes": [ "v3", "3/6" ] }