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GET /api/patches/2216457/?format=api
{ "id": 2216457, "url": "http://patchwork.ozlabs.org/api/patches/2216457/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326135855.2795149-5-thierry.reding@kernel.org/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326135855.2795149-5-thierry.reding@kernel.org>", "list_archive_url": null, "date": "2026-03-26T13:58:51", "name": "[v3,4/6] PCI: Use standard wait times for PCIe link monitoring", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "c718764f791e6c54805fd259ecbc2fb39608a7fd", "submitter": { "id": 92481, "url": "http://patchwork.ozlabs.org/api/people/92481/?format=api", "name": "Thierry Reding", "email": "thierry.reding@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326135855.2795149-5-thierry.reding@kernel.org/mbox/", "series": [ { "id": 497593, "url": "http://patchwork.ozlabs.org/api/series/497593/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497593", "date": "2026-03-26T13:58:47", "name": "PCI: tegra: Add Tegra264 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497593/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216457/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216457/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51186-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ZTwI0D4g;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; helo=sto.lore.kernel.org;\n envelope-from=linux-pci+bounces-51186-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"ZTwI0D4g\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from sto.lore.kernel.org (sto.lore.kernel.org [172.232.135.74])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhQWf0f2Lz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 27 Mar 2026 01:04:46 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sto.lore.kernel.org (Postfix) with ESMTP id 7E3E1309DB14\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 14:00:12 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 35A06308F38;\n\tThu, 26 Mar 2026 13:59:10 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 103B32DB78C;\n\tThu, 26 Mar 2026 13:59:09 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPSA id 6574AC116C6;\n\tThu, 26 Mar 2026 13:59:09 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774533550; cv=none;\n b=qzkvko7vI8Pxf+C/PAmXTZB9sSuYbezOO2VCOg7NXphlN7SCQAdPDMTWLTYEc3UUOqYskVmVE1oxStrzx1SQvuUAOkxip1ctDX62j1itW4j2tqWV+XwZAjYIElYRVTMEMPCQaKJc00T4KnXhx2Lcz/yh4HyQsFpbnnxeRPCjcbg=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774533550; c=relaxed/simple;\n\tbh=F7wtKERyAW10tVzrR2NShbHmK35CspKk2rWys/MAvP4=;\n\th=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References:\n\t MIME-Version;\n b=WbAYY/J8U2iu6Pnqaz04ZT0Dtx4hrSTjTYlCJ0++omhX00oFmnWxo+lKuLmZ6cfzMSODVsJIt+6fFFzy1tj+TEBOT6pB+jOgwcayYW4c/zGhv0Cl49s2QBilno7Phe/yFVjLrfH6ppu/novojj+0uzf1Zsa4b0CBdFvQpHFeEz4=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=ZTwI0D4g; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774533549;\n\tbh=F7wtKERyAW10tVzrR2NShbHmK35CspKk2rWys/MAvP4=;\n\th=From:To:Cc:Subject:Date:In-Reply-To:References:From;\n\tb=ZTwI0D4gaMk3CPkFfyJKYilKxxsgDrRdBlQF46Et72XBkNcUH+SvcHPgHQYirGB29\n\t 449jFIk6UzqZMf7mJUbsc/av5GkCo9BD57eDqjx0HFrQ4DgPS8pyqh7ZESOO8evpZQ\n\t z0ZDhRgTo5vWzcAXzzdvvBWwGdPIvGQaqUrSrkx9ma8pjlKzDzeQ+SXHwDUCpJtSZZ\n\t yI2szP0UBnFU/u1iWaYELmuJOz1XUGAqRFRHiSOiV5VdM/JBrv6oW9rwzNJRUzEUFc\n\t CHCTprsoOyFCbkX8xsKP+QTvY+lWQJY78a/pysxi3femfZE5xzluK4rVZxFxNGtMLl\n\t 51BgmQ7nOnIFw==", "From": "Thierry Reding <thierry.reding@kernel.org>", "To": "Thierry Reding <thierry.reding@kernel.org>,\n Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>", "Cc": "Jon Hunter <jonathanh@nvidia.com>,\n\tMikko Perttunen <mperttunen@nvidia.com>,\n\tlinux-pci@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-tegra@vger.kernel.org", "Subject": "[PATCH v3 4/6] PCI: Use standard wait times for PCIe link monitoring", "Date": "Thu, 26 Mar 2026 14:58:51 +0100", "Message-ID": "<20260326135855.2795149-5-thierry.reding@kernel.org>", "X-Mailer": "git-send-email 2.52.0", "In-Reply-To": "<20260326135855.2795149-1-thierry.reding@kernel.org>", "References": "<20260326135855.2795149-1-thierry.reding@kernel.org>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit" }, "content": "From: Thierry Reding <treding@nvidia.com>\n\nInstead of defining the wait values for each driver, use common values\ndefined in the core pci.h header file. Note that most drivers don't use\nthe millisecond waits, but rather usleep_range(), so add these commonly\nused values to the header so that all drivers can use them.\n\nSigned-off-by: Thierry Reding <treding@nvidia.com>\n---\nChanges in v2:\n- fix build for Cadence\n\n .../pci/controller/cadence/pcie-cadence-host-common.c | 6 ++++--\n drivers/pci/controller/cadence/pcie-cadence-lga-regs.h | 5 -----\n drivers/pci/controller/mobiveil/pcie-mobiveil.c | 4 ++--\n drivers/pci/controller/mobiveil/pcie-mobiveil.h | 5 -----\n drivers/pci/controller/pci-aardvark.c | 7 ++-----\n drivers/pci/controller/pcie-xilinx-nwl.c | 9 ++-------\n drivers/pci/controller/plda/pcie-starfive.c | 9 ++-------\n drivers/pci/pci.h | 2 ++\n 8 files changed, 14 insertions(+), 33 deletions(-)", "diff": "diff --git a/drivers/pci/controller/cadence/pcie-cadence-host-common.c b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\nindex 2b0211870f02..72b36c70f389 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n+++ b/drivers/pci/controller/cadence/pcie-cadence-host-common.c\n@@ -15,6 +15,8 @@\n #include \"pcie-cadence.h\"\n #include \"pcie-cadence-host-common.h\"\n \n+#include \"../../pci.h\"\n+\n #define LINK_RETRAIN_TIMEOUT HZ\n \n u64 bar_max_size[] = {\n@@ -53,12 +55,12 @@ int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie,\n \tint retries;\n \n \t/* Check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (pcie_link_up(pcie)) {\n \t\t\tdev_info(dev, \"Link up\\n\");\n \t\t\treturn 0;\n \t\t}\n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \treturn -ETIMEDOUT;\ndiff --git a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\nindex 857b2140c5d2..15dc4fcaf45d 100644\n--- a/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\n+++ b/drivers/pci/controller/cadence/pcie-cadence-lga-regs.h\n@@ -10,11 +10,6 @@\n \n #include <linux/bitfield.h>\n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES\t10\n-#define LINK_WAIT_USLEEP_MIN\t90000\n-#define LINK_WAIT_USLEEP_MAX\t100000\n-\n /* Local Management Registers */\n #define CDNS_PCIE_LM_BASE\t0x00100000\n \ndiff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.c b/drivers/pci/controller/mobiveil/pcie-mobiveil.c\nindex 62ecbaeb0a60..cc102032c1e6 100644\n--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.c\n+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.c\n@@ -218,11 +218,11 @@ int mobiveil_bringup_link(struct mobiveil_pcie *pcie)\n \tint retries;\n \n \t/* check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (mobiveil_pcie_link_up(pcie))\n \t\t\treturn 0;\n \n-\t\tusleep_range(LINK_WAIT_MIN, LINK_WAIT_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \tdev_err(&pcie->pdev->dev, \"link never came up\\n\");\ndiff --git a/drivers/pci/controller/mobiveil/pcie-mobiveil.h b/drivers/pci/controller/mobiveil/pcie-mobiveil.h\nindex 7246de6a7176..11010a99e27c 100644\n--- a/drivers/pci/controller/mobiveil/pcie-mobiveil.h\n+++ b/drivers/pci/controller/mobiveil/pcie-mobiveil.h\n@@ -122,11 +122,6 @@\n #define IB_WIN_SIZE\t\t\t((u64)256 * 1024 * 1024 * 1024)\n #define MAX_PIO_WINDOWS\t\t\t8\n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES\t\t10\n-#define LINK_WAIT_MIN\t\t\t90000\n-#define LINK_WAIT_MAX\t\t\t100000\n-\n #define PAGED_ADDR_BNDRY\t\t0xc00\n #define OFFSET_TO_PAGE_ADDR(off)\t\\\n \t((off & PAGE_LO_MASK) | PAGED_ADDR_BNDRY)\ndiff --git a/drivers/pci/controller/pci-aardvark.c b/drivers/pci/controller/pci-aardvark.c\nindex e34bea1ff0ac..506323a6c72b 100644\n--- a/drivers/pci/controller/pci-aardvark.c\n+++ b/drivers/pci/controller/pci-aardvark.c\n@@ -255,9 +255,6 @@ enum {\n #define PIO_RETRY_CNT\t\t\t750000 /* 1.5 s */\n #define PIO_RETRY_DELAY\t\t\t2 /* 2 us*/\n \n-#define LINK_WAIT_MAX_RETRIES\t\t10\n-#define LINK_WAIT_USLEEP_MIN\t\t90000\n-#define LINK_WAIT_USLEEP_MAX\t\t100000\n #define RETRAIN_WAIT_MAX_RETRIES\t10\n #define RETRAIN_WAIT_USLEEP_US\t\t2000\n \n@@ -349,11 +346,11 @@ static int advk_pcie_wait_for_link(struct advk_pcie *pcie)\n \tint retries;\n \n \t/* check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (advk_pcie_link_up(pcie))\n \t\t\treturn 0;\n \n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \treturn -ETIMEDOUT;\ndiff --git a/drivers/pci/controller/pcie-xilinx-nwl.c b/drivers/pci/controller/pcie-xilinx-nwl.c\nindex 7db2c96c6cec..fc65e9fdddb3 100644\n--- a/drivers/pci/controller/pcie-xilinx-nwl.c\n+++ b/drivers/pci/controller/pcie-xilinx-nwl.c\n@@ -140,11 +140,6 @@\n #define PCIE_PHY_LINKUP_BIT\t\tBIT(0)\n #define PHY_RDY_LINKUP_BIT\t\tBIT(1)\n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES 10\n-#define LINK_WAIT_USLEEP_MIN 90000\n-#define LINK_WAIT_USLEEP_MAX 100000\n-\n struct nwl_msi {\t\t\t/* MSI information */\n \tDECLARE_BITMAP(bitmap, INT_PCI_MSI_NR);\n \tstruct irq_domain *dev_domain;\n@@ -203,10 +198,10 @@ static int nwl_wait_for_link(struct nwl_pcie *pcie)\n \tint retries;\n \n \t/* check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (nwl_phy_link_up(pcie))\n \t\t\treturn 0;\n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \tdev_err(dev, \"PHY link never came up\\n\");\ndiff --git a/drivers/pci/controller/plda/pcie-starfive.c b/drivers/pci/controller/plda/pcie-starfive.c\nindex 298036c3e7f9..542a751b6f4d 100644\n--- a/drivers/pci/controller/plda/pcie-starfive.c\n+++ b/drivers/pci/controller/plda/pcie-starfive.c\n@@ -45,11 +45,6 @@\n #define STG_SYSCON_LNKSTA_OFFSET\t\t0x170\n #define DATA_LINK_ACTIVE\t\t\tBIT(5)\n \n-/* Parameters for the waiting for link up routine */\n-#define LINK_WAIT_MAX_RETRIES\t10\n-#define LINK_WAIT_USLEEP_MIN\t90000\n-#define LINK_WAIT_USLEEP_MAX\t100000\n-\n struct starfive_jh7110_pcie {\n \tstruct plda_pcie_rp plda;\n \tstruct reset_control *resets;\n@@ -217,12 +212,12 @@ static int starfive_pcie_host_wait_for_link(struct starfive_jh7110_pcie *pcie)\n \tint retries;\n \n \t/* Check if the link is up or not */\n-\tfor (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {\n+\tfor (retries = 0; retries < PCIE_LINK_WAIT_MAX_RETRIES; retries++) {\n \t\tif (starfive_pcie_link_up(&pcie->plda)) {\n \t\t\tdev_info(pcie->plda.dev, \"port link up\\n\");\n \t\t\treturn 0;\n \t\t}\n-\t\tusleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);\n+\t\tusleep_range(PCIE_LINK_WAIT_US_MIN, PCIE_LINK_WAIT_US_MAX);\n \t}\n \n \treturn -ETIMEDOUT;\ndiff --git a/drivers/pci/pci.h b/drivers/pci/pci.h\nindex e542d1bf2853..0ca1c159b458 100644\n--- a/drivers/pci/pci.h\n+++ b/drivers/pci/pci.h\n@@ -63,6 +63,8 @@ struct pcie_tlp_log;\n /* Parameters for the waiting for link up routine */\n #define PCIE_LINK_WAIT_MAX_RETRIES\t10\n #define PCIE_LINK_WAIT_SLEEP_MS\t\t90\n+#define PCIE_LINK_WAIT_US_MIN\t\t90000\n+#define PCIE_LINK_WAIT_US_MAX\t\t100000\n \n /* Format of TLP; PCIe r7.0, sec 2.2.1 */\n #define PCIE_TLP_FMT_3DW_NO_DATA\t0x00 /* 3DW header, no data */\n", "prefixes": [ "v3", "4/6" ] }