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{
    "id": 2216449,
    "url": "http://patchwork.ozlabs.org/api/patches/2216449/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-12-robert.marko@sartura.hr/",
    "project": {
        "id": 18,
        "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api",
        "name": "U-Boot",
        "link_name": "uboot",
        "list_id": "u-boot.lists.denx.de",
        "list_email": "u-boot@lists.denx.de",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260326112830.313874-12-robert.marko@sartura.hr>",
    "list_archive_url": null,
    "date": "2026-03-26T11:26:53",
    "name": "[12/14] net: add Microchip SparX-5 and LAN969x support",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "e870db6d7e7a4fa49ed9dcd02cc6e53c0135d0b1",
    "submitter": {
        "id": 78207,
        "url": "http://patchwork.ozlabs.org/api/people/78207/?format=api",
        "name": "Robert Marko",
        "email": "robert.marko@sartura.hr"
    },
    "delegate": {
        "id": 3651,
        "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api",
        "username": "trini",
        "first_name": "Tom",
        "last_name": "Rini",
        "email": "trini@ti.com"
    },
    "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-12-robert.marko@sartura.hr/mbox/",
    "series": [
        {
            "id": 497572,
            "url": "http://patchwork.ozlabs.org/api/series/497572/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497572",
            "date": "2026-03-26T11:26:42",
            "name": "[01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/497572/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2216449/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2216449/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Robert Marko <robert.marko@sartura.hr>",
        "To": "u-boot@lists.denx.de, trini@konsulko.com, lukma@denx.de, hs@nabladev.com,\n peng.fan@nxp.com, jh80.chung@samsung.com, gregory.clement@bootlin.com,\n lars.povlsen@microchip.com, horatiu.vultur@microchip.com,\n jerome.forissier@arm.com, marex@denx.de, daniel.machon@microchip.com",
        "Cc": "luka.perkov@sartura.hr,\n\tRobert Marko <robert.marko@sartura.hr>",
        "Subject": "[PATCH 12/14] net: add Microchip SparX-5 and LAN969x support",
        "Date": "Thu, 26 Mar 2026 12:26:53 +0100",
        "Message-ID": "<20260326112830.313874-12-robert.marko@sartura.hr>",
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    "content": "Add support for Microchip SparX-5 and LAN969x networking.\nCurrently, only the \"management\" ports via RGMII are supported.\n\nDriver is imported from Microchip BSP U-Boot[1] but updated to use\nDM_MDIO, modernised parsing of DT properties, PHY connections etc.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/net/mscc_eswitch/Kconfig              |    7 +\n drivers/net/mscc_eswitch/Makefile             |    1 +\n drivers/net/mscc_eswitch/sparx5_reg_offset.c  |  353 ++\n drivers/net/mscc_eswitch/sparx5_reg_offset.h  |  201 ++\n drivers/net/mscc_eswitch/sparx5_regs.h        |  701 ++++\n drivers/net/mscc_eswitch/sparx5_serdes.c      | 2703 +++++++++++++++\n drivers/net/mscc_eswitch/sparx5_serdes.h      |   69 +\n drivers/net/mscc_eswitch/sparx5_serdes_priv.h |  130 +\n drivers/net/mscc_eswitch/sparx5_serdes_regs.h | 3047 +++++++++++++++++\n drivers/net/mscc_eswitch/sparx5_switch.c      | 1181 +++++++\n drivers/net/mscc_eswitch/sparx5_switch.h      |   69 +\n include/dt-bindings/mscc/sparx5_data.h        |   19 +\n 12 files changed, 8481 insertions(+)\n create mode 100644 drivers/net/mscc_eswitch/sparx5_reg_offset.c\n create mode 100644 drivers/net/mscc_eswitch/sparx5_reg_offset.h\n create mode 100644 drivers/net/mscc_eswitch/sparx5_regs.h\n create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes.c\n create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes.h\n create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes_priv.h\n create mode 100644 drivers/net/mscc_eswitch/sparx5_serdes_regs.h\n create mode 100644 drivers/net/mscc_eswitch/sparx5_switch.c\n create mode 100644 drivers/net/mscc_eswitch/sparx5_switch.h\n create mode 100644 include/dt-bindings/mscc/sparx5_data.h",
    "diff": "diff --git a/drivers/net/mscc_eswitch/Kconfig b/drivers/net/mscc_eswitch/Kconfig\nindex f9780661c80..ed07c95ab15 100644\n--- a/drivers/net/mscc_eswitch/Kconfig\n+++ b/drivers/net/mscc_eswitch/Kconfig\n@@ -44,3 +44,10 @@ config MSCC_FELIX_SWITCH\n \thelp\n \t  This driver supports the Ethernet switch integrated in the\n \t  NXP LS1028A SoC.\n+\n+config MSCC_LAN969X_SWITCH\n+\tbool \"Microchip LAN966X switch driver\"\n+\tdepends on DM_ETH && TARGET_LAN969X\n+\tselect PHYLIB\n+\thelp\n+\t  This driver supports the LAN969X network switch device.\ndiff --git a/drivers/net/mscc_eswitch/Makefile b/drivers/net/mscc_eswitch/Makefile\nindex 22342ed1141..ffc9b02b43e 100644\n--- a/drivers/net/mscc_eswitch/Makefile\n+++ b/drivers/net/mscc_eswitch/Makefile\n@@ -5,3 +5,4 @@ obj-$(CONFIG_MSCC_JR2_SWITCH) += jr2_switch.o mscc_xfer.o mscc_miim.o\n obj-$(CONFIG_MSCC_SERVALT_SWITCH) += servalt_switch.o mscc_xfer.o mscc_miim.o\n obj-$(CONFIG_MSCC_SERVAL_SWITCH) += serval_switch.o mscc_xfer.o mscc_mac_table.o mscc_miim.o\n obj-$(CONFIG_MSCC_FELIX_SWITCH) += felix_switch.o\n+obj-$(CONFIG_MSCC_LAN969X_SWITCH) += sparx5_switch.o sparx5_serdes.o sparx5_reg_offset.o mscc_xfer.o\ndiff --git a/drivers/net/mscc_eswitch/sparx5_reg_offset.c b/drivers/net/mscc_eswitch/sparx5_reg_offset.c\nnew file mode 100644\nindex 00000000000..fbb8a0a4453\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_reg_offset.c\n@@ -0,0 +1,353 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (c) 2019 Microsemi Corporation\n+ */\n+\n+#include \"sparx5_reg_offset.h\"\n+#include <linux/bitops.h>\n+\n+const unsigned int sparx5_regfield_addr[FIELD_LAST] = {\n+\t[FIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE] = BIT(10),\n+};\n+\n+const unsigned int sparx5_reg_addr[RA_LAST] = {\n+\t[RA_CPU_RESET_PROT_STAT] = 132,\n+\t[RA_CPU_PROC_CTRL] = 176,\n+\t[RA_GCB_SOFT_RST] = 8,\n+\t[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 24,\n+\t[RA_GCB_GPIO_OUT_CLR] = 8,\n+\t[RA_GCB_GPIO_OUT_CLR1] = 12,\n+\t[RA_GCB_GPIO_OUT] = 16,\n+\t[RA_GCB_GPIO_OUT1] = 20,\n+\t[RA_GCB_GPIO_IN] = 24,\n+\t[RA_GCB_GPIO_IN1] = 28,\n+\t[RA_GCB_GPIO_OE] = 32,\n+\t[RA_GCB_GPIO_OE1] = 36,\n+\t[RA_GCB_GPIO_INTR] = 40,\n+\t[RA_GCB_GPIO_INTR1] = 44,\n+\t[RA_GCB_GPIO_INTR_ENA] = 48,\n+\t[RA_GCB_GPIO_INTR_ENA1] = 52,\n+\t[RA_GCB_GPIO_INTR_IDENT] = 56,\n+\t[RA_GCB_GPIO_INTR_IDENT1] = 60,\n+\t[RA_GCB_GPIO_ALT] = 64,\n+\t[RA_GCB_GPIO_ALT1] = 72,\n+};\n+\n+const unsigned int sparx5_reg_cnt[RC_LAST] = {\n+\t[RC_ANA_AC_OWN_UPSID] = 3,\n+\t[RC_ANA_ACL_VCAP_S2_CFG] = 70,\n+\t[RC_ANA_ACL_OWN_UPSID] = 3,\n+\t[RC_ANA_AC_POL_POL_ACL_RATE_CFG] = 64,\n+\t[RC_ANA_AC_POL_POL_ACL_THRES_CFG] = 64,\n+\t[RC_ANA_AC_POL_POL_ACL_CTRL] = 64,\n+\t[RC_ANA_AC_POL_POL_PORT_THRES_CFG_0] = 280,\n+\t[RC_ANA_AC_POL_POL_PORT_THRES_CFG_1] = 280,\n+\t[RC_ANA_AC_POL_POL_PORT_RATE_CFG] = 280,\n+\t[RC_ANA_CL_OWN_UPSID] = 3,\n+\t[RC_ANA_L2_OWN_UPSID] = 3,\n+\t[RC_ASM_PORT_CFG] = 67,\n+\t[RC_DSM_BUF_CFG] = 67,\n+\t[RC_DSM_IPG_SHRINK_CFG] = 67,\n+\t[RC_DSM_DEV_TX_STOP_WM_CFG] = 67,\n+\t[RC_DSM_RX_PAUSE_CFG] = 67,\n+\t[RC_DSM_MAC_CFG] = 67,\n+\t[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 65,\n+\t[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 65,\n+\t[RC_DSM_TAXI_CAL_CFG] = 9,\n+\t[RC_DSM_PREEMPT_CFG] = 67,\n+\t[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 65,\n+\t[RC_HSCH_PORT_MODE] = 70,\n+\t[RC_QFWD_SWITCH_PORT_MODE] = 70,\n+\t[RC_QSYS_PAUSE_CFG] = 70,\n+\t[RC_QSYS_ATOP] = 70,\n+\t[RC_QSYS_FWD_PRESSURE] = 70,\n+\t[RC_QSYS_CAL_AUTO] = 7,\n+\t[RC_REW_OWN_UPSID] = 3,\n+\t[RC_REW_RTAG_ETAG_CTRL] = 70,\n+};\n+\n+const unsigned int sparx5_reggrp_addr[GA_LAST] = {\n+\t[GA_ANA_AC_RAM_CTRL] = 839108,\n+\t[GA_ANA_AC_PS_COMMON] = 894472,\n+\t[GA_ANA_AC_MIRROR_PROBE] = 893696,\n+\t[GA_ANA_AC_SRC] = 849920,\n+\t[GA_ANA_AC_PGID] = 786432,\n+\t[GA_ANA_AC_PS_STICKY] = 839128,\n+\t[GA_ANA_AC_PS_STICKY_MASK] = 894824,\n+\t[GA_ANA_AC_TSN_SF] = 839136,\n+\t[GA_ANA_AC_TSN_SF_CFG] = 839680,\n+\t[GA_ANA_AC_TSN_SF_STATUS] = 839072,\n+\t[GA_ANA_AC_SG_ACCESS] = 839140,\n+\t[GA_ANA_AC_SG_CONFIG] = 851584,\n+\t[GA_ANA_AC_SG_STATUS] = 839088,\n+\t[GA_ANA_AC_SG_STATUS_STICKY] = 839152,\n+\t[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 851552,\n+\t[GA_ANA_AC_STAT_CNT_CFG_PORT] = 843776,\n+\t[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 893792,\n+\t[GA_ANA_AC_STAT_CNT_CFG_ACL] = 848896,\n+\t[GA_ANA_ACL_COMMON] = 32768,\n+\t[GA_ANA_ACL_KEY_SEL] = 34200,\n+\t[GA_ANA_ACL_CNT_B] = 16384,\n+\t[GA_ANA_ACL_STICKY] = 36408,\n+\t[GA_ANA_AC_POL_POL_ALL_CFG] = 75968,\n+\t[GA_ANA_AC_POL_POL_PORT_CFG] = 65536,\n+\t[GA_ANA_AC_POL_POL_PORT_CTRL] = 73728,\n+\t[GA_ANA_AC_POL_COMMON_BDLB] = 79048,\n+\t[GA_ANA_AC_POL_COMMON_BUM_SLB] = 79056,\n+\t[GA_ANA_AC_SDLB_LBGRP_TBL] = 295468,\n+\t[GA_ANA_CL_PORT] = 131072,\n+\t[GA_ANA_CL_COMMON] = 166912,\n+\t[GA_ANA_L2_COMMON] = 566024,\n+\t[GA_ANA_L3_COMMON] = 493632,\n+\t[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 491460,\n+\t[GA_ASM_CFG] = 33280,\n+\t[GA_ASM_PFC_TIMER_CFG] = 34716,\n+\t[GA_ASM_LBK_WM_CFG] = 34744,\n+\t[GA_ASM_LBK_MISC_CFG] = 34756,\n+\t[GA_ASM_RAM_CTRL] = 34832,\n+\t[GA_DEV2G5_MM_CONFIG] = 216,\n+\t[GA_DEV2G5_MM_STATISTICS] = 224,\n+\t[GA_EACL_ES2_KEY_SELECT_PROFILE] = 149504,\n+\t[GA_EACL_CNT_TBL] = 122880,\n+\t[GA_EACL_POL_CFG] = 150608,\n+\t[GA_EACL_ES2_STICKY] = 118696,\n+\t[GA_EACL_RAM_CTRL] = 118736,\n+\t[GA_GCB_GPIO] = 480,\n+\t[GA_GCB_SIO_CTRL] = 876,\n+\t[GA_HSCH_HSCH_L0_CFG] = 163840,\n+\t[GA_HSCH_HSCH_DWRR] = 162816,\n+\t[GA_HSCH_HSCH_MISC] = 163104,\n+\t[GA_HSCH_HSCH_LEAK_LISTS] = 161664,\n+\t[GA_HSCH_SYSTEM] = 184000,\n+\t[GA_HSCH_MMGT] = 162368,\n+\t[GA_HSCH_TAS_CONFIG] = 162384,\n+\t[GA_HSCH_TAS_PROFILE_CFG] = 188416,\n+\t[GA_HSCH_TAS_LIST_CFG] = 161600,\n+\t[GA_HSCH_TAS_GCL_CFG] = 161584,\n+\t[GA_HSCH_HSCH_TAS_STATE] = 161580,\n+\t[GA_PTP_PTP_CFG] = 320,\n+\t[GA_PTP_PTP_TOD_DOMAINS] = 336,\n+\t[GA_PTP_PHASE_DETECTOR_CTRL] = 420,\n+\t[GA_QSYS_CALCFG] = 2304,\n+\t[GA_QSYS_RAM_CTRL] = 2344,\n+\t[GA_REW_COMMON] = 387264,\n+\t[GA_REW_PORT] = 360448,\n+\t[GA_REW_VOE_PORT_LM_CNT] = 393216,\n+\t[GA_REW_RAM_CTRL] = 378696,\n+\t[GA_VOP_RAM_CTRL] = 279176,\n+\t[GA_XQS_SYSTEM] = 6768,\n+\t[GA_XQS_QLIMIT_SHR] = 7936,\n+};\n+\n+const unsigned int sparx5_reggrp_cnt[GC_LAST] = {\n+\t[GC_ANA_AC_SRC] = 102,\n+\t[GC_ANA_AC_PGID] = 3290,\n+\t[GC_ANA_AC_TSN_SF_CFG] = 1024,\n+\t[GC_ANA_AC_STAT_CNT_CFG_PORT] = 70,\n+\t[GC_ANA_AC_STAT_CNT_CFG_ACL] = 64,\n+\t[GC_ANA_ACL_KEY_SEL] = 134,\n+\t[GC_ANA_ACL_CNT_A] = 4096,\n+\t[GC_ANA_ACL_CNT_B] = 4096,\n+\t[GC_ANA_AC_POL_POL_PORT_CTRL] = 70,\n+\t[GC_ANA_AC_SDLB_LBGRP_TBL] = 10,\n+\t[GC_ANA_AC_SDLB_LBSET_TBL] = 4616,\n+\t[GC_ANA_CL_PORT] = 70,\n+\t[GC_ANA_L2_ISDX_LIMIT] = 1536,\n+\t[GC_ANA_L2_ISDX] = 4096,\n+\t[GC_ANA_L3_VLAN] = 5120,\n+\t[GC_ASM_DEV_STATISTICS] = 65,\n+\t[GC_EACL_ES2_KEY_SELECT_PROFILE] = 138,\n+\t[GC_EACL_CNT_TBL] = 2048,\n+\t[GC_GCB_SIO_CTRL] = 3,\n+\t[GC_HSCH_HSCH_L0_CFG] = 5040,\n+\t[GC_HSCH_HSCH_CFG] = 5040,\n+\t[GC_HSCH_HSCH_DWRR] = 72,\n+\t[GC_HSCH_TAS_PROFILE_CFG] = 100,\n+\t[GC_PTP_PTP_PINS] = 5,\n+\t[GC_PTP_PHASE_DETECTOR_CTRL] = 5,\n+\t[GC_REW_PORT] = 70,\n+\t[GC_REW_VOE_PORT_LM_CNT] = 520,\n+};\n+\n+const unsigned int sparx5_reggrp_sz[GW_LAST] = {\n+\t[GW_ANA_AC_SRC] = 16,\t    [GW_ANA_L2_COMMON] = 700,\n+\t[GW_ASM_CFG] = 1088,\t    [GW_CPU_CPU_REGS] = 204,\n+\t[GW_FDMA_FDMA] = 428,\t    [GW_GCB_CHIP_REGS] = 424,\n+\t[GW_HSCH_TAS_CONFIG] = 12,  [GW_HSCH_TAS_PROFILE_CFG] = 64,\n+\t[GW_HSCH_TAS_GCL_CFG] = 8,  [GW_PTP_PHASE_DETECTOR_CTRL] = 8,\n+\t[GW_QSYS_PAUSE_CFG] = 1128,\n+\t[GW_GCB_GPIO] = 208,\n+};\n+\n+const unsigned int lan969x_regfield_addr[FIELD_LAST] = {\n+\t[FIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE] = BIT(5),\n+};\n+\n+const unsigned int lan969x_reg_addr[RA_LAST] = {\n+\t[RA_CPU_RESET_PROT_STAT] = 136,\n+\t[RA_CPU_PROC_CTRL] = 160,\n+\t[RA_GCB_SOFT_RST] = 12,\n+\t[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20,\n+\t[RA_GCB_GPIO_OUT_CLR] = 12,\n+\t[RA_GCB_GPIO_OUT_CLR1] = 16,\n+\t[RA_GCB_GPIO_OUT] = 24,\n+\t[RA_GCB_GPIO_OUT1] = 28,\n+\t[RA_GCB_GPIO_IN] = 36,\n+\t[RA_GCB_GPIO_IN1] = 40,\n+\t[RA_GCB_GPIO_OE] = 48,\n+\t[RA_GCB_GPIO_OE1] = 52,\n+\t[RA_GCB_GPIO_INTR] = 60,\n+\t[RA_GCB_GPIO_INTR1] = 64,\n+\t[RA_GCB_GPIO_INTR_ENA] = 72,\n+\t[RA_GCB_GPIO_INTR_ENA1] = 76,\n+\t[RA_GCB_GPIO_INTR_IDENT] = 84,\n+\t[RA_GCB_GPIO_INTR_IDENT1] = 88,\n+\t[RA_GCB_GPIO_ALT] = 96,\n+\t[RA_GCB_GPIO_ALT1] = 108,\n+};\n+\n+const unsigned int lan969x_reg_cnt[RC_LAST] = {\n+\t[RC_ANA_AC_OWN_UPSID] = 1,\n+\t[RC_ANA_ACL_VCAP_S2_CFG] = 35,\n+\t[RC_ANA_ACL_OWN_UPSID] = 1,\n+\t[RC_ANA_AC_POL_POL_ACL_RATE_CFG] = 32,\n+\t[RC_ANA_AC_POL_POL_ACL_THRES_CFG] = 32,\n+\t[RC_ANA_AC_POL_POL_ACL_CTRL] = 32,\n+\t[RC_ANA_AC_POL_POL_PORT_THRES_CFG_0] = 140,\n+\t[RC_ANA_AC_POL_POL_PORT_THRES_CFG_1] = 140,\n+\t[RC_ANA_AC_POL_POL_PORT_RATE_CFG] = 140,\n+\t[RC_ANA_CL_OWN_UPSID] = 1,\n+\t[RC_ANA_L2_OWN_UPSID] = 1,\n+\t[RC_ASM_PORT_CFG] = 32,\n+\t[RC_DSM_BUF_CFG] = 32,\n+\t[RC_DSM_IPG_SHRINK_CFG] = 32,\n+\t[RC_DSM_DEV_TX_STOP_WM_CFG] = 32,\n+\t[RC_DSM_RX_PAUSE_CFG] = 32,\n+\t[RC_DSM_MAC_CFG] = 32,\n+\t[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30,\n+\t[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30,\n+\t[RC_DSM_TAXI_CAL_CFG] = 6,\n+\t[RC_DSM_PREEMPT_CFG] = 32,\n+\t[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30,\n+\t[RC_HSCH_PORT_MODE] = 35,\n+\t[RC_QFWD_SWITCH_PORT_MODE] = 35,\n+\t[RC_QSYS_PAUSE_CFG] = 35,\n+\t[RC_QSYS_ATOP] = 35,\n+\t[RC_QSYS_FWD_PRESSURE] = 35,\n+\t[RC_QSYS_CAL_AUTO] = 4,\n+\t[RC_REW_OWN_UPSID] = 1,\n+\t[RC_REW_RTAG_ETAG_CTRL] = 35,\n+};\n+\n+const unsigned int lan969x_reggrp_addr[GA_LAST] = {\n+\t[GA_ANA_AC_RAM_CTRL] = 202000,\n+\t[GA_ANA_AC_PS_COMMON] = 202880,\n+\t[GA_ANA_AC_MIRROR_PROBE] = 203232,\n+\t[GA_ANA_AC_SRC] = 201728,\n+\t[GA_ANA_AC_PGID] = 131072,\n+\t[GA_ANA_AC_PS_STICKY] = 202020,\n+\t[GA_ANA_AC_PS_STICKY_MASK] = 203328,\n+\t[GA_ANA_AC_TSN_SF] = 202028,\n+\t[GA_ANA_AC_TSN_SF_CFG] = 148480,\n+\t[GA_ANA_AC_TSN_SF_STATUS] = 147936,\n+\t[GA_ANA_AC_SG_ACCESS] = 202032,\n+\t[GA_ANA_AC_SG_CONFIG] = 202752,\n+\t[GA_ANA_AC_SG_STATUS] = 147952,\n+\t[GA_ANA_AC_SG_STATUS_STICKY] = 202044,\n+\t[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048,\n+\t[GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800,\n+\t[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068,\n+\t[GA_ANA_AC_STAT_CNT_CFG_ACL] = 201216,\n+\t[GA_ANA_ACL_COMMON] = 8192,\n+\t[GA_ANA_ACL_KEY_SEL] = 9204,\n+\t[GA_ANA_ACL_CNT_B] = 4096,\n+\t[GA_ANA_ACL_STICKY] = 10852,\n+\t[GA_ANA_AC_POL_POL_ALL_CFG] = 17504,\n+\t[GA_ANA_AC_POL_POL_PORT_CFG] = 0,\n+\t[GA_ANA_AC_POL_POL_PORT_CTRL] = 16384,\n+\t[GA_ANA_AC_POL_COMMON_BDLB] = 19464,\n+\t[GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472,\n+\t[GA_ANA_AC_SDLB_LBGRP_TBL] = 31788,\n+\t[GA_ANA_CL_PORT] = 65536,\n+\t[GA_ANA_CL_COMMON] = 87040,\n+\t[GA_ANA_L2_COMMON] = 561928,\n+\t[GA_ANA_L3_COMMON] = 370752,\n+\t[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580,\n+\t[GA_ASM_CFG] = 18304,\n+\t[GA_ASM_PFC_TIMER_CFG] = 15568,\n+\t[GA_ASM_LBK_WM_CFG] = 15596,\n+\t[GA_ASM_LBK_MISC_CFG] = 15608,\n+\t[GA_ASM_RAM_CTRL] = 15684,\n+\t[GA_DEV2G5_MM_CONFIG] = 224,\n+\t[GA_DEV2G5_MM_STATISTICS] = 232,\n+\t[GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864,\n+\t[GA_EACL_CNT_TBL] = 30720,\n+\t[GA_EACL_POL_CFG] = 38400,\n+\t[GA_EACL_ES2_STICKY] = 29072,\n+\t[GA_EACL_RAM_CTRL] = 29112,\n+\t[GA_GCB_GPIO] = 212,\n+\t[GA_GCB_SIO_CTRL] = 560,\n+\t[GA_HSCH_HSCH_L0_CFG] = 40960,\n+\t[GA_HSCH_HSCH_DWRR] = 36480,\n+\t[GA_HSCH_HSCH_MISC] = 36608,\n+\t[GA_HSCH_HSCH_LEAK_LISTS] = 37256,\n+\t[GA_HSCH_SYSTEM] = 37384,\n+\t[GA_HSCH_MMGT] = 36260,\n+\t[GA_HSCH_TAS_CONFIG] = 37696,\n+\t[GA_HSCH_TAS_PROFILE_CFG] = 37712,\n+\t[GA_HSCH_TAS_LIST_CFG] = 36288,\n+\t[GA_HSCH_TAS_GCL_CFG] = 36240,\n+\t[GA_HSCH_HSCH_TAS_STATE] = 36256,\n+\t[GA_PTP_PTP_CFG] = 512,\n+\t[GA_PTP_PTP_TOD_DOMAINS] = 528,\n+\t[GA_PTP_PHASE_DETECTOR_CTRL] = 628,\n+\t[GA_QSYS_CALCFG] = 2164,\n+\t[GA_QSYS_RAM_CTRL] = 2204,\n+\t[GA_REW_COMMON] = 98304,\n+\t[GA_REW_PORT] = 49152,\n+\t[GA_REW_VOE_PORT_LM_CNT] = 90112,\n+\t[GA_REW_RAM_CTRL] = 93992,\n+\t[GA_VOP_RAM_CTRL] = 16368,\n+\t[GA_XQS_SYSTEM] = 5744,\n+\t[GA_XQS_QLIMIT_SHR] = 6912,\n+};\n+\n+const unsigned int lan969x_reggrp_cnt[GC_LAST] = {\n+\t[GC_ANA_AC_SRC] = 67,\n+\t[GC_ANA_AC_PGID] = 1054,\n+\t[GC_ANA_AC_TSN_SF_CFG] = 256,\n+\t[GC_ANA_AC_STAT_CNT_CFG_PORT] = 35,\n+\t[GC_ANA_AC_STAT_CNT_CFG_ACL] = 32,\n+\t[GC_ANA_ACL_KEY_SEL] = 99,\n+\t[GC_ANA_ACL_CNT_A] = 1024,\n+\t[GC_ANA_ACL_CNT_B] = 1024,\n+\t[GC_ANA_AC_POL_POL_PORT_CTRL] = 35,\n+\t[GC_ANA_AC_SDLB_LBGRP_TBL] = 5,\n+\t[GC_ANA_AC_SDLB_LBSET_TBL] = 496,\n+\t[GC_ANA_CL_PORT] = 35,\n+\t[GC_ANA_L2_ISDX_LIMIT] = 256,\n+\t[GC_ANA_L2_ISDX] = 1024,\n+\t[GC_ANA_L3_VLAN] = 4608,\n+\t[GC_ASM_DEV_STATISTICS] = 30,\n+\t[GC_EACL_ES2_KEY_SELECT_PROFILE] = 68,\n+\t[GC_EACL_CNT_TBL] = 512,\n+\t[GC_GCB_SIO_CTRL] = 1,\n+\t[GC_HSCH_HSCH_L0_CFG] = 1120,\n+\t[GC_HSCH_HSCH_CFG] = 1120,\n+\t[GC_HSCH_HSCH_DWRR] = 32,\n+\t[GC_HSCH_TAS_PROFILE_CFG] = 30,\n+\t[GC_PTP_PTP_PINS] = 8,\n+\t[GC_PTP_PHASE_DETECTOR_CTRL] = 8,\n+\t[GC_REW_PORT] = 35,\n+\t[GC_REW_VOE_PORT_LM_CNT] = 240,\n+};\n+\n+const unsigned int lan969x_reggrp_sz[GW_LAST] = {\n+\t[GW_ANA_AC_SRC] = 4,\t    [GW_ANA_L2_COMMON] = 712,\n+\t[GW_ASM_CFG] = 1092,\t    [GW_CPU_CPU_REGS] = 180,\n+\t[GW_FDMA_FDMA] = 448,\t    [GW_GCB_CHIP_REGS] = 180,\n+\t[GW_HSCH_TAS_CONFIG] = 16,  [GW_HSCH_TAS_PROFILE_CFG] = 68,\n+\t[GW_HSCH_TAS_GCL_CFG] = 16, [GW_PTP_PHASE_DETECTOR_CTRL] = 12,\n+\t[GW_QSYS_PAUSE_CFG] = 988,\n+\t[GW_GCB_GPIO] = 212,\n+};\ndiff --git a/drivers/net/mscc_eswitch/sparx5_reg_offset.h b/drivers/net/mscc_eswitch/sparx5_reg_offset.h\nnew file mode 100644\nindex 00000000000..519b06b813d\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_reg_offset.h\n@@ -0,0 +1,201 @@\n+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n+/*\n+ * Copyright (c) 2018 Microsemi Corporation\n+ */\n+\n+enum sparx5_field {\n+\tFIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE,\n+\tFIELD_LAST,\n+};\n+\n+enum sparx5_ra {\n+\tRA_CPU_RESET_PROT_STAT,\n+\tRA_CPU_PROC_CTRL,\n+\tRA_GCB_SOFT_RST,\n+\tRA_GCB_HW_SGPIO_TO_SD_MAP_CFG,\n+\tRA_GCB_GPIO_OUT_CLR,\n+\tRA_GCB_GPIO_OUT_CLR1,\n+\tRA_GCB_GPIO_OUT,\n+\tRA_GCB_GPIO_OUT1,\n+\tRA_GCB_GPIO_IN,\n+\tRA_GCB_GPIO_IN1,\n+\tRA_GCB_GPIO_OE,\n+\tRA_GCB_GPIO_OE1,\n+\tRA_GCB_GPIO_INTR,\n+\tRA_GCB_GPIO_INTR1,\n+\tRA_GCB_GPIO_INTR_ENA,\n+\tRA_GCB_GPIO_INTR_ENA1,\n+\tRA_GCB_GPIO_INTR_IDENT,\n+\tRA_GCB_GPIO_INTR_IDENT1,\n+\tRA_GCB_GPIO_ALT,\n+\tRA_GCB_GPIO_ALT1,\n+\tRA_LAST,\n+};\n+\n+enum sparx5_rc {\n+\tRC_ANA_AC_OWN_UPSID,\n+\tRC_ANA_ACL_VCAP_S2_CFG,\n+\tRC_ANA_ACL_OWN_UPSID,\n+\tRC_ANA_AC_POL_POL_ACL_RATE_CFG,\n+\tRC_ANA_AC_POL_POL_ACL_THRES_CFG,\n+\tRC_ANA_AC_POL_POL_ACL_CTRL,\n+\tRC_ANA_AC_POL_POL_PORT_THRES_CFG_0,\n+\tRC_ANA_AC_POL_POL_PORT_THRES_CFG_1,\n+\tRC_ANA_AC_POL_POL_PORT_RATE_CFG,\n+\tRC_ANA_CL_OWN_UPSID,\n+\tRC_ANA_L2_OWN_UPSID,\n+\tRC_ASM_PORT_CFG,\n+\tRC_DSM_BUF_CFG,\n+\tRC_DSM_IPG_SHRINK_CFG,\n+\tRC_DSM_DEV_TX_STOP_WM_CFG,\n+\tRC_DSM_RX_PAUSE_CFG,\n+\tRC_DSM_MAC_CFG,\n+\tRC_DSM_MAC_ADDR_BASE_HIGH_CFG,\n+\tRC_DSM_MAC_ADDR_BASE_LOW_CFG,\n+\tRC_DSM_TAXI_CAL_CFG,\n+\tRC_DSM_PREEMPT_CFG,\n+\tRC_GCB_HW_SGPIO_TO_SD_MAP_CFG,\n+\tRC_HSCH_PORT_MODE,\n+\tRC_QFWD_SWITCH_PORT_MODE,\n+\tRC_QSYS_PAUSE_CFG,\n+\tRC_QSYS_ATOP,\n+\tRC_QSYS_FWD_PRESSURE,\n+\tRC_QSYS_CAL_AUTO,\n+\tRC_REW_OWN_UPSID,\n+\tRC_REW_RTAG_ETAG_CTRL,\n+\tRC_LAST,\n+};\n+\n+enum sparx5_ga {\n+\tGA_ANA_AC_RAM_CTRL,\n+\tGA_ANA_AC_PS_COMMON,\n+\tGA_ANA_AC_MIRROR_PROBE,\n+\tGA_ANA_AC_SRC,\n+\tGA_ANA_AC_PGID,\n+\tGA_ANA_AC_PS_STICKY,\n+\tGA_ANA_AC_PS_STICKY_MASK,\n+\tGA_ANA_AC_TSN_SF,\n+\tGA_ANA_AC_TSN_SF_CFG,\n+\tGA_ANA_AC_TSN_SF_STATUS,\n+\tGA_ANA_AC_SG_ACCESS,\n+\tGA_ANA_AC_SG_CONFIG,\n+\tGA_ANA_AC_SG_STATUS,\n+\tGA_ANA_AC_SG_STATUS_STICKY,\n+\tGA_ANA_AC_STAT_GLOBAL_CFG_PORT,\n+\tGA_ANA_AC_STAT_CNT_CFG_PORT,\n+\tGA_ANA_AC_STAT_GLOBAL_CFG_ACL,\n+\tGA_ANA_AC_STAT_CNT_CFG_ACL,\n+\tGA_ANA_ACL_COMMON,\n+\tGA_ANA_ACL_KEY_SEL,\n+\tGA_ANA_ACL_CNT_B,\n+\tGA_ANA_ACL_STICKY,\n+\tGA_ANA_AC_POL_POL_ALL_CFG,\n+\tGA_ANA_AC_POL_POL_PORT_CFG,\n+\tGA_ANA_AC_POL_POL_PORT_CTRL,\n+\tGA_ANA_AC_POL_COMMON_BDLB,\n+\tGA_ANA_AC_POL_COMMON_BUM_SLB,\n+\tGA_ANA_AC_SDLB_LBGRP_TBL,\n+\tGA_ANA_CL_PORT,\n+\tGA_ANA_CL_COMMON,\n+\tGA_ANA_L2_COMMON,\n+\tGA_ANA_L3_COMMON,\n+\tGA_ANA_L3_VLAN_ARP_L3MC_STICKY,\n+\tGA_ASM_CFG,\n+\tGA_ASM_PFC_TIMER_CFG,\n+\tGA_ASM_LBK_WM_CFG,\n+\tGA_ASM_LBK_MISC_CFG,\n+\tGA_ASM_RAM_CTRL,\n+\tGA_DEV2G5_MM_CONFIG,\n+\tGA_DEV2G5_MM_STATISTICS,\n+\tGA_EACL_ES2_KEY_SELECT_PROFILE,\n+\tGA_EACL_CNT_TBL,\n+\tGA_EACL_POL_CFG,\n+\tGA_EACL_ES2_STICKY,\n+\tGA_EACL_RAM_CTRL,\n+\tGA_GCB_GPIO,\n+\tGA_GCB_SIO_CTRL,\n+\tGA_HSCH_HSCH_L0_CFG,\n+\tGA_HSCH_HSCH_DWRR,\n+\tGA_HSCH_HSCH_MISC,\n+\tGA_HSCH_HSCH_LEAK_LISTS,\n+\tGA_HSCH_SYSTEM,\n+\tGA_HSCH_MMGT,\n+\tGA_HSCH_TAS_CONFIG,\n+\tGA_HSCH_TAS_PROFILE_CFG,\n+\tGA_HSCH_TAS_LIST_CFG,\n+\tGA_HSCH_TAS_GCL_CFG,\n+\tGA_HSCH_HSCH_TAS_STATE,\n+\tGA_PTP_PTP_CFG,\n+\tGA_PTP_PTP_TOD_DOMAINS,\n+\tGA_PTP_PHASE_DETECTOR_CTRL,\n+\tGA_QSYS_CALCFG,\n+\tGA_QSYS_RAM_CTRL,\n+\tGA_REW_COMMON,\n+\tGA_REW_PORT,\n+\tGA_REW_VOE_PORT_LM_CNT,\n+\tGA_REW_RAM_CTRL,\n+\tGA_VOP_RAM_CTRL,\n+\tGA_XQS_SYSTEM,\n+\tGA_XQS_QLIMIT_SHR,\n+\tGA_LAST,\n+};\n+\n+enum sparx5_gc {\n+\tGC_ANA_AC_SRC,\n+\tGC_ANA_AC_PGID,\n+\tGC_ANA_AC_TSN_SF_CFG,\n+\tGC_ANA_AC_STAT_CNT_CFG_PORT,\n+\tGC_ANA_AC_STAT_CNT_CFG_ACL,\n+\tGC_ANA_ACL_KEY_SEL,\n+\tGC_ANA_ACL_CNT_A,\n+\tGC_ANA_ACL_CNT_B,\n+\tGC_ANA_AC_POL_POL_PORT_CTRL,\n+\tGC_ANA_AC_SDLB_LBGRP_TBL,\n+\tGC_ANA_AC_SDLB_LBSET_TBL,\n+\tGC_ANA_CL_PORT,\n+\tGC_ANA_L2_ISDX_LIMIT,\n+\tGC_ANA_L2_ISDX,\n+\tGC_ANA_L3_VLAN,\n+\tGC_ASM_DEV_STATISTICS,\n+\tGC_EACL_ES2_KEY_SELECT_PROFILE,\n+\tGC_EACL_CNT_TBL,\n+\tGC_GCB_SIO_CTRL,\n+\tGC_HSCH_HSCH_L0_CFG,\n+\tGC_HSCH_HSCH_CFG,\n+\tGC_HSCH_HSCH_DWRR,\n+\tGC_HSCH_TAS_PROFILE_CFG,\n+\tGC_PTP_PTP_PINS,\n+\tGC_PTP_PHASE_DETECTOR_CTRL,\n+\tGC_REW_PORT,\n+\tGC_REW_VOE_PORT_LM_CNT,\n+\tGC_LAST,\n+};\n+\n+enum sparx5_gw {\n+\tGW_ANA_AC_SRC,\n+\tGW_ANA_L2_COMMON,\n+\tGW_ASM_CFG,\n+\tGW_CPU_CPU_REGS,\n+\tGW_FDMA_FDMA,\n+\tGW_GCB_CHIP_REGS,\n+\tGW_HSCH_TAS_CONFIG,\n+\tGW_HSCH_TAS_PROFILE_CFG,\n+\tGW_HSCH_TAS_GCL_CFG,\n+\tGW_PTP_PHASE_DETECTOR_CTRL,\n+\tGW_QSYS_PAUSE_CFG,\n+\tGW_GCB_GPIO,\n+\tGW_LAST,\n+};\n+\n+extern const unsigned int sparx5_reg_addr[RA_LAST];\n+extern const unsigned int sparx5_reg_cnt[RC_LAST];\n+extern const unsigned int sparx5_reggrp_addr[GA_LAST];\n+extern const unsigned int sparx5_reggrp_cnt[GC_LAST];\n+extern const unsigned int sparx5_reggrp_sz[GW_LAST];\n+extern const unsigned int sparx5_regfield_addr[FIELD_LAST];\n+extern const unsigned int lan969x_reg_addr[RA_LAST];\n+extern const unsigned int lan969x_reg_cnt[RC_LAST];\n+extern const unsigned int lan969x_reggrp_addr[GA_LAST];\n+extern const unsigned int lan969x_reggrp_cnt[GC_LAST];\n+extern const unsigned int lan969x_reggrp_sz[GW_LAST];\n+extern const unsigned int lan969x_regfield_addr[FIELD_LAST];\ndiff --git a/drivers/net/mscc_eswitch/sparx5_regs.h b/drivers/net/mscc_eswitch/sparx5_regs.h\nnew file mode 100644\nindex 00000000000..df6ea270e39\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_regs.h\n@@ -0,0 +1,701 @@\n+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n+/*\n+ * Copyright (c) 2018 Microsemi Corporation\n+ */\n+\n+#include <linux/bitfield.h>\n+\n+#define GRP_ADDR(o)   priv->data->regs.reggrp_addr[o]\n+#define GRP_CNT(o)    priv->data->regs.reggrp_cnt[o]\n+#define GRP_SIZE(o)   priv->data->regs.reggrp_size[o]\n+#define REG_ADDR(o)   priv->data->regs.reg_addr[o]\n+#define REG_CNT(o)    priv->data->regs.reg_cnt[o]\n+#define FIELD_ADDR(o) priv->data->regs.regfield_addr[o]\n+\n+#define __REG(...) __VA_ARGS__\n+\n+/* RAM init regs */\n+#define ANA_AC_RAM_INIT                                                      \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_RAM_CTRL), 0, 1, 4, 0, \\\n+\t      0, 1, 4)\n+#define QSYS_RAM_INIT                                                          \\\n+\t__REG(TARGET_QSYS, 0, 1, GRP_ADDR(GA_QSYS_RAM_CTRL), 0, 1, 4, 0, 0, 1, \\\n+\t      4)\n+#define ASM_RAM_INIT \\\n+\t__REG(TARGET_ASM, 0, 1, GRP_ADDR(GA_ASM_RAM_CTRL), 0, 1, 4, 0, 0, 1, 4)\n+#define REW_RAM_INIT \\\n+\t__REG(TARGET_REW, 0, 1, GRP_ADDR(GA_REW_RAM_CTRL), 0, 1, 4, 0, 0, 1, 4)\n+#define DSM_RAM_INIT __REG(TARGET_DSM, 0, 1, 0, 0, 1, 4, 0, 0, 1, 4)\n+#define EACL_RAM_INIT                                                          \\\n+\t__REG(TARGET_EACL, 0, 1, GRP_ADDR(GA_EACL_RAM_CTRL), 0, 1, 4, 0, 0, 1, \\\n+\t      4)\n+#define VCAP_SUPER_RAM_INIT \\\n+\t__REG(TARGET_VCAP_SUPER, 0, 1, 1120, 0, 1, 4, 0, 0, 1, 4)\n+#define VOP_RAM_INIT \\\n+\t__REG(TARGET_VOP, 0, 1, GRP_ADDR(GA_VOP_RAM_CTRL), 0, 1, 4, 0, 0, 1, 4)\n+\n+/* ANA_AC:STAT_GLOBAL_CFG_PORT:STAT_RESET */\n+#define ANA_AC_STAT_RESET                                                    \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_STAT_GLOBAL_CFG_PORT), \\\n+\t      0, 1, 20, 16, 0, 1, 4)\n+\n+/* ASM:CFG:STAT_CFG */\n+#define ASM_STAT_CFG                                        \\\n+\t__REG(TARGET_ASM, 0, 1, GRP_ADDR(GA_ASM_CFG), 0, 1, \\\n+\t      GRP_SIZE(GW_ASM_CFG), 0, 0, 1, 4)\n+\n+/* QSYS:CALCFG:CAL_AUTO */\n+#define QSYS_CAL_AUTO(r)                                                   \\\n+\t__REG(TARGET_QSYS, 0, 1, GRP_ADDR(GA_QSYS_CALCFG), 0, 1, 40, 0, r, \\\n+\t      REG_CNT(RC_QSYS_CAL_AUTO), 4)\n+\n+/* QSYS:CALCFG:CAL_CTRL */\n+#define QSYS_CAL_CTRL                                                          \\\n+\t__REG(TARGET_QSYS, 0, 1, GRP_ADDR(GA_QSYS_CALCFG), 0, 1, 40, 36, 0, 1, \\\n+\t      4)\n+\n+#define QSYS_CAL_CTRL_CAL_MODE GENMASK(14, 11)\n+#define QSYS_CAL_CTRL_CAL_MODE_SET(x) FIELD_PREP(QSYS_CAL_CTRL_CAL_MODE, x)\n+#define QSYS_CAL_CTRL_CAL_MODE_GET(x) FIELD_GET(QSYS_CAL_CTRL_CAL_MODE, x)\n+\n+/* PORT_CONF:HW_CFG:DEV5G_MODES */\n+#define PORT_CONF_DEV5G_MODES \\\n+\t__REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 0, 0, 1, 4)\n+\n+#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE BIT(12)\n+#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(x) \\\n+\tFIELD_PREP(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)\n+#define PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_GET(x) \\\n+\tFIELD_GET(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE, x)\n+\n+/* PORT_CONF:HW_CFG:DEV10G_MODES */\n+#define PORT_CONF_DEV10G_MODES \\\n+\t__REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 4, 0, 1, 4)\n+\n+/* SPARX5 ONLY */\n+/* PORT_CONF:HW_CFG:DEV25G_MODES */\n+#define PORT_CONF_DEV25G_MODES                                                 \\\n+\t__REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 8, 0, 1, 4)\n+\n+/* DSM:CFG:DEV_TX_STOP_WM_CFG */\n+#define DSM_DEV_TX_STOP_WM_CFG(r)                        \\\n+\t__REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 1360, r, \\\n+\t      REG_CNT(RC_DSM_DEV_TX_STOP_WM_CFG), 4)\n+\n+#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA BIT(8)\n+#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(x) \\\n+\tFIELD_PREP(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)\n+#define DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_GET(x) \\\n+\tFIELD_GET(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA, x)\n+\n+/* PORT_CONF:HW_CFG:QSGMII_ENA */\n+#define PORT_CONF_QSGMII_ENA \\\n+\t__REG(TARGET_PORT_CONF, 0, 1, 0, 0, 1, 24, 12, 0, 1, 4)\n+\n+/* PORT_CONF:USGMII_CFG_STAT:USGMII_CFG */\n+#define PORT_CONF_USGMII_CFG(g) \\\n+\t__REG(TARGET_PORT_CONF, 0, 1, 72, g, 6, 8, 0, 0, 1, 4)\n+\n+/* DEV1G:DEV_CFG_STATUS:DEV_RST_CTRL */\n+#define DEV2G5_DEV_RST_CTRL(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 0, 0, 1, 36, 0, 0, 1, 4)\n+\n+#define DEV2G5_DEV_RST_CTRL_SPEED_SEL GENMASK(22, 20)\n+#define DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(x) \\\n+\tFIELD_PREP(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)\n+#define DEV2G5_DEV_RST_CTRL_SPEED_SEL_GET(x) \\\n+\tFIELD_GET(DEV2G5_DEV_RST_CTRL_SPEED_SEL, x)\n+\n+#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST BIT(17)\n+#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(x) \\\n+\tFIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)\n+#define DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_GET(x) \\\n+\tFIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST, x)\n+\n+#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST BIT(16)\n+#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(x) \\\n+\tFIELD_PREP(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)\n+#define DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_GET(x) \\\n+\tFIELD_GET(DEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST, x)\n+\n+#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST BIT(12)\n+#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(x) \\\n+\tFIELD_PREP(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)\n+#define DEV2G5_DEV_RST_CTRL_PCS_TX_RST_GET(x) \\\n+\tFIELD_GET(DEV2G5_DEV_RST_CTRL_PCS_TX_RST, x)\n+\n+/* ANA_AC:PGID:PGID_CFG */\n+#define ANA_AC_PGID_CFG(g)                                      \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_PGID), g, \\\n+\t      GRP_CNT(GC_ANA_AC_PGID), 16, 0, 0, 1, 4)\n+\n+/* SPARX5 ONLY */\n+/* ANA_AC:PGID:PGID_CFG1 */\n+#define ANA_AC_PGID_CFG1(g)                                     \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_PGID), g, \\\n+\t      GRP_CNT(GC_ANA_AC_PGID), 16, 4, 0, 1, 4)\n+\n+/* SPARX5 ONLY */\n+/* ANA_AC:PGID:PGID_CFG2 */\n+#define ANA_AC_PGID_CFG2(g)                                     \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_PGID), g, \\\n+\t      GRP_CNT(GC_ANA_AC_PGID), 16, 8, 0, 1, 4)\n+\n+/* ANA_AC:SRC:SRC_CFG */\n+#define ANA_AC_SRC_CFG(g)                                      \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_SRC), g, \\\n+\t      GRP_CNT(GC_ANA_AC_SRC), GRP_SIZE(GW_ANA_AC_SRC), 0, 0, 1, 4)\n+\n+/* SPARX5 ONLY */\n+/* ANA_AC:SRC:SRC_CFG1 */\n+#define ANA_AC_SRC_CFG1(g)                                     \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_SRC), g, \\\n+\t      GRP_CNT(GC_ANA_AC_SRC), GRP_SIZE(GW_ANA_AC_SRC), 4, 0, 1, 4)\n+\n+/* SPARX5 ONLY */\n+/* ANA_AC:SRC:SRC_CFG2 */\n+#define ANA_AC_SRC_CFG2(g)                                     \\\n+\t__REG(TARGET_ANA_AC, 0, 1, GRP_ADDR(GA_ANA_AC_SRC), g, \\\n+\t      GRP_CNT(GC_ANA_AC_SRC), GRP_SIZE(GW_ANA_AC_SRC), 8, 0, 1, 4)\n+\n+/* XQS:SYSTEM:STAT_CFG */\n+#define XQS_STAT_CFG                                                           \\\n+\t__REG(TARGET_XQS, 0, 1, GRP_ADDR(GA_XQS_SYSTEM), 0, 1, 872, 860, 0, 1, \\\n+\t      4)\n+\n+/* ANA_CL:PORT:VLAN_CTRL */\n+#define ANA_CL_VLAN_CTRL(g)                                     \\\n+\t__REG(TARGET_ANA_CL, 0, 1, GRP_ADDR(GA_ANA_CL_PORT), g, \\\n+\t      GRP_CNT(GC_ANA_CL_PORT), 512, 32, 0, 1, 4)\n+\n+#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA BIT(19)\n+#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(x) \\\n+\tFIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)\n+#define ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_GET(x) \\\n+\tFIELD_GET(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA, x)\n+\n+#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT GENMASK(18, 17)\n+#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(x) \\\n+\tFIELD_PREP(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)\n+#define ANA_CL_VLAN_CTRL_VLAN_POP_CNT_GET(x) \\\n+\tFIELD_GET(ANA_CL_VLAN_CTRL_VLAN_POP_CNT, x)\n+\n+#define ANA_CL_VLAN_CTRL_PORT_VID GENMASK(11, 0)\n+#define ANA_CL_VLAN_CTRL_PORT_VID_SET(x) \\\n+\tFIELD_PREP(ANA_CL_VLAN_CTRL_PORT_VID, x)\n+#define ANA_CL_VLAN_CTRL_PORT_VID_GET(x) FIELD_GET(ANA_CL_VLAN_CTRL_PORT_VID, x)\n+\n+/* ANA_L3:VLAN:VLAN_CFG */\n+#define ANA_L3_VLAN_CFG(g)                                                     \\\n+\t__REG(TARGET_ANA_L3, 0, 1, 0, g, GRP_CNT(GC_ANA_L3_VLAN), 64, 8, 0, 1, \\\n+\t      4)\n+\n+#define ANA_L3_VLAN_CFG_VLAN_FID GENMASK(20, 8)\n+#define ANA_L3_VLAN_CFG_VLAN_FID_SET(x) FIELD_PREP(ANA_L3_VLAN_CFG_VLAN_FID, x)\n+#define ANA_L3_VLAN_CFG_VLAN_FID_GET(x) FIELD_GET(ANA_L3_VLAN_CFG_VLAN_FID, x)\n+\n+#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS BIT(3)\n+#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(x) \\\n+\tFIELD_PREP(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)\n+#define ANA_L3_VLAN_CFG_VLAN_LRN_DIS_GET(x) \\\n+\tFIELD_GET(ANA_L3_VLAN_CFG_VLAN_LRN_DIS, x)\n+\n+/* ANA_L3:COMMON:VLAN_CTRL */\n+#define ANA_L3_VLAN_CTRL                                                     \\\n+\t__REG(TARGET_ANA_L3, 0, 1, GRP_ADDR(GA_ANA_L3_COMMON), 0, 1, 184, 4, \\\n+\t      0, 1, 4)\n+\n+#define ANA_L3_VLAN_CTRL_VLAN_ENA BIT(0)\n+#define ANA_L3_VLAN_CTRL_VLAN_ENA_SET(x) \\\n+\tFIELD_PREP(ANA_L3_VLAN_CTRL_VLAN_ENA, x)\n+#define ANA_L3_VLAN_CTRL_VLAN_ENA_GET(x) FIELD_GET(ANA_L3_VLAN_CTRL_VLAN_ENA, x)\n+\n+/* HSCH:MMGT:RESET_CFG */\n+#define HSCH_RESET_CFG \\\n+\t__REG(TARGET_HSCH, 0, 1, GRP_ADDR(GA_HSCH_MMGT), 0, 1, 16, 8, 0, 1, 4)\n+\n+#define HSCH_RESET_CFG_CORE_ENA BIT(0)\n+#define HSCH_RESET_CFG_CORE_ENA_SET(x) FIELD_PREP(HSCH_RESET_CFG_CORE_ENA, x)\n+#define HSCH_RESET_CFG_CORE_ENA_GET(x) FIELD_GET(HSCH_RESET_CFG_CORE_ENA, x)\n+\n+/* ASM:CFG:PORT_CFG */\n+#define ASM_PORT_CFG(r)                                     \\\n+\t__REG(TARGET_ASM, 0, 1, GRP_ADDR(GA_ASM_CFG), 0, 1, \\\n+\t      GRP_SIZE(GW_ASM_CFG), 540, r, REG_CNT(RC_ASM_PORT_CFG), 4)\n+\n+#define ASM_PORT_CFG_NO_PREAMBLE_ENA BIT(9)\n+#define ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(x) \\\n+\tFIELD_PREP(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)\n+#define ASM_PORT_CFG_NO_PREAMBLE_ENA_GET(x) \\\n+\tFIELD_GET(ASM_PORT_CFG_NO_PREAMBLE_ENA, x)\n+\n+#define ASM_PORT_CFG_PAD_ENA BIT(6)\n+#define ASM_PORT_CFG_PAD_ENA_SET(x) FIELD_PREP(ASM_PORT_CFG_PAD_ENA, x)\n+#define ASM_PORT_CFG_PAD_ENA_GET(x) FIELD_GET(ASM_PORT_CFG_PAD_ENA, x)\n+\n+#define ASM_PORT_CFG_INJ_FORMAT_CFG GENMASK(3, 2)\n+#define ASM_PORT_CFG_INJ_FORMAT_CFG_SET(x) \\\n+\tFIELD_PREP(ASM_PORT_CFG_INJ_FORMAT_CFG, x)\n+#define ASM_PORT_CFG_INJ_FORMAT_CFG_GET(x) \\\n+\tFIELD_GET(ASM_PORT_CFG_INJ_FORMAT_CFG, x)\n+\n+/* DEVCPU_QS:INJ:INJ_GRP_CFG */\n+#define QS_INJ_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 36, 0, 1, 40, 0, r, 2, 4)\n+\n+#define QS_INJ_GRP_CFG_MODE GENMASK(3, 2)\n+#define QS_INJ_GRP_CFG_MODE_SET(x) FIELD_PREP(QS_INJ_GRP_CFG_MODE, x)\n+#define QS_INJ_GRP_CFG_MODE_GET(x) FIELD_GET(QS_INJ_GRP_CFG_MODE, x)\n+\n+#define QS_INJ_GRP_CFG_BYTE_SWAP BIT(0)\n+#define QS_INJ_GRP_CFG_BYTE_SWAP_SET(x) FIELD_PREP(QS_INJ_GRP_CFG_BYTE_SWAP, x)\n+#define QS_INJ_GRP_CFG_BYTE_SWAP_GET(x) FIELD_GET(QS_INJ_GRP_CFG_BYTE_SWAP, x)\n+\n+/* DEVCPU_QS:XTR:XTR_GRP_CFG */\n+#define QS_XTR_GRP_CFG(r) __REG(TARGET_QS, 0, 1, 0, 0, 1, 36, 0, r, 2, 4)\n+\n+#define QS_XTR_GRP_CFG_MODE GENMASK(3, 2)\n+#define QS_XTR_GRP_CFG_MODE_SET(x) FIELD_PREP(QS_XTR_GRP_CFG_MODE, x)\n+#define QS_XTR_GRP_CFG_MODE_GET(x) FIELD_GET(QS_XTR_GRP_CFG_MODE, x)\n+\n+#define QS_XTR_GRP_CFG_STATUS_WORD_POS BIT(1)\n+#define QS_XTR_GRP_CFG_STATUS_WORD_POS_SET(x) \\\n+\tFIELD_PREP(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)\n+#define QS_XTR_GRP_CFG_STATUS_WORD_POS_GET(x) \\\n+\tFIELD_GET(QS_XTR_GRP_CFG_STATUS_WORD_POS, x)\n+\n+#define QS_XTR_GRP_CFG_BYTE_SWAP BIT(0)\n+#define QS_XTR_GRP_CFG_BYTE_SWAP_SET(x) FIELD_PREP(QS_XTR_GRP_CFG_BYTE_SWAP, x)\n+#define QS_XTR_GRP_CFG_BYTE_SWAP_GET(x) FIELD_GET(QS_XTR_GRP_CFG_BYTE_SWAP, x)\n+\n+/* QFWD:SYSTEM:SWITCH_PORT_MODE */\n+#define QFWD_SWITCH_PORT_MODE(r)                     \\\n+\t__REG(TARGET_QFWD, 0, 1, 0, 0, 1, 340, 0, r, \\\n+\t      REG_CNT(RC_QFWD_SWITCH_PORT_MODE), 4)\n+\n+#define QFWD_SWITCH_PORT_MODE_PORT_ENA BIT(19)\n+#define QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(x) \\\n+\tFIELD_PREP(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)\n+#define QFWD_SWITCH_PORT_MODE_PORT_ENA_GET(x) \\\n+\tFIELD_GET(QFWD_SWITCH_PORT_MODE_PORT_ENA, x)\n+\n+/* ANA_CL:PORT:FILTER_CTRL */\n+#define ANA_CL_FILTER_CTRL(g)                                   \\\n+\t__REG(TARGET_ANA_CL, 0, 1, GRP_ADDR(GA_ANA_CL_PORT), g, \\\n+\t      GRP_CNT(GC_ANA_CL_PORT), 512, 4, 0, 1, 4)\n+\n+#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA BIT(0)\n+#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(x) \\\n+\tFIELD_PREP(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)\n+#define ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_GET(x) \\\n+\tFIELD_GET(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA, x)\n+\n+/* ANA_L2:COMMON:FWD_CFG */\n+#define ANA_L2_FWD_CFG                                               \\\n+\t__REG(TARGET_ANA_L2, 0, 1, GRP_ADDR(GA_ANA_L2_COMMON), 0, 1, \\\n+\t      GRP_SIZE(GW_ANA_L2_COMMON), 0, 0, 1, 4)\n+\n+#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA BIT(6)\n+#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(x) \\\n+\tFIELD_PREP(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)\n+#define ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_GET(x) \\\n+\tFIELD_GET(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA, x)\n+\n+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_CFG */\n+#define DEV2G5_PCS1G_CFG(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 0, 0, 1, 4)\n+\n+#define DEV2G5_PCS1G_CFG_PCS_ENA BIT(0)\n+#define DEV2G5_PCS1G_CFG_PCS_ENA_SET(x) FIELD_PREP(DEV2G5_PCS1G_CFG_PCS_ENA, x)\n+#define DEV2G5_PCS1G_CFG_PCS_ENA_GET(x) FIELD_GET(DEV2G5_PCS1G_CFG_PCS_ENA, x)\n+\n+/* DEV1G:MAC_CFG_STATUS:MAC_ENA_CFG */\n+#define DEV2G5_MAC_ENA_CFG(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 0, 0, 1, 4)\n+\n+#define DEV2G5_MAC_ENA_CFG_RX_ENA BIT(4)\n+#define DEV2G5_MAC_ENA_CFG_RX_ENA_SET(x) \\\n+\tFIELD_PREP(DEV2G5_MAC_ENA_CFG_RX_ENA, x)\n+#define DEV2G5_MAC_ENA_CFG_RX_ENA_GET(x) FIELD_GET(DEV2G5_MAC_ENA_CFG_RX_ENA, x)\n+\n+#define DEV2G5_MAC_ENA_CFG_TX_ENA BIT(0)\n+#define DEV2G5_MAC_ENA_CFG_TX_ENA_SET(x) \\\n+\tFIELD_PREP(DEV2G5_MAC_ENA_CFG_TX_ENA, x)\n+#define DEV2G5_MAC_ENA_CFG_TX_ENA_GET(x) FIELD_GET(DEV2G5_MAC_ENA_CFG_TX_ENA, x)\n+\n+/*DEV1G:USXGMII_ANEG_CFG_STATUS:USXGMII_PCS_SD_CFG */\n+#define DEV2G5_USXGMII_PCS_SD_CFG(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 36, 0, 1, 16, 8, 0, 1, 4)\n+\n+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_MODE_CFG */\n+#define DEV2G5_PCS1G_MODE_CFG(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 4, 0, 1, 4)\n+\n+#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA BIT(0)\n+#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(x) \\\n+\tFIELD_PREP(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)\n+#define DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_GET(x) \\\n+\tFIELD_GET(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA, x)\n+\n+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_CFG */\n+#define DEV2G5_PCS1G_ANEG_CFG(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 12, 0, 1, 4)\n+\n+#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY GENMASK(31, 16)\n+#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(x) \\\n+\tFIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)\n+#define DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_GET(x) \\\n+\tFIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY, x)\n+\n+#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA BIT(8)\n+#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(x) \\\n+\tFIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)\n+#define DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_GET(x) \\\n+\tFIELD_GET(DEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA, x)\n+\n+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT BIT(1)\n+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(x) \\\n+\tFIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)\n+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_GET(x) \\\n+\tFIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT, x)\n+\n+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA BIT(0)\n+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(x) \\\n+\tFIELD_PREP(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)\n+#define DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_GET(x) \\\n+\tFIELD_GET(DEV2G5_PCS1G_ANEG_CFG_ANEG_ENA, x)\n+\n+/* DEV1G:MAC_CFG_STATUS:MAC_IFG_CFG */\n+#define DEV2G5_MAC_IFG_CFG(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 52, 0, 1, 36, 24, 0, 1, 4)\n+\n+#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK BIT(17)\n+#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_SET(x) \\\n+\tFIELD_PREP(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)\n+#define DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK_GET(x) \\\n+\tFIELD_GET(DEV2G5_MAC_IFG_CFG_RESTORE_OLD_IPG_CHECK, x)\n+\n+#define DEV2G5_MAC_IFG_CFG_TX_IFG GENMASK(12, 8)\n+#define DEV2G5_MAC_IFG_CFG_TX_IFG_SET(x) \\\n+\tFIELD_PREP(DEV2G5_MAC_IFG_CFG_TX_IFG, x)\n+#define DEV2G5_MAC_IFG_CFG_TX_IFG_GET(x) FIELD_GET(DEV2G5_MAC_IFG_CFG_TX_IFG, x)\n+\n+#define DEV2G5_MAC_IFG_CFG_RX_IFG2 GENMASK(7, 4)\n+#define DEV2G5_MAC_IFG_CFG_RX_IFG2_SET(x) \\\n+\tFIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)\n+#define DEV2G5_MAC_IFG_CFG_RX_IFG2_GET(x) \\\n+\tFIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG2, x)\n+\n+#define DEV2G5_MAC_IFG_CFG_RX_IFG1 GENMASK(3, 0)\n+#define DEV2G5_MAC_IFG_CFG_RX_IFG1_SET(x) \\\n+\tFIELD_PREP(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)\n+#define DEV2G5_MAC_IFG_CFG_RX_IFG1_GET(x) \\\n+\tFIELD_GET(DEV2G5_MAC_IFG_CFG_RX_IFG1, x)\n+\n+/* LRN:COMMON:COMMON_ACCESS_CTRL */\n+#define LRN_COMMON_ACCESS_CTRL __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 0, 0, 1, 4)\n+\n+#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD GENMASK(4, 1)\n+#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(x) \\\n+\tFIELD_PREP(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)\n+#define LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_GET(x) \\\n+\tFIELD_GET(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD, x)\n+\n+#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT BIT(0)\n+#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(x) \\\n+\tFIELD_PREP(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)\n+#define LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_GET(x) \\\n+\tFIELD_GET(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT, x)\n+\n+/* LRN:COMMON:MAC_ACCESS_CFG_0 */\n+#define LRN_MAC_ACCESS_CFG_0 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 4, 0, 1, 4)\n+\n+/* LRN:COMMON:MAC_ACCESS_CFG_1 */\n+#define LRN_MAC_ACCESS_CFG_1 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 8, 0, 1, 4)\n+\n+/* LRN:COMMON:MAC_ACCESS_CFG_2 */\n+#define LRN_MAC_ACCESS_CFG_2 __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 12, 0, 1, 4)\n+\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU GENMASK(26, 24)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(x) \\\n+\tFIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_GET(x) \\\n+\tFIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU, x)\n+\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY BIT(23)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(x) \\\n+\tFIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_GET(x) \\\n+\tFIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY, x)\n+\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED BIT(16)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(x) \\\n+\tFIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_GET(x) \\\n+\tFIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED, x)\n+\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD BIT(15)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(x) \\\n+\tFIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_GET(x) \\\n+\tFIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD, x)\n+\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE GENMASK(14, 12)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(x) \\\n+\tFIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_GET(x) \\\n+\tFIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE, x)\n+\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR GENMASK(11, 0)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(x) \\\n+\tFIELD_PREP(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)\n+#define LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_GET(x) \\\n+\tFIELD_GET(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR, x)\n+\n+#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX GENMASK(10, 0)\n+#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_SET(x) \\\n+\tFIELD_PREP(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)\n+#define LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX_GET(x) \\\n+\tFIELD_GET(LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX, x)\n+\n+/* LRN:COMMON:SCAN_NEXT_CFG */\n+#define LRN_SCAN_NEXT_CFG __REG(TARGET_LRN, 0, 1, 0, 0, 1, 72, 20, 0, 1, 4)\n+\n+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA BIT(10)\n+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(x) \\\n+\tFIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)\n+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_GET(x) \\\n+\tFIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA, x)\n+\n+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA BIT(7)\n+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(x) \\\n+\tFIELD_PREP(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)\n+#define LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_GET(x) \\\n+\tFIELD_GET(LRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA, x)\n+\n+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_LINK_STATUS */\n+#define DEV2G5_PCS1G_LINK_STATUS(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 40, 0, 1, 4)\n+\n+#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS BIT(4)\n+#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_SET(x) \\\n+\tFIELD_PREP(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)\n+#define DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(x) \\\n+\tFIELD_GET(DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS, x)\n+\n+/* DEV1G:PCS1G_CFG_STATUS:PCS1G_ANEG_STATUS */\n+#define DEV2G5_PCS1G_ANEG_STATUS(t) \\\n+\t__REG(TARGET_DEV2G5, t, 65, 88, 0, 1, 68, 32, 0, 1, 4)\n+\n+#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE BIT(0)\n+#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_SET(x) \\\n+\tFIELD_PREP(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)\n+#define DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE_GET(x) \\\n+\tFIELD_GET(DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE, x)\n+\n+/*      CPU:CPU_REGS:RESET_PROT_STAT */\n+#define CPU_RESET_PROT_STAT       __REG(TARGET_CPU, 0, 1, 0, 0, 1, 204, \\\n+\t\t\t\t\tREG_ADDR(RA_CPU_RESET_PROT_STAT), 0, 1, 4)\n+\n+#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE   FIELD_ADDR(FIELD_CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE)\n+#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_SET(x)\\\n+\tFIELD_PREP(CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE, x)\n+#define CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE_GET(x)\\\n+\tFIELD_GET(CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE, x)\n+\n+/*      DEVCPU_GCB:CHIP_REGS:SOFT_RST */\n+#define GCB_SOFT_RST              __REG(TARGET_GCB, 0, 1, 0, 0, 1, 424, \\\n+\t\t\t\t\tREG_ADDR(RA_GCB_SOFT_RST), 0, 1, 4)\n+\n+#define GCB_SOFT_RST_SOFT_CHIP_RST               BIT(0)\n+#define GCB_SOFT_RST_SOFT_CHIP_RST_SET(x)\\\n+\tFIELD_PREP(GCB_SOFT_RST_SOFT_CHIP_RST, x)\n+#define GCB_SOFT_RST_SOFT_CHIP_RST_GET(x)\\\n+\tFIELD_GET(GCB_SOFT_RST_SOFT_CHIP_RST, x)\n+\n+/* HSIOWRAP:XMII_CFG: */\n+#define HSIO_WRAP_XMII_CFG(g)     __REG(TARGET_HSIO, 0, 1, 116, g, 2, 20, 0, 0, 1, 4)\n+\n+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG         GENMASK(2, 1)\n+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(x)\\\n+\tFIELD_PREP(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)\n+#define HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_GET(x)\\\n+\tFIELD_GET(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG, x)\n+\n+/* HSIOWRAP:XMII_CFG: */\n+#define HSIO_WRAP_RGMII_CFG(g)    __REG(TARGET_HSIO, 0, 1, 116, g, 2, 20, 4, 0, 1, 4)\n+\n+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG           GENMASK(4, 2)\n+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(x)\\\n+\tFIELD_PREP(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)\n+#define HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_GET(x)\\\n+\tFIELD_GET(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG, x)\n+\n+/* HSIOWRAP:XMII_CFG: */\n+#define HSIO_WRAP_DLL_CFG(g, r)   __REG(TARGET_HSIO, 0, 1, 116, g, 2, 20, 12, r, 2, 4)\n+\n+#define HSIO_WRAP_DLL_CFG_DLL_ENA                BIT(19)\n+#define HSIO_WRAP_DLL_CFG_DLL_ENA_SET(x)\\\n+\tFIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_ENA, x)\n+#define HSIO_WRAP_DLL_CFG_DLL_ENA_GET(x)\\\n+\tFIELD_GET(HSIO_WRAP_DLL_CFG_DLL_ENA, x)\n+\n+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA            BIT(18)\n+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(x)\\\n+\tFIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)\n+#define HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_GET(x)\\\n+\tFIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_ENA, x)\n+\n+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL            GENMASK(17, 15)\n+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(x)\\\n+\tFIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)\n+#define HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_GET(x)\\\n+\tFIELD_GET(HSIO_WRAP_DLL_CFG_DLL_CLK_SEL, x)\n+\n+#define HSIO_WRAP_DLL_CFG_DLL_RST                BIT(0)\n+#define HSIO_WRAP_DLL_CFG_DLL_RST_SET(x)\\\n+\tFIELD_PREP(HSIO_WRAP_DLL_CFG_DLL_RST, x)\n+#define HSIO_WRAP_DLL_CFG_DLL_RST_GET(x)\\\n+\tFIELD_GET(HSIO_WRAP_DLL_CFG_DLL_RST, x)\n+\n+/* DEV1G:DEV_CFG_STATUS: */\n+#define DEVRGMII_DEV_RST_CTRL(t)  __REG(TARGET_DEV2G5, t, 2, 0, 0, 1, 36, 0, 0, 1, 4)\n+\n+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL          GENMASK(22, 20)\n+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(x)\\\n+\tFIELD_PREP(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)\n+#define DEVRGMII_DEV_RST_CTRL_SPEED_SEL_GET(x)\\\n+\tFIELD_GET(DEVRGMII_DEV_RST_CTRL_SPEED_SEL, x)\n+\n+/* DEV1G:MAC_CFG_STATUS: */\n+#define DEVRGMII_MAC_IFG_CFG(t)   __REG(TARGET_DEV2G5, t, 2, 36, 0, 1, 36, 24, 0, 1, 4)\n+\n+#define DEVRGMII_MAC_IFG_CFG_TX_IFG              GENMASK(12, 8)\n+#define DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(x)\\\n+\tFIELD_PREP(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)\n+#define DEVRGMII_MAC_IFG_CFG_TX_IFG_GET(x)\\\n+\tFIELD_GET(DEVRGMII_MAC_IFG_CFG_TX_IFG, x)\n+\n+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2             GENMASK(7, 4)\n+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(x)\\\n+\tFIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)\n+#define DEVRGMII_MAC_IFG_CFG_RX_IFG2_GET(x)\\\n+\tFIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG2, x)\n+\n+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1             GENMASK(3, 0)\n+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(x)\\\n+\tFIELD_PREP(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)\n+#define DEVRGMII_MAC_IFG_CFG_RX_IFG1_GET(x)\\\n+\tFIELD_GET(DEVRGMII_MAC_IFG_CFG_RX_IFG1, x)\n+\n+/* DEV1G:MAC_CFG_STATUS: */\n+#define DEVRGMII_MAC_ENA_CFG(t)   __REG(TARGET_DEV2G5, t, 2, 36, 0, 1, 36, 0, 0, 1, 4)\n+\n+#define DEVRGMII_MAC_ENA_CFG_RX_ENA              BIT(4)\n+#define DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(x)\\\n+\tFIELD_PREP(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)\n+#define DEVRGMII_MAC_ENA_CFG_RX_ENA_GET(x)\\\n+\tFIELD_GET(DEVRGMII_MAC_ENA_CFG_RX_ENA, x)\n+\n+#define DEVRGMII_MAC_ENA_CFG_TX_ENA              BIT(0)\n+#define DEVRGMII_MAC_ENA_CFG_TX_ENA_SET(x)\\\n+\tFIELD_PREP(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)\n+#define DEVRGMII_MAC_ENA_CFG_TX_ENA_GET(x)\\\n+\tFIELD_GET(DEVRGMII_MAC_ENA_CFG_TX_ENA, x)\n+\n+/* DEVCPU_GCB:SIO_CTRL:SIO_CFG */\n+#define GCB_SIO_CFG(g)                                                      \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 16, 0, 1, 4)\n+\n+/* DEVCPU_GCB:SIO_CTRL:SIO_CLOCK */\n+#define GCB_SIO_CLOCK(g)                                                    \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 20, 0, 1, 4)\n+\n+/* DEVCPU_GCB:SIO_CTRL:SIO_PORT_ENA */\n+#define GCB_SIO_PORT_ENA(g)                                                 \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 152, 0, 1, 4)\n+\n+/* DEVCPU_GCB:SIO_CTRL:SIO_INTR_POL */\n+#define GCB_SIO_INTR_POL(g, r)                                              \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 168, r, 4, 4)\n+\n+/* DEVCPU_GCB:SIO_CTRL:SIO_PORT_CFG */\n+#define GCB_SIO_PORT_CFG(g, r)                                              \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_SIO_CTRL), g, GRP_CNT(GC_GCB_SIO_CTRL), 280, 24, r, 32, 4)\n+\n+/* DEVCPU_GCB:GPIO:GPIO_OE */\n+#define GCB_GPIO_OE                                                         \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_GPIO), 0, 1, GRP_SIZE(GW_GCB_GPIO), REG_ADDR(RA_GCB_GPIO_OE), 0, 1, 4)\n+\n+/* DEVCPU_GCB:GPIO:GPIO_OUT_CLR */\n+#define GCB_GPIO_OUT_CLR                                                    \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_GPIO), 0, 1, GRP_SIZE(GW_GCB_GPIO), REG_ADDR(RA_GCB_GPIO_OUT_CLR), 0, 1, 4)\n+\n+/* DEVCPU_GCB:GPIO:GPIO_OUT_SET */\n+#define GCB_GPIO_OUT_SET                                                    \\\n+\t__REG(TARGET_GCB, 0, 1, GRP_ADDR(GA_GCB_GPIO), 0, 1, GRP_SIZE(GW_GCB_GPIO), 0, 0, 1, 4)\n+\n+/*      DEVCPU_PTP:PTP_CFG:PTP_DOM_CFG */\n+#define PTP_PTP_DOM_CFG                                                     \\\n+\t__REG(TARGET_PTP, 0, 1, GRP_ADDR(GA_PTP_PTP_CFG), 0, 1, 16, 12, 0, 1, 4)\n+\n+#define PTP_PTP_DOM_CFG_PTP_ENA                  GENMASK(11, 9)\n+#define PTP_PTP_DOM_CFG_PTP_ENA_SET(x)\\\n+\tFIELD_PREP(PTP_PTP_DOM_CFG_PTP_ENA, x)\n+#define PTP_PTP_DOM_CFG_PTP_ENA_GET(x)\\\n+\tFIELD_GET(PTP_PTP_DOM_CFG_PTP_ENA, x)\n+\n+/*      DEVCPU_PTP:PTP_TOD_DOMAINS:CLK_PER_CFG */\n+#define PTP_CLK_PER_CFG(g, r)                                               \\\n+\t__REG(TARGET_PTP, 0, 1, GRP_ADDR(GA_PTP_PTP_TOD_DOMAINS), g, 3, 28, 0, r, 2, 4)\n+\n+/*      DSM:CFG:TAXI_CAL_CFG */\n+#define DSM_TAXI_CAL_CFG(r)                                                 \\\n+\t__REG(TARGET_DSM, 0, 1, 20, 0, 1, 3528, 3224, r, 9, 4)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT            BIT(23)\n+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)\n+#define DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_SEL_STAT, x)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_SWITCH              BIT(22)\n+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)\n+#define DSM_TAXI_CAL_CFG_CAL_SWITCH_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_SWITCH, x)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL             BIT(21)\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_SEL_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_SEL, x)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_IDX                 GENMASK(20, 15)\n+#define DSM_TAXI_CAL_CFG_CAL_IDX_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_IDX, x)\n+#define DSM_TAXI_CAL_CFG_CAL_IDX_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_IDX, x)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN             GENMASK(14, 9)\n+#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)\n+#define DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_LEN, x)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL             GENMASK(8, 5)\n+#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)\n+#define DSM_TAXI_CAL_CFG_CAL_CUR_VAL_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_CUR_VAL, x)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL             GENMASK(4, 1)\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_VAL_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_VAL, x)\n+\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA             BIT(0)\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(x)\\\n+\tFIELD_PREP(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)\n+#define DSM_TAXI_CAL_CFG_CAL_PGM_ENA_GET(x)\\\n+\tFIELD_GET(DSM_TAXI_CAL_CFG_CAL_PGM_ENA, x)\ndiff --git a/drivers/net/mscc_eswitch/sparx5_serdes.c b/drivers/net/mscc_eswitch/sparx5_serdes.c\nnew file mode 100644\nindex 00000000000..9ea959fde8c\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_serdes.c\n@@ -0,0 +1,2703 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/* Microchip Sparx5 Switch SerDes driver\n+ *\n+ * Copyright (c) 2020 Microchip Technology Inc. and its subsidiaries.\n+ *\n+ * The Sparx5 Chip Register Model can be browsed at this location:\n+ * https://github.com/microchip-ung/sparx-5_reginfo\n+ * and the datasheet is available here:\n+ * https://ww1.microchip.com/downloads/en/DeviceDoc/SparX-5_Family_L2L3_Enterprise_10G_Ethernet_Switches_Datasheet_00003822B.pdf\n+ */\n+\n+#include <clk.h>\n+#include <linux/delay.h>\n+#include <linux/ethtool.h>\n+#include <linux/io.h>\n+#include <linux/netdevice.h>\n+#include <linux/printk.h>\n+#include <dm/devres.h>\n+#include <dm/device_compat.h>\n+#include <dm/device.h>\n+#include <dm/read.h>\n+\n+#include <dt-bindings/mscc/sparx5_data.h>\n+\n+#include \"sparx5_switch.h\"\n+#include \"sparx5_serdes.h\"\n+#include \"sparx5_serdes_priv.h\"\n+\n+/**\n+ * phy_modes - map phy_interface_t enum to device tree binding of phy-mode\n+ * @interface: enum phy_interface_t value\n+ *\n+ * Description: maps enum &phy_interface_t defined in this file\n+ * into the device tree binding of 'phy-mode', so that Ethernet\n+ * device driver can get PHY interface from device tree.\n+ */\n+static inline const char *phy_modes(phy_interface_t interface)\n+{\n+\tswitch (interface) {\n+\tcase PHY_INTERFACE_MODE_NA:\n+\t\treturn \"\";\n+\tcase PHY_INTERFACE_MODE_INTERNAL:\n+\t\treturn \"internal\";\n+\tcase PHY_INTERFACE_MODE_MII:\n+\t\treturn \"mii\";\n+\tcase PHY_INTERFACE_MODE_GMII:\n+\t\treturn \"gmii\";\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\treturn \"sgmii\";\n+\tcase PHY_INTERFACE_MODE_TBI:\n+\t\treturn \"tbi\";\n+\tcase PHY_INTERFACE_MODE_REVMII:\n+\t\treturn \"rev-mii\";\n+\tcase PHY_INTERFACE_MODE_RMII:\n+\t\treturn \"rmii\";\n+\tcase PHY_INTERFACE_MODE_REVRMII:\n+\t\treturn \"rev-rmii\";\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\treturn \"rgmii\";\n+\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\treturn \"rgmii-id\";\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\t\treturn \"rgmii-rxid\";\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\t\treturn \"rgmii-txid\";\n+\tcase PHY_INTERFACE_MODE_RTBI:\n+\t\treturn \"rtbi\";\n+\tcase PHY_INTERFACE_MODE_SMII:\n+\t\treturn \"smii\";\n+\tcase PHY_INTERFACE_MODE_XGMII:\n+\t\treturn \"xgmii\";\n+\tcase PHY_INTERFACE_MODE_XLGMII:\n+\t\treturn \"xlgmii\";\n+\tcase PHY_INTERFACE_MODE_MOCA:\n+\t\treturn \"moca\";\n+\tcase PHY_INTERFACE_MODE_QSGMII:\n+\t\treturn \"qsgmii\";\n+\tcase PHY_INTERFACE_MODE_TRGMII:\n+\t\treturn \"trgmii\";\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\t\treturn \"1000base-x\";\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\treturn \"2500base-x\";\n+\tcase PHY_INTERFACE_MODE_5GBASER:\n+\t\treturn \"5gbase-r\";\n+\tcase PHY_INTERFACE_MODE_RXAUI:\n+\t\treturn \"rxaui\";\n+\tcase PHY_INTERFACE_MODE_XAUI:\n+\t\treturn \"xaui\";\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\treturn \"10gbase-r\";\n+\tcase PHY_INTERFACE_MODE_25GBASER:\n+\t\treturn \"25gbase-r\";\n+\tcase PHY_INTERFACE_MODE_USXGMII:\n+\t\treturn \"usxgmii\";\n+\tcase PHY_INTERFACE_MODE_10GKR:\n+\t\treturn \"10gbase-kr\";\n+\tcase PHY_INTERFACE_MODE_100BASEX:\n+\t\treturn \"100base-x\";\n+\tcase PHY_INTERFACE_MODE_QUSGMII:\n+\t\treturn \"qusgmii\";\n+\tdefault:\n+\t\treturn \"unknown\";\n+\t}\n+}\n+\n+// It is not clear why the SPEED_5000 is not seen inside <linux/ethtool.h> but\n+// all the other macros as seen\n+#define SPEED_5000 5000\n+\n+#define SPX5_SERDES_10G_START 13\n+#define SPX5_SERDES_25G_START 25\n+#define SPX5_SERDES_25G_CNT   8\n+\n+/* Optimal power settings from GUC */\n+#define SPX5_SERDES_QUIET_MODE_VAL 0x1EF4E0C\n+\n+const unsigned int sparx5_serdes_tsize[TSIZE_LAST] = {\n+\t[TC_SD10G_LANE] = 12,\n+\t[TC_SD_CMU] = 14,\n+\t[TC_SD_CMU_CFG] = 14,\n+\t[TC_SD_LANE] = 25,\n+};\n+\n+const unsigned int lan969x_serdes_tsize[TSIZE_LAST] = {\n+\t[TC_SD10G_LANE] = 10,\n+\t[TC_SD_CMU] = 6,\n+\t[TC_SD_CMU_CFG] = 6,\n+\t[TC_SD_LANE] = 10,\n+};\n+\n+enum sparx5_sd25g28_mode_preset_type {\n+\tSPX5_SD25G28_MODE_PRESET_25000,\n+\tSPX5_SD25G28_MODE_PRESET_10000,\n+\tSPX5_SD25G28_MODE_PRESET_5000,\n+\tSPX5_SD25G28_MODE_PRESET_SD_2G5,\n+\tSPX5_SD25G28_MODE_PRESET_1000BASEX,\n+};\n+\n+enum sparx5_sd10g28_mode_preset_type {\n+\tSPX5_SD10G28_MODE_PRESET_10000,\n+\tSPX5_SD10G28_MODE_PRESET_SFI_5000_6G,\n+\tSPX5_SD10G28_MODE_PRESET_SFI_5000_10G,\n+\tSPX5_SD10G28_MODE_PRESET_QSGMII,\n+\tSPX5_SD10G28_MODE_PRESET_SD_2G5,\n+\tSPX5_SD10G28_MODE_PRESET_1000BASEX,\n+};\n+\n+struct sparx5_sd25g28_mode_preset {\n+\tu8 bitwidth;\n+\tu8 tx_pre_div;\n+\tu8 fifo_ck_div;\n+\tu8 pre_divsel;\n+\tu8 vco_div_mode;\n+\tu8 sel_div;\n+\tu8 ck_bitwidth;\n+\tu8 subrate;\n+\tu8 com_txcal_en;\n+\tu8 com_tx_reserve_msb;\n+\tu8 com_tx_reserve_lsb;\n+\tu8 cfg_itx_ipcml_base;\n+\tu8 tx_reserve_lsb;\n+\tu8 tx_reserve_msb;\n+\tu8 bw;\n+\tu8 rxterm;\n+\tu8 dfe_tap;\n+\tu8 dfe_enable;\n+\tbool txmargin;\n+\tu8 cfg_ctle_rstn;\n+\tu8 r_dfe_rstn;\n+\tu8 cfg_pi_bw_3_0;\n+\tu8 tx_tap_dly;\n+\tu8 tx_tap_adv;\n+};\n+\n+struct sparx5_sd25g28_media_preset {\n+\tu8 cfg_eq_c_force_3_0;\n+\tu8 cfg_vga_ctrl_byp_4_0;\n+\tu8 cfg_eq_r_force_3_0;\n+\tu8 cfg_en_adv;\n+\tu8 cfg_en_main;\n+\tu8 cfg_en_dly;\n+\tu8 cfg_tap_adv_3_0;\n+\tu8 cfg_tap_main;\n+\tu8 cfg_tap_dly_4_0;\n+\tu8 cfg_alos_thr_2_0;\n+};\n+\n+struct sparx5_sd25g28_args {\n+\tu8 if_width; /* UDL if-width: 10/16/20/32/64 */\n+\tbool skip_cmu_cfg:1; /* Enable/disable CMU cfg */\n+\tenum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */\n+\tbool no_pwrcycle:1; /* Omit initial power-cycle */\n+\tbool txinvert:1; /* Enable inversion of output data */\n+\tbool rxinvert:1; /* Enable inversion of input data */\n+\tu16 txswing; /* Set output level */\n+\tu8 rate; /* Rate of network interface */\n+\tu8 pi_bw_gen1;\n+\tu8 duty_cycle; /* Set output level to  half/full */\n+\tbool mute:1; /* Mute Output Buffer */\n+\tbool reg_rst:1;\n+\tu8 com_pll_reserve;\n+};\n+\n+struct sparx5_sd25g28_params {\n+\tu8 reg_rst;\n+\tu8 cfg_jc_byp;\n+\tu8 cfg_common_reserve_7_0;\n+\tu8 r_reg_manual;\n+\tu8 r_d_width_ctrl_from_hwt;\n+\tu8 r_d_width_ctrl_2_0;\n+\tu8 r_txfifo_ck_div_pmad_2_0;\n+\tu8 r_rxfifo_ck_div_pmad_2_0;\n+\tu8 cfg_pll_lol_set;\n+\tu8 cfg_vco_div_mode_1_0;\n+\tu8 cfg_pre_divsel_1_0;\n+\tu8 cfg_sel_div_3_0;\n+\tu8 cfg_vco_start_code_3_0;\n+\tu8 cfg_pma_tx_ck_bitwidth_2_0;\n+\tu8 cfg_tx_prediv_1_0;\n+\tu8 cfg_rxdiv_sel_2_0;\n+\tu8 cfg_tx_subrate_2_0;\n+\tu8 cfg_rx_subrate_2_0;\n+\tu8 r_multi_lane_mode;\n+\tu8 cfg_cdrck_en;\n+\tu8 cfg_dfeck_en;\n+\tu8 cfg_dfe_pd;\n+\tu8 cfg_dfedmx_pd;\n+\tu8 cfg_dfetap_en_5_1;\n+\tu8 cfg_dmux_pd;\n+\tu8 cfg_dmux_clk_pd;\n+\tu8 cfg_erramp_pd;\n+\tu8 cfg_pi_dfe_en;\n+\tu8 cfg_pi_en;\n+\tu8 cfg_pd_ctle;\n+\tu8 cfg_summer_en;\n+\tu8 cfg_pmad_ck_pd;\n+\tu8 cfg_pd_clk;\n+\tu8 cfg_pd_cml;\n+\tu8 cfg_pd_driver;\n+\tu8 cfg_rx_reg_pu;\n+\tu8 cfg_pd_rms_det;\n+\tu8 cfg_dcdr_pd;\n+\tu8 cfg_ecdr_pd;\n+\tu8 cfg_pd_sq;\n+\tu8 cfg_itx_ipdriver_base_2_0;\n+\tu8 cfg_tap_dly_4_0;\n+\tu8 cfg_tap_main;\n+\tu8 cfg_en_main;\n+\tu8 cfg_tap_adv_3_0;\n+\tu8 cfg_en_adv;\n+\tu8 cfg_en_dly;\n+\tu8 cfg_iscan_en;\n+\tu8 l1_pcs_en_fast_iscan;\n+\tu8 l0_cfg_bw_1_0;\n+\tu8 l0_cfg_txcal_en;\n+\tu8 cfg_en_dummy;\n+\tu8 cfg_pll_reserve_3_0;\n+\tu8 l0_cfg_tx_reserve_15_8;\n+\tu8 l0_cfg_tx_reserve_7_0;\n+\tu8 cfg_tx_reserve_15_8;\n+\tu8 cfg_tx_reserve_7_0;\n+\tu8 cfg_bw_1_0;\n+\tu8 cfg_txcal_man_en;\n+\tu8 cfg_phase_man_4_0;\n+\tu8 cfg_quad_man_1_0;\n+\tu8 cfg_txcal_shift_code_5_0;\n+\tu8 cfg_txcal_valid_sel_3_0;\n+\tu8 cfg_txcal_en;\n+\tu8 cfg_cdr_kf_2_0;\n+\tu8 cfg_cdr_m_7_0;\n+\tu8 cfg_pi_bw_3_0;\n+\tu8 cfg_pi_steps_1_0;\n+\tu8 cfg_dis_2ndorder;\n+\tu8 cfg_ctle_rstn;\n+\tu8 r_dfe_rstn;\n+\tu8 cfg_alos_thr_2_0;\n+\tu8 cfg_itx_ipcml_base_1_0;\n+\tu8 cfg_rx_reserve_7_0;\n+\tu8 cfg_rx_reserve_15_8;\n+\tu8 cfg_rxterm_2_0;\n+\tu8 cfg_fom_selm;\n+\tu8 cfg_rx_sp_ctle_1_0;\n+\tu8 cfg_isel_ctle_1_0;\n+\tu8 cfg_vga_ctrl_byp_4_0;\n+\tu8 cfg_vga_byp;\n+\tu8 cfg_agc_adpt_byp;\n+\tu8 cfg_eqr_byp;\n+\tu8 cfg_eqr_force_3_0;\n+\tu8 cfg_eqc_force_3_0;\n+\tu8 cfg_sum_setcm_en;\n+\tu8 cfg_init_pos_iscan_6_0;\n+\tu8 cfg_init_pos_ipi_6_0;\n+\tu8 cfg_dfedig_m_2_0;\n+\tu8 cfg_en_dfedig;\n+\tu8 cfg_pi_DFE_en;\n+\tu8 cfg_tx2rx_lp_en;\n+\tu8 cfg_txlb_en;\n+\tu8 cfg_rx2tx_lp_en;\n+\tu8 cfg_rxlb_en;\n+\tu8 r_tx_pol_inv;\n+\tu8 r_rx_pol_inv;\n+};\n+\n+struct sparx5_sd10g28_media_preset {\n+\tu8 cfg_en_adv;\n+\tu8 cfg_en_main;\n+\tu8 cfg_en_dly;\n+\tu8 cfg_tap_adv_3_0;\n+\tu8 cfg_tap_main;\n+\tu8 cfg_tap_dly_4_0;\n+\tu8 cfg_vga_ctrl_3_0;\n+\tu8 cfg_vga_cp_2_0;\n+\tu8 cfg_eq_res_3_0;\n+\tu8 cfg_eq_r_byp;\n+\tu8 cfg_eq_c_force_3_0;\n+\tu8 cfg_alos_thr_3_0;\n+};\n+\n+struct sparx5_sd10g28_mode_preset {\n+\tu8 bwidth; /* interface width: 10/16/20/32/64 */\n+\tenum sparx5_10g28cmu_mode cmu_sel; /* Device/Mode serdes uses */\n+\tu8 rate; /* Rate of network interface */\n+\tu8 dfe_tap;\n+\tu8 dfe_enable;\n+\tu8 pi_bw_gen1;\n+\tu8 duty_cycle; /* Set output level to  half/full */\n+};\n+\n+struct sparx5_sd10g28_args {\n+\tbool skip_cmu_cfg:1; /* Enable/disable CMU cfg */\n+\tbool no_pwrcycle:1; /* Omit initial power-cycle */\n+\tbool txinvert:1; /* Enable inversion of output data */\n+\tbool rxinvert:1; /* Enable inversion of input data */\n+\tbool txmargin:1; /* Set output level to  half/full */\n+\tu16 txswing; /* Set output level */\n+\tbool mute:1; /* Mute Output Buffer */\n+\tbool is_6g:1;\n+\tbool reg_rst:1;\n+};\n+\n+struct sparx5_sd10g28_params {\n+\tu8 cmu_sel;\n+\tu8 is_6g;\n+\tu8 skip_cmu_cfg;\n+\tu8 cfg_lane_reserve_7_0;\n+\tu8 cfg_ssc_rtl_clk_sel;\n+\tu8 cfg_lane_reserve_15_8;\n+\tu8 cfg_txrate_1_0;\n+\tu8 cfg_rxrate_1_0;\n+\tu8 r_d_width_ctrl_2_0;\n+\tu8 cfg_pma_tx_ck_bitwidth_2_0;\n+\tu8 cfg_rxdiv_sel_2_0;\n+\tu8 r_pcs2pma_phymode_4_0;\n+\tu8 cfg_lane_id_2_0;\n+\tu8 cfg_cdrck_en;\n+\tu8 cfg_dfeck_en;\n+\tu8 cfg_dfe_pd;\n+\tu8 cfg_dfetap_en_5_1;\n+\tu8 cfg_erramp_pd;\n+\tu8 cfg_pi_DFE_en;\n+\tu8 cfg_pi_en;\n+\tu8 cfg_pd_ctle;\n+\tu8 cfg_summer_en;\n+\tu8 cfg_pd_rx_cktree;\n+\tu8 cfg_pd_clk;\n+\tu8 cfg_pd_cml;\n+\tu8 cfg_pd_driver;\n+\tu8 cfg_rx_reg_pu;\n+\tu8 cfg_d_cdr_pd;\n+\tu8 cfg_pd_sq;\n+\tu8 cfg_rxdet_en;\n+\tu8 cfg_rxdet_str;\n+\tu8 r_multi_lane_mode;\n+\tu8 cfg_en_adv;\n+\tu8 cfg_en_main;\n+\tu8 cfg_en_dly;\n+\tu8 cfg_tap_adv_3_0;\n+\tu8 cfg_tap_main;\n+\tu8 cfg_tap_dly_4_0;\n+\tu8 cfg_vga_ctrl_3_0;\n+\tu8 cfg_vga_cp_2_0;\n+\tu8 cfg_eq_res_3_0;\n+\tu8 cfg_eq_r_byp;\n+\tu8 cfg_eq_c_force_3_0;\n+\tu8 cfg_en_dfedig;\n+\tu8 cfg_sum_setcm_en;\n+\tu8 cfg_en_preemph;\n+\tu8 cfg_itx_ippreemp_base_1_0;\n+\tu8 cfg_itx_ipdriver_base_2_0;\n+\tu8 cfg_ibias_tune_reserve_5_0;\n+\tu8 cfg_txswing_half;\n+\tu8 cfg_dis_2nd_order;\n+\tu8 cfg_rx_ssc_lh;\n+\tu8 cfg_pi_floop_steps_1_0;\n+\tu8 cfg_pi_ext_dac_23_16;\n+\tu8 cfg_pi_ext_dac_15_8;\n+\tu8 cfg_iscan_ext_dac_7_0;\n+\tu8 cfg_cdr_kf_gen1_2_0;\n+\tu8 cfg_cdr_kf_gen2_2_0;\n+\tu8 cfg_cdr_kf_gen3_2_0;\n+\tu8 cfg_cdr_kf_gen4_2_0;\n+\tu8 r_cdr_m_gen1_7_0;\n+\tu8 cfg_pi_bw_gen1_3_0;\n+\tu8 cfg_pi_bw_gen2;\n+\tu8 cfg_pi_bw_gen3;\n+\tu8 cfg_pi_bw_gen4;\n+\tu8 cfg_pi_ext_dac_7_0;\n+\tu8 cfg_pi_steps;\n+\tu8 cfg_mp_max_3_0;\n+\tu8 cfg_rstn_dfedig;\n+\tu8 cfg_alos_thr_3_0;\n+\tu8 cfg_predrv_slewrate_1_0;\n+\tu8 cfg_itx_ipcml_base_1_0;\n+\tu8 cfg_ip_pre_base_1_0;\n+\tu8 r_cdr_m_gen2_7_0;\n+\tu8 r_cdr_m_gen3_7_0;\n+\tu8 r_cdr_m_gen4_7_0;\n+\tu8 r_en_auto_cdr_rstn;\n+\tu8 cfg_oscal_afe;\n+\tu8 cfg_pd_osdac_afe;\n+\tu8 cfg_resetb_oscal_afe[2];\n+\tu8 cfg_center_spreading;\n+\tu8 cfg_m_cnt_maxval_4_0;\n+\tu8 cfg_ncnt_maxval_7_0;\n+\tu8 cfg_ncnt_maxval_10_8;\n+\tu8 cfg_ssc_en;\n+\tu8 cfg_tx2rx_lp_en;\n+\tu8 cfg_txlb_en;\n+\tu8 cfg_rx2tx_lp_en;\n+\tu8 cfg_rxlb_en;\n+\tu8 r_tx_pol_inv;\n+\tu8 r_rx_pol_inv;\n+\tu8 fx_100;\n+};\n+\n+static struct sparx5_sd25g28_media_preset media_presets_25g[] = {\n+\t{ /* ETH_MEDIA_DEFAULT */\n+\t\t.cfg_en_adv               = 0,\n+\t\t.cfg_en_main              = 1,\n+\t\t.cfg_en_dly               = 0,\n+\t\t.cfg_tap_adv_3_0          = 0,\n+\t\t.cfg_tap_main             = 1,\n+\t\t.cfg_tap_dly_4_0          = 0,\n+\t\t.cfg_eq_c_force_3_0       = 0xf,\n+\t\t.cfg_vga_ctrl_byp_4_0     = 4,\n+\t\t.cfg_eq_r_force_3_0       = 12,\n+\t\t.cfg_alos_thr_2_0         = 7,\n+\t},\n+\t{ /* ETH_MEDIA_SR */\n+\t\t.cfg_en_adv               = 1,\n+\t\t.cfg_en_main              = 1,\n+\t\t.cfg_en_dly               = 1,\n+\t\t.cfg_tap_adv_3_0          = 0,\n+\t\t.cfg_tap_main             = 1,\n+\t\t.cfg_tap_dly_4_0          = 0x10,\n+\t\t.cfg_eq_c_force_3_0       = 0xf,\n+\t\t.cfg_vga_ctrl_byp_4_0     = 8,\n+\t\t.cfg_eq_r_force_3_0       = 4,\n+\t\t.cfg_alos_thr_2_0         = 0,\n+\t},\n+\t{ /* ETH_MEDIA_DAC */\n+\t\t.cfg_en_adv               = 0,\n+\t\t.cfg_en_main              = 1,\n+\t\t.cfg_en_dly               = 0,\n+\t\t.cfg_tap_adv_3_0          = 0,\n+\t\t.cfg_tap_main             = 1,\n+\t\t.cfg_tap_dly_4_0          = 0,\n+\t\t.cfg_eq_c_force_3_0       = 0xf,\n+\t\t.cfg_vga_ctrl_byp_4_0     = 8,\n+\t\t.cfg_eq_r_force_3_0       = 0xc,\n+\t\t.cfg_alos_thr_2_0         = 0,\n+\t},\n+};\n+\n+static struct sparx5_sd25g28_mode_preset mode_presets_25g[] = {\n+\t{ /* SPX5_SD25G28_MODE_PRESET_25000 */\n+\t\t.bitwidth           = 40,\n+\t\t.tx_pre_div         = 0,\n+\t\t.fifo_ck_div        = 0,\n+\t\t.pre_divsel         = 1,\n+\t\t.vco_div_mode       = 0,\n+\t\t.sel_div            = 15,\n+\t\t.ck_bitwidth        = 3,\n+\t\t.subrate            = 0,\n+\t\t.com_txcal_en       = 0,\n+\t\t.com_tx_reserve_msb = (0x26 << 1),\n+\t\t.com_tx_reserve_lsb = 0xf0,\n+\t\t.cfg_itx_ipcml_base = 0,\n+\t\t.tx_reserve_msb     = 0xcc,\n+\t\t.tx_reserve_lsb     = 0xfe,\n+\t\t.bw                 = 3,\n+\t\t.rxterm             = 0,\n+\t\t.dfe_enable         = 1,\n+\t\t.dfe_tap            = 0x1f,\n+\t\t.txmargin           = 1,\n+\t\t.cfg_ctle_rstn      = 1,\n+\t\t.r_dfe_rstn         = 1,\n+\t\t.cfg_pi_bw_3_0      = 0,\n+\t\t.tx_tap_dly         = 8,\n+\t\t.tx_tap_adv         = 0xc,\n+\t},\n+\t{ /* SPX5_SD25G28_MODE_PRESET_10000 */\n+\t\t.bitwidth           = 64,\n+\t\t.tx_pre_div         = 0,\n+\t\t.fifo_ck_div        = 2,\n+\t\t.pre_divsel         = 0,\n+\t\t.vco_div_mode       = 1,\n+\t\t.sel_div            = 9,\n+\t\t.ck_bitwidth        = 0,\n+\t\t.subrate            = 0,\n+\t\t.com_txcal_en       = 1,\n+\t\t.com_tx_reserve_msb = (0x20 << 1),\n+\t\t.com_tx_reserve_lsb = 0x40,\n+\t\t.cfg_itx_ipcml_base = 0,\n+\t\t.tx_reserve_msb     = 0x4c,\n+\t\t.tx_reserve_lsb     = 0x44,\n+\t\t.bw                 = 3,\n+\t\t.cfg_pi_bw_3_0      = 0,\n+\t\t.rxterm             = 3,\n+\t\t.dfe_enable         = 1,\n+\t\t.dfe_tap            = 0x1f,\n+\t\t.txmargin           = 0,\n+\t\t.cfg_ctle_rstn      = 1,\n+\t\t.r_dfe_rstn         = 1,\n+\t\t.tx_tap_dly         = 0,\n+\t\t.tx_tap_adv         = 0,\n+\t},\n+\t{ /* SPX5_SD25G28_MODE_PRESET_5000 */\n+\t\t.bitwidth           = 64,\n+\t\t.tx_pre_div         = 0,\n+\t\t.fifo_ck_div        = 2,\n+\t\t.pre_divsel         = 0,\n+\t\t.vco_div_mode       = 2,\n+\t\t.sel_div            = 9,\n+\t\t.ck_bitwidth        = 0,\n+\t\t.subrate            = 0,\n+\t\t.com_txcal_en       = 1,\n+\t\t.com_tx_reserve_msb = (0x20 << 1),\n+\t\t.com_tx_reserve_lsb = 0,\n+\t\t.cfg_itx_ipcml_base = 0,\n+\t\t.tx_reserve_msb     = 0xe,\n+\t\t.tx_reserve_lsb     = 0x80,\n+\t\t.bw                 = 0,\n+\t\t.rxterm             = 0,\n+\t\t.cfg_pi_bw_3_0      = 6,\n+\t\t.dfe_enable         = 0,\n+\t\t.dfe_tap            = 0,\n+\t\t.tx_tap_dly         = 0,\n+\t\t.tx_tap_adv         = 0,\n+\t},\n+\t{ /* SPX5_SD25G28_MODE_PRESET_SD_2G5 */\n+\t\t.bitwidth           = 10,\n+\t\t.tx_pre_div         = 0,\n+\t\t.fifo_ck_div        = 0,\n+\t\t.pre_divsel         = 0,\n+\t\t.vco_div_mode       = 1,\n+\t\t.sel_div            = 6,\n+\t\t.ck_bitwidth        = 3,\n+\t\t.subrate            = 2,\n+\t\t.com_txcal_en       = 1,\n+\t\t.com_tx_reserve_msb = (0x26 << 1),\n+\t\t.com_tx_reserve_lsb = (0xf << 4),\n+\t\t.cfg_itx_ipcml_base = 2,\n+\t\t.tx_reserve_msb     = 0x8,\n+\t\t.tx_reserve_lsb     = 0x8a,\n+\t\t.bw                 = 0,\n+\t\t.cfg_pi_bw_3_0      = 0,\n+\t\t.rxterm             = (1 << 2),\n+\t\t.dfe_enable         = 0,\n+\t\t.dfe_tap            = 0,\n+\t\t.tx_tap_dly         = 0,\n+\t\t.tx_tap_adv         = 0,\n+\t},\n+\t{ /* SPX5_SD25G28_MODE_PRESET_1000BASEX */\n+\t\t.bitwidth           = 10,\n+\t\t.tx_pre_div         = 0,\n+\t\t.fifo_ck_div        = 1,\n+\t\t.pre_divsel         = 0,\n+\t\t.vco_div_mode       = 1,\n+\t\t.sel_div            = 8,\n+\t\t.ck_bitwidth        = 3,\n+\t\t.subrate            = 3,\n+\t\t.com_txcal_en       = 1,\n+\t\t.com_tx_reserve_msb = (0x26 << 1),\n+\t\t.com_tx_reserve_lsb = 0xf0,\n+\t\t.cfg_itx_ipcml_base = 0,\n+\t\t.tx_reserve_msb     = 0x8,\n+\t\t.tx_reserve_lsb     = 0xce,\n+\t\t.bw                 = 0,\n+\t\t.rxterm             = 0,\n+\t\t.cfg_pi_bw_3_0      = 0,\n+\t\t.dfe_enable         = 0,\n+\t\t.dfe_tap            = 0,\n+\t\t.tx_tap_dly         = 0,\n+\t\t.tx_tap_adv         = 0,\n+\t},\n+};\n+\n+static struct sparx5_sd10g28_media_preset media_presets_10g[] = {\n+\t{ /* ETH_MEDIA_DEFAULT */\n+\t\t.cfg_en_adv               = 0,\n+\t\t.cfg_en_main              = 1,\n+\t\t.cfg_en_dly               = 0,\n+\t\t.cfg_tap_adv_3_0          = 0,\n+\t\t.cfg_tap_main             = 1,\n+\t\t.cfg_tap_dly_4_0          = 0,\n+\t\t.cfg_vga_ctrl_3_0         = 5,\n+\t\t.cfg_vga_cp_2_0           = 0,\n+\t\t.cfg_eq_res_3_0           = 0xa,\n+\t\t.cfg_eq_r_byp             = 1,\n+\t\t.cfg_eq_c_force_3_0       = 0x8,\n+\t\t.cfg_alos_thr_3_0         = 0x3,\n+\t},\n+\t{ /* ETH_MEDIA_SR */\n+\t\t.cfg_en_adv               = 1,\n+\t\t.cfg_en_main              = 1,\n+\t\t.cfg_en_dly               = 1,\n+\t\t.cfg_tap_adv_3_0          = 0,\n+\t\t.cfg_tap_main             = 1,\n+\t\t.cfg_tap_dly_4_0          = 0xc,\n+\t\t.cfg_vga_ctrl_3_0         = 0xa,\n+\t\t.cfg_vga_cp_2_0           = 0x4,\n+\t\t.cfg_eq_res_3_0           = 0xa,\n+\t\t.cfg_eq_r_byp             = 1,\n+\t\t.cfg_eq_c_force_3_0       = 0xF,\n+\t\t.cfg_alos_thr_3_0         = 0x3,\n+\t},\n+\t{ /* ETH_MEDIA_DAC */\n+\t\t.cfg_en_adv               = 1,\n+\t\t.cfg_en_main              = 1,\n+\t\t.cfg_en_dly               = 1,\n+\t\t.cfg_tap_adv_3_0          = 12,\n+\t\t.cfg_tap_main             = 1,\n+\t\t.cfg_tap_dly_4_0          = 8,\n+\t\t.cfg_vga_ctrl_3_0         = 0xa,\n+\t\t.cfg_vga_cp_2_0           = 4,\n+\t\t.cfg_eq_res_3_0           = 0xa,\n+\t\t.cfg_eq_r_byp             = 1,\n+\t\t.cfg_eq_c_force_3_0       = 0xf,\n+\t\t.cfg_alos_thr_3_0         = 0x0,\n+\t}\n+};\n+\n+static struct sparx5_sd10g28_mode_preset mode_presets_10g[] = {\n+\t{ /* SPX5_SD10G28_MODE_PRESET_10000 */\n+\t\t.bwidth           = 64,\n+\t\t.cmu_sel          = SPX5_SD10G28_CMU_MAIN,\n+\t\t.rate             = 0x0,\n+\t\t.dfe_enable       = 1,\n+\t\t.dfe_tap          = 0x1f,\n+\t\t.pi_bw_gen1       = 0x0,\n+\t\t.duty_cycle       = 0x2,\n+\t},\n+\t{ /* SPX5_SD10G28_MODE_PRESET_SFI_5000_6G */\n+\t\t.bwidth           = 16,\n+\t\t.cmu_sel          = SPX5_SD10G28_CMU_MAIN,\n+\t\t.rate             = 0x1,\n+\t\t.dfe_enable       = 0,\n+\t\t.dfe_tap          = 0,\n+\t\t.pi_bw_gen1       = 0x5,\n+\t\t.duty_cycle       = 0x0,\n+\t},\n+\t{ /* SPX5_SD10G28_MODE_PRESET_SFI_5000_10G */\n+\t\t.bwidth           = 64,\n+\t\t.cmu_sel          = SPX5_SD10G28_CMU_MAIN,\n+\t\t.rate             = 0x1,\n+\t\t.dfe_enable       = 0,\n+\t\t.dfe_tap          = 0,\n+\t\t.pi_bw_gen1       = 0x5,\n+\t\t.duty_cycle       = 0x0,\n+\t},\n+\t{ /* SPX5_SD10G28_MODE_PRESET_QSGMII */\n+\t\t.bwidth           = 20,\n+\t\t.cmu_sel          = SPX5_SD10G28_CMU_AUX1,\n+\t\t.rate             = 0x1,\n+\t\t.dfe_enable       = 0,\n+\t\t.dfe_tap          = 0,\n+\t\t.pi_bw_gen1       = 0x5,\n+\t\t.duty_cycle       = 0x0,\n+\t},\n+\t{ /* SPX5_SD10G28_MODE_PRESET_SD_2G5 */\n+\t\t.bwidth           = 10,\n+\t\t.cmu_sel          = SPX5_SD10G28_CMU_AUX2,\n+\t\t.rate             = 0x2,\n+\t\t.dfe_enable       = 0,\n+\t\t.dfe_tap          = 0,\n+\t\t.pi_bw_gen1       = 0x7,\n+\t\t.duty_cycle       = 0x0,\n+\t},\n+\t{ /* SPX5_SD10G28_MODE_PRESET_1000BASEX */\n+\t\t.bwidth           = 10,\n+\t\t.cmu_sel          = SPX5_SD10G28_CMU_AUX1,\n+\t\t.rate             = 0x3,\n+\t\t.dfe_enable       = 0,\n+\t\t.dfe_tap          = 0,\n+\t\t.pi_bw_gen1       = 0x7,\n+\t\t.duty_cycle       = 0x0,\n+\t},\n+};\n+\n+/* map from SD25G28 interface width to configuration value */\n+static u8 sd25g28_get_iw_setting(struct udevice *dev, const u8 interface_width)\n+{\n+\tswitch (interface_width) {\n+\tcase 10: return 0;\n+\tcase 16: return 1;\n+\tcase 32: return 3;\n+\tcase 40: return 4;\n+\tcase 64: return 5;\n+\tdefault:\n+\t\tdev_err(dev, \"%s: Illegal value %d for interface width\\n\",\n+\t\t       __func__, interface_width);\n+\t}\n+\treturn 0;\n+}\n+\n+/* map from SD10G28 interface width to configuration value */\n+static u8 sd10g28_get_iw_setting(struct udevice *dev, const u8 interface_width)\n+{\n+\tswitch (interface_width) {\n+\tcase 10: return 0;\n+\tcase 16: return 1;\n+\tcase 20: return 2;\n+\tcase 32: return 3;\n+\tcase 40: return 4;\n+\tcase 64: return 7;\n+\tdefault:\n+\t\tdev_err(dev, \"%s: Illegal value %d for interface width\\n\", __func__,\n+\t\t       interface_width);\n+\t\treturn 0;\n+\t}\n+}\n+\n+static int sparx5_sd10g25_get_mode_preset(struct sparx5_serdes_macro *macro,\n+\t\t\t\t\t  struct sparx5_sd25g28_mode_preset *mode)\n+{\n+\tswitch (macro->serdesmode) {\n+\tcase SPX5_SD_MODE_SFI:\n+\t\tif (macro->speed == SPEED_25000)\n+\t\t\t*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];\n+\t\telse if (macro->speed == SPEED_10000)\n+\t\t\t*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_10000];\n+\t\telse if (macro->speed == SPEED_5000)\n+\t\t\t*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_5000];\n+\t\tbreak;\n+\tcase SPX5_SD_MODE_2G5:\n+\t\t*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_SD_2G5];\n+\t\tbreak;\n+\tcase SPX5_SD_MODE_1000BASEX:\n+\t\t*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_1000BASEX];\n+\t\tbreak;\n+\tcase SPX5_SD_MODE_100FX:\n+\t\t /* Not supported */\n+\t\treturn -EINVAL;\n+\tdefault:\n+\t\t*mode = mode_presets_25g[SPX5_SD25G28_MODE_PRESET_25000];\n+\t\tbreak;\n+\t}\n+\treturn 0;\n+}\n+\n+static int sparx5_sd10g28_get_mode_preset(struct sparx5_serdes_macro *macro,\n+\t\t\t\t\t  struct sparx5_sd10g28_mode_preset *mode,\n+\t\t\t\t\t  struct sparx5_sd10g28_args *args)\n+{\n+\tswitch (macro->serdesmode) {\n+\tcase SPX5_SD_MODE_SFI:\n+\t\tif (macro->speed == SPEED_10000) {\n+\t\t\t*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];\n+\t\t} else if (macro->speed == SPEED_5000) {\n+\t\t\tif (args->is_6g)\n+\t\t\t\t*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_6G];\n+\t\t\telse\n+\t\t\t\t*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SFI_5000_10G];\n+\t\t} else {\n+\t\t\tdev_err(macro->priv->dev, \"%s: Illegal speed: %02u, sidx: %02u, mode (%u)\",\n+\t\t\t       __func__, macro->speed, macro->sidx,\n+\t\t\t       macro->serdesmode);\n+\t\t\treturn -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tcase SPX5_SD_MODE_QSGMII:\n+\t\t*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_QSGMII];\n+\t\tbreak;\n+\tcase SPX5_SD_MODE_2G5:\n+\t\t*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_SD_2G5];\n+\t\tbreak;\n+\tcase SPX5_SD_MODE_100FX:\n+\tcase SPX5_SD_MODE_1000BASEX:\n+\t\t*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_1000BASEX];\n+\t\tbreak;\n+\tdefault:\n+\t\t*mode = mode_presets_10g[SPX5_SD10G28_MODE_PRESET_10000];\n+\t\tbreak;\n+\t}\n+\treturn 0;\n+}\n+\n+static void sparx5_sd25g28_get_params(struct sparx5_serdes_macro *macro,\n+\t\t\t\t      struct sparx5_sd25g28_media_preset *media,\n+\t\t\t\t      struct sparx5_sd25g28_mode_preset *mode,\n+\t\t\t\t      struct sparx5_sd25g28_args *args,\n+\t\t\t\t      struct sparx5_sd25g28_params *params)\n+{\n+\tu8 iw = sd25g28_get_iw_setting(macro->priv->dev, mode->bitwidth);\n+\tstruct sparx5_sd25g28_params init = {\n+\t\t.r_d_width_ctrl_2_0         = iw,\n+\t\t.r_txfifo_ck_div_pmad_2_0   = mode->fifo_ck_div,\n+\t\t.r_rxfifo_ck_div_pmad_2_0   = mode->fifo_ck_div,\n+\t\t.cfg_vco_div_mode_1_0       = mode->vco_div_mode,\n+\t\t.cfg_pre_divsel_1_0         = mode->pre_divsel,\n+\t\t.cfg_sel_div_3_0            = mode->sel_div,\n+\t\t.cfg_vco_start_code_3_0     = 0,\n+\t\t.cfg_pma_tx_ck_bitwidth_2_0 = mode->ck_bitwidth,\n+\t\t.cfg_tx_prediv_1_0          = mode->tx_pre_div,\n+\t\t.cfg_rxdiv_sel_2_0          = mode->ck_bitwidth,\n+\t\t.cfg_tx_subrate_2_0         = mode->subrate,\n+\t\t.cfg_rx_subrate_2_0         = mode->subrate,\n+\t\t.r_multi_lane_mode          = 0,\n+\t\t.cfg_cdrck_en               = 1,\n+\t\t.cfg_dfeck_en               = mode->dfe_enable,\n+\t\t.cfg_dfe_pd                 = mode->dfe_enable == 1 ? 0 : 1,\n+\t\t.cfg_dfedmx_pd              = 1,\n+\t\t.cfg_dfetap_en_5_1          = mode->dfe_tap,\n+\t\t.cfg_dmux_pd                = 0,\n+\t\t.cfg_dmux_clk_pd            = 1,\n+\t\t.cfg_erramp_pd              = mode->dfe_enable == 1 ? 0 : 1,\n+\t\t.cfg_pi_DFE_en              = mode->dfe_enable,\n+\t\t.cfg_pi_en                  = 1,\n+\t\t.cfg_pd_ctle                = 0,\n+\t\t.cfg_summer_en              = 1,\n+\t\t.cfg_pmad_ck_pd             = 0,\n+\t\t.cfg_pd_clk                 = 0,\n+\t\t.cfg_pd_cml                 = 0,\n+\t\t.cfg_pd_driver              = 0,\n+\t\t.cfg_rx_reg_pu              = 1,\n+\t\t.cfg_pd_rms_det             = 1,\n+\t\t.cfg_dcdr_pd                = 0,\n+\t\t.cfg_ecdr_pd                = 1,\n+\t\t.cfg_pd_sq                  = 1,\n+\t\t.cfg_itx_ipdriver_base_2_0  = mode->txmargin,\n+\t\t.cfg_tap_dly_4_0            = media->cfg_tap_dly_4_0,\n+\t\t.cfg_tap_main               = media->cfg_tap_main,\n+\t\t.cfg_en_main                = media->cfg_en_main,\n+\t\t.cfg_tap_adv_3_0            = media->cfg_tap_adv_3_0,\n+\t\t.cfg_en_adv                 = media->cfg_en_adv,\n+\t\t.cfg_en_dly                 = media->cfg_en_dly,\n+\t\t.cfg_iscan_en               = 0,\n+\t\t.l1_pcs_en_fast_iscan       = 0,\n+\t\t.l0_cfg_bw_1_0              = 0,\n+\t\t.cfg_en_dummy               = 0,\n+\t\t.cfg_pll_reserve_3_0        = args->com_pll_reserve,\n+\t\t.l0_cfg_txcal_en            = mode->com_txcal_en,\n+\t\t.l0_cfg_tx_reserve_15_8     = mode->com_tx_reserve_msb,\n+\t\t.l0_cfg_tx_reserve_7_0      = mode->com_tx_reserve_lsb,\n+\t\t.cfg_tx_reserve_15_8        = mode->tx_reserve_msb,\n+\t\t.cfg_tx_reserve_7_0         = mode->tx_reserve_lsb,\n+\t\t.cfg_bw_1_0                 = mode->bw,\n+\t\t.cfg_txcal_man_en           = 1,\n+\t\t.cfg_phase_man_4_0          = 0,\n+\t\t.cfg_quad_man_1_0           = 0,\n+\t\t.cfg_txcal_shift_code_5_0   = 2,\n+\t\t.cfg_txcal_valid_sel_3_0    = 4,\n+\t\t.cfg_txcal_en               = 0,\n+\t\t.cfg_cdr_kf_2_0             = 1,\n+\t\t.cfg_cdr_m_7_0              = 6,\n+\t\t.cfg_pi_bw_3_0              = mode->cfg_pi_bw_3_0,\n+\t\t.cfg_pi_steps_1_0           = 0,\n+\t\t.cfg_dis_2ndorder           = 1,\n+\t\t.cfg_ctle_rstn              = mode->cfg_ctle_rstn,\n+\t\t.r_dfe_rstn                 = mode->r_dfe_rstn,\n+\t\t.cfg_alos_thr_2_0           = media->cfg_alos_thr_2_0,\n+\t\t.cfg_itx_ipcml_base_1_0     = mode->cfg_itx_ipcml_base,\n+\t\t.cfg_rx_reserve_7_0         = 0xbf,\n+\t\t.cfg_rx_reserve_15_8        = 0x61,\n+\t\t.cfg_rxterm_2_0             = mode->rxterm,\n+\t\t.cfg_fom_selm               = 0,\n+\t\t.cfg_rx_sp_ctle_1_0         = 0,\n+\t\t.cfg_isel_ctle_1_0          = 0,\n+\t\t.cfg_vga_ctrl_byp_4_0       = media->cfg_vga_ctrl_byp_4_0,\n+\t\t.cfg_vga_byp                = 1,\n+\t\t.cfg_agc_adpt_byp           = 1,\n+\t\t.cfg_eqr_byp                = 1,\n+\t\t.cfg_eqr_force_3_0          = media->cfg_eq_r_force_3_0,\n+\t\t.cfg_eqc_force_3_0          = media->cfg_eq_c_force_3_0,\n+\t\t.cfg_sum_setcm_en           = 1,\n+\t\t.cfg_pi_dfe_en              = 1,\n+\t\t.cfg_init_pos_iscan_6_0     = 6,\n+\t\t.cfg_init_pos_ipi_6_0       = 9,\n+\t\t.cfg_dfedig_m_2_0           = 6,\n+\t\t.cfg_en_dfedig              = mode->dfe_enable,\n+\t\t.r_d_width_ctrl_from_hwt    = 0,\n+\t\t.r_reg_manual               = 1,\n+\t\t.reg_rst                    = args->reg_rst,\n+\t\t.cfg_jc_byp                 = 1,\n+\t\t.cfg_common_reserve_7_0     = 1,\n+\t\t.cfg_pll_lol_set            = 1,\n+\t\t.cfg_tx2rx_lp_en            = 0,\n+\t\t.cfg_txlb_en                = 0,\n+\t\t.cfg_rx2tx_lp_en            = 0,\n+\t\t.cfg_rxlb_en                = 0,\n+\t\t.r_tx_pol_inv               = args->txinvert,\n+\t\t.r_rx_pol_inv               = args->rxinvert,\n+\t};\n+\n+\t*params = init;\n+}\n+\n+static void sparx5_sd10g28_get_params(struct sparx5_serdes_macro *macro,\n+\t\t\t\t      struct sparx5_sd10g28_media_preset *media,\n+\t\t\t\t      struct sparx5_sd10g28_mode_preset *mode,\n+\t\t\t\t      struct sparx5_sd10g28_args *args,\n+\t\t\t\t      struct sparx5_sd10g28_params *params)\n+{\n+\tu8 iw = sd10g28_get_iw_setting(macro->priv->dev, mode->bwidth);\n+\tstruct sparx5_sd10g28_params init = {\n+\t\t.skip_cmu_cfg                = args->skip_cmu_cfg,\n+\t\t.is_6g                       = args->is_6g,\n+\t\t.cmu_sel                     = mode->cmu_sel,\n+\t\t.cfg_lane_reserve_7_0        = (mode->cmu_sel % 2) << 6,\n+\t\t.cfg_ssc_rtl_clk_sel         = (mode->cmu_sel / 2),\n+\t\t.cfg_lane_reserve_15_8       = mode->duty_cycle,\n+\t\t.cfg_txrate_1_0              = mode->rate,\n+\t\t.cfg_rxrate_1_0              = mode->rate,\n+\t\t.fx_100                      = macro->serdesmode == SPX5_SD_MODE_100FX,\n+\t\t.r_d_width_ctrl_2_0          = iw,\n+\t\t.cfg_pma_tx_ck_bitwidth_2_0  = iw,\n+\t\t.cfg_rxdiv_sel_2_0           = iw,\n+\t\t.r_pcs2pma_phymode_4_0       = 0,\n+\t\t.cfg_lane_id_2_0             = 0,\n+\t\t.cfg_cdrck_en                = 1,\n+\t\t.cfg_dfeck_en                = mode->dfe_enable,\n+\t\t.cfg_dfe_pd                  = (mode->dfe_enable == 1) ? 0 : 1,\n+\t\t.cfg_dfetap_en_5_1           = mode->dfe_tap,\n+\t\t.cfg_erramp_pd               = (mode->dfe_enable == 1) ? 0 : 1,\n+\t\t.cfg_pi_DFE_en               = mode->dfe_enable,\n+\t\t.cfg_pi_en                   = 1,\n+\t\t.cfg_pd_ctle                 = 0,\n+\t\t.cfg_summer_en               = 1,\n+\t\t.cfg_pd_rx_cktree            = 0,\n+\t\t.cfg_pd_clk                  = 0,\n+\t\t.cfg_pd_cml                  = 0,\n+\t\t.cfg_pd_driver               = 0,\n+\t\t.cfg_rx_reg_pu               = 1,\n+\t\t.cfg_d_cdr_pd                = 0,\n+\t\t.cfg_pd_sq                   = mode->dfe_enable,\n+\t\t.cfg_rxdet_en                = 0,\n+\t\t.cfg_rxdet_str               = 0,\n+\t\t.r_multi_lane_mode           = 0,\n+\t\t.cfg_en_adv                  = media->cfg_en_adv,\n+\t\t.cfg_en_main                 = 1,\n+\t\t.cfg_en_dly                  = media->cfg_en_dly,\n+\t\t.cfg_tap_adv_3_0             = media->cfg_tap_adv_3_0,\n+\t\t.cfg_tap_main                = media->cfg_tap_main,\n+\t\t.cfg_tap_dly_4_0             = media->cfg_tap_dly_4_0,\n+\t\t.cfg_vga_ctrl_3_0            = media->cfg_vga_ctrl_3_0,\n+\t\t.cfg_vga_cp_2_0              = media->cfg_vga_cp_2_0,\n+\t\t.cfg_eq_res_3_0              = media->cfg_eq_res_3_0,\n+\t\t.cfg_eq_r_byp                = media->cfg_eq_r_byp,\n+\t\t.cfg_eq_c_force_3_0          = media->cfg_eq_c_force_3_0,\n+\t\t.cfg_en_dfedig               = mode->dfe_enable,\n+\t\t.cfg_sum_setcm_en            = 1,\n+\t\t.cfg_en_preemph              = 0,\n+\t\t.cfg_itx_ippreemp_base_1_0   = 0,\n+\t\t.cfg_itx_ipdriver_base_2_0   = (args->txswing >> 6),\n+\t\t.cfg_ibias_tune_reserve_5_0  = (args->txswing & 63),\n+\t\t.cfg_txswing_half            = (args->txmargin),\n+\t\t.cfg_dis_2nd_order           = 0x1,\n+\t\t.cfg_rx_ssc_lh               = 0x0,\n+\t\t.cfg_pi_floop_steps_1_0      = 0x0,\n+\t\t.cfg_pi_ext_dac_23_16        = (1 << 5),\n+\t\t.cfg_pi_ext_dac_15_8         = (0 << 6),\n+\t\t.cfg_iscan_ext_dac_7_0       = (1 << 7) + 9,\n+\t\t.cfg_cdr_kf_gen1_2_0         = 1,\n+\t\t.cfg_cdr_kf_gen2_2_0         = 1,\n+\t\t.cfg_cdr_kf_gen3_2_0         = 1,\n+\t\t.cfg_cdr_kf_gen4_2_0         = 1,\n+\t\t.r_cdr_m_gen1_7_0            = 4,\n+\t\t.cfg_pi_bw_gen1_3_0          = mode->pi_bw_gen1,\n+\t\t.cfg_pi_bw_gen2              = mode->pi_bw_gen1,\n+\t\t.cfg_pi_bw_gen3              = mode->pi_bw_gen1,\n+\t\t.cfg_pi_bw_gen4              = mode->pi_bw_gen1,\n+\t\t.cfg_pi_ext_dac_7_0          = 3,\n+\t\t.cfg_pi_steps                = 0,\n+\t\t.cfg_mp_max_3_0              = 1,\n+\t\t.cfg_rstn_dfedig             = mode->dfe_enable,\n+\t\t.cfg_alos_thr_3_0            = media->cfg_alos_thr_3_0,\n+\t\t.cfg_predrv_slewrate_1_0     = 3,\n+\t\t.cfg_itx_ipcml_base_1_0      = 0,\n+\t\t.cfg_ip_pre_base_1_0         = 0,\n+\t\t.r_cdr_m_gen2_7_0            = 2,\n+\t\t.r_cdr_m_gen3_7_0            = 2,\n+\t\t.r_cdr_m_gen4_7_0            = 2,\n+\t\t.r_en_auto_cdr_rstn          = 0,\n+\t\t.cfg_oscal_afe               = 1,\n+\t\t.cfg_pd_osdac_afe            = 0,\n+\t\t.cfg_resetb_oscal_afe[0]     = 0,\n+\t\t.cfg_resetb_oscal_afe[1]     = 1,\n+\t\t.cfg_center_spreading        = 0,\n+\t\t.cfg_m_cnt_maxval_4_0        = 15,\n+\t\t.cfg_ncnt_maxval_7_0         = 32,\n+\t\t.cfg_ncnt_maxval_10_8        = 6,\n+\t\t.cfg_ssc_en                  = 1,\n+\t\t.cfg_tx2rx_lp_en             = 0,\n+\t\t.cfg_txlb_en                 = 0,\n+\t\t.cfg_rx2tx_lp_en             = 0,\n+\t\t.cfg_rxlb_en                 = 0,\n+\t\t.r_tx_pol_inv                = args->txinvert,\n+\t\t.r_rx_pol_inv                = args->rxinvert,\n+\t};\n+\n+\t*params = init;\n+}\n+\n+static int sparx5_cmu_apply_cfg(struct sparx5_serdes_private *priv,\n+\t\t\t\tu32 cmu_idx,\n+\t\t\t\tvoid __iomem *cmu_tgt,\n+\t\t\t\tvoid __iomem *cmu_cfg_tgt,\n+\t\t\t\tu32 spd10g)\n+{\n+\tvoid __iomem **regs = priv->regs;\n+\tstruct udevice *dev = priv->dev;\n+\tint value;\n+\n+\tcmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);\n+\tcmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);\n+\n+\tif (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||\n+\t    cmu_idx == 10 || cmu_idx == 13) {\n+\t\tspd10g = 0;\n+\t}\n+\n+\tsdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(1),\n+\t\t      SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,\n+\t\t      cmu_cfg_tgt,\n+\t\t      SD_CMU_CFG_SD_CMU_CFG(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),\n+\t\t      SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST,\n+\t\t      cmu_cfg_tgt,\n+\t\t      SD_CMU_CFG_SD_CMU_CFG(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(1),\n+\t\t      SD_CMU_CFG_SD_CMU_CFG_CMU_RST,\n+\t\t      cmu_cfg_tgt,\n+\t\t      SD_CMU_CFG_SD_CMU_CFG(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(0x1) |\n+\t\t      SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(0x1) |\n+\t\t      SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(0x1) |\n+\t\t      SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(0x1) |\n+\t\t      SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(0x0),\n+\t\t      SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT |\n+\t\t      SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT |\n+\t\t      SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT |\n+\t\t      SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT |\n+\t\t      SD_CMU_CMU_45_R_EN_RATECHG_CTRL,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_45(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(0),\n+\t\t      SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_47(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(0),\n+\t\t      SD_CMU_CMU_1B_CFG_RESERVE_7_0,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_1B(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_0D_CFG_JC_BYP_SET(0x1),\n+\t\t      SD_CMU_CMU_0D_CFG_JC_BYP,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_0D(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(1),\n+\t\t      SD_CMU_CMU_1F_CFG_VTUNE_SEL,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_1F(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(3),\n+\t\t      SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_00(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(3),\n+\t\t      SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_05(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(1),\n+\t\t      SD_CMU_CMU_30_R_PLL_DLOL_EN,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_30(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_09_CFG_SW_10G_SET(spd10g),\n+\t\t      SD_CMU_CMU_09_CFG_SW_10G,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_09(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(0),\n+\t\t      SD_CMU_CFG_SD_CMU_CFG_CMU_RST,\n+\t\t      cmu_cfg_tgt,\n+\t\t      SD_CMU_CFG_SD_CMU_CFG(cmu_idx));\n+\n+\tudelay(20 * 1000);\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(0),\n+\t\t      SD_CMU_CMU_44_R_PLL_RSTN,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_44(cmu_idx));\n+\n+\tsdx5_inst_rmw(SD_CMU_CMU_44_R_PLL_RSTN_SET(1),\n+\t\t      SD_CMU_CMU_44_R_PLL_RSTN,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_44(cmu_idx));\n+\n+\tudelay(20 * 1000);\n+\n+\tvalue = readl(sdx5_addr(regs, SD_CMU_CMU_E0(cmu_idx)));\n+\tvalue = SD_CMU_CMU_E0_PLL_LOL_UDL_GET(value);\n+\n+\tif (value) {\n+\t\tdev_err(dev, \"CMU PLL Loss of Lock: 0x%x\\n\", value);\n+\t\treturn -EINVAL;\n+\t}\n+\tsdx5_inst_rmw(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(0),\n+\t\t      SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD,\n+\t\t      cmu_tgt,\n+\t\t      SD_CMU_CMU_0D(cmu_idx));\n+\treturn 0;\n+}\n+\n+static int sparx5_cmu_cfg(struct sparx5_serdes_private *priv, u32 cmu_idx)\n+{\n+\tvoid __iomem *cmu_tgt, *cmu_cfg_tgt;\n+\tu32 spd10g = 1;\n+\n+\tif (cmu_idx == 1 || cmu_idx == 4 || cmu_idx == 7 ||\n+\t    cmu_idx == 10 || cmu_idx == 13) {\n+\t\tspd10g = 0;\n+\t}\n+\n+\tcmu_tgt = sdx5_inst_get(priv, TARGET_SD_CMU, cmu_idx);\n+\tcmu_cfg_tgt = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, cmu_idx);\n+\n+\treturn sparx5_cmu_apply_cfg(priv, cmu_idx, cmu_tgt, cmu_cfg_tgt, spd10g);\n+}\n+\n+/* Map of 6G/10G serdes mode and index to CMU index. */\n+static const int\n+sparx5_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][SPX5_SERDES_25G_START] = {\n+\t[SPX5_SD10G28_CMU_MAIN] = { 2,   2,  2,  2,  2,\n+\t\t\t\t    2,   2,  2,  5,  5,\n+\t\t\t\t    5,   5,  5,  5,  5,\n+\t\t\t\t    5,   8, 11, 11, 11,\n+\t\t\t\t   11,  11, 11, 11, 11 },\n+\t[SPX5_SD10G28_CMU_AUX1] = { 0,  0,  3,  3,  3,\n+\t\t\t\t    3,  3,  3,  3,  3,\n+\t\t\t\t    6,  6,  6,  6,  6,\n+\t\t\t\t    6,  6,  9,  9, 12,\n+\t\t\t\t   12, 12, 12, 12, 12  },\n+\t[SPX5_SD10G28_CMU_AUX2] = { 1,  1,  1,  1,  4,\n+\t\t\t\t    4,  4,  4,  4,  4,\n+\t\t\t\t    4,  4,  7,  7,  7,\n+\t\t\t\t    7,  7, 10, 10, 10,\n+\t\t\t\t   10, 13, 13, 13, 13  },\n+\t[SPX5_SD10G28_CMU_NONE] = { 1,  1,  1,  1,  4,\n+\t\t\t\t    4,  4,  4,  4,  4,\n+\t\t\t\t    4,  4,  7,  7,  7,\n+\t\t\t\t    7,  7, 10, 10, 10,\n+\t\t\t\t   10, 13, 13, 13, 13  },\n+};\n+\n+/* Sparx5 - Get the index of the CMU which provides the clock for the specified\n+ * serdes mode and index.\n+ */\n+static int sparx5_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index)\n+{\n+\treturn sparx5_serdes_cmu_map[mode][sd_index];\n+}\n+\n+/* Map of 10G serdes mode and index to CMU index. */\n+static const int\n+lan969x_serdes_cmu_map[SPX5_SD10G28_CMU_MAX][10] = {\n+\t[SPX5_SD10G28_CMU_MAIN] = { 2, 2, 2, 2, 2,\n+\t\t\t\t    2, 2, 2, 5, 5 },\n+\t[SPX5_SD10G28_CMU_AUX1] = { 0, 0, 3, 3, 3,\n+\t\t\t\t    3, 3, 3, 3, 3 },\n+\t[SPX5_SD10G28_CMU_AUX2] = { 1, 1, 1, 1, 4,\n+\t\t\t\t    4, 4, 4, 4, 4 },\n+\t[SPX5_SD10G28_CMU_NONE] = { 1, 1, 1, 1, 4,\n+\t\t\t\t    4, 4, 4, 4, 4 },\n+};\n+\n+/* lan969x - Get the index of the CMU which provides the clock for the specified\n+ * serdes mode and index.\n+ */\n+static int lan969x_serdes_cmu_get(enum sparx5_10g28cmu_mode mode, int sd_index)\n+{\n+\treturn lan969x_serdes_cmu_map[mode][sd_index];\n+}\n+\n+static void sparx5_serdes_cmu_power_off(struct sparx5_serdes_private *priv)\n+{\n+\tvoid __iomem *cmu_inst, *cmu_cfg_inst;\n+\tint i;\n+\n+\t/* Power down each CMU */\n+\tfor (i = 0; i < priv->data->consts.cmu_max; i++) {\n+\t\tcmu_inst = sdx5_inst_get(priv, TARGET_SD_CMU, i);\n+\t\tcmu_cfg_inst = sdx5_inst_get(priv, TARGET_SD_CMU_CFG, i);\n+\n+\t\tsdx5_inst_rmw(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(0),\n+\t\t\t      SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, cmu_cfg_inst,\n+\t\t\t      SD_CMU_CFG_SD_CMU_CFG(0));\n+\n+\t\tsdx5_inst_rmw(SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(0),\n+\t\t\t      SD_CMU_CMU_05_CFG_REFCK_TERM_EN, cmu_inst,\n+\t\t\t      SD_CMU_CMU_05(0));\n+\n+\t\tsdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(0),\n+\t\t\t      SD_CMU_CMU_09_CFG_EN_TX_CK_DN, cmu_inst,\n+\t\t\t      SD_CMU_CMU_09(0));\n+\n+\t\tsdx5_inst_rmw(SD_CMU_CMU_06_CFG_VCO_PD_SET(1),\n+\t\t\t      SD_CMU_CMU_06_CFG_VCO_PD, cmu_inst,\n+\t\t\t      SD_CMU_CMU_06(0));\n+\n+\t\tsdx5_inst_rmw(SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(0),\n+\t\t\t      SD_CMU_CMU_09_CFG_EN_TX_CK_UP, cmu_inst,\n+\t\t\t      SD_CMU_CMU_09(0));\n+\n+\t\tsdx5_inst_rmw(SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(1),\n+\t\t\t      SD_CMU_CMU_08_CFG_CK_TREE_PD, cmu_inst,\n+\t\t\t      SD_CMU_CMU_08(0));\n+\n+\t\tsdx5_inst_rmw(\n+\t\t\tSD_CMU_CMU_0D_CFG_REFCK_PD_SET(1) |\n+\t\t\tSD_CMU_CMU_0D_CFG_PD_DIV64_SET(1) |\n+\t\t\tSD_CMU_CMU_0D_CFG_PD_DIV66_SET(1),\n+\t\t\tSD_CMU_CMU_0D_CFG_REFCK_PD |\n+\t\t\tSD_CMU_CMU_0D_CFG_PD_DIV64 |\n+\t\t\tSD_CMU_CMU_0D_CFG_PD_DIV66,\n+\t\t\tcmu_inst, SD_CMU_CMU_0D(0));\n+\n+\t\tsdx5_inst_rmw(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(1),\n+\t\t\t      SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, cmu_inst,\n+\t\t\t      SD_CMU_CMU_06(0));\n+\t}\n+\n+\tfor (i = 0; i < SPX5_SERDES_25G_CNT; i++) {\n+\t\tsdx5_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(1),\n+\t\t\t      SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t\t      priv, SD_LANE_25G_SD_LANE_CFG(i));\n+\n+\t\tsdx5_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),\n+\t\t\t      SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t\t      priv, SD_LANE_25G_SD_LANE_CFG(i));\n+\n+\t\tsdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff),\n+\t\t\t      SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,\n+\t\t\t      priv, SD25G_LANE_CMU_FF(i));\n+\n+\t\tsdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(1),\n+\t\t\t      SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,\n+\t\t\t      priv, SD25G_LANE_CMU_31(i));\n+\n+\t\tsdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0),\n+\t\t\t      SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,\n+\t\t\t      priv, SD25G_LANE_CMU_FF(i));\n+\t}\n+}\n+\n+static void sparx5_sd25g28_reset(void __iomem *regs[],\n+\t\t\t\t struct sparx5_sd25g28_params *params,\n+\t\t\t\t u32 sd_index)\n+{\n+\tif (params->reg_rst == 1) {\n+\t\tsdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(1),\n+\t\t\t SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t\t sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index)));\n+\n+\t\tudelay(2000);\n+\n+\t\tsdx5_rmw_addr(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),\n+\t\t\t SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t\t sdx5_addr(regs, SD_LANE_25G_SD_LANE_CFG(sd_index)));\n+\t}\n+}\n+\n+static int sparx5_sd25g28_apply_params(struct sparx5_serdes_macro *macro,\n+\t\t\t\t       struct sparx5_sd25g28_params *params)\n+{\n+\tstruct sparx5_serdes_private *priv = macro->priv;\n+\tvoid __iomem **regs = priv->regs;\n+\tstruct udevice *dev = priv->dev;\n+\tu32 sd_index = macro->stpidx;\n+\tu32 value;\n+\n+\tsdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(1),\n+\t\t SD_LANE_25G_SD_LANE_CFG_MACRO_RST,\n+\t\t priv,\n+\t\t SD_LANE_25G_SD_LANE_CFG(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xFF),\n+\t\t SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_FF(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET\n+\t\t (params->r_d_width_ctrl_from_hwt) |\n+\t\t SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(params->r_reg_manual),\n+\t\t SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT |\n+\t\t SD25G_LANE_CMU_1A_R_REG_MANUAL,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_1A(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET\n+\t\t (params->cfg_common_reserve_7_0),\n+\t\t SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_31(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(params->cfg_en_dummy),\n+\t\t SD25G_LANE_CMU_09_CFG_EN_DUMMY,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_09(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET\n+\t\t (params->cfg_pll_reserve_3_0),\n+\t\t SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_13(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(params->l0_cfg_txcal_en),\n+\t\t SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_40(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET\n+\t\t (params->l0_cfg_tx_reserve_15_8),\n+\t\t SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_46(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET\n+\t\t (params->l0_cfg_tx_reserve_7_0),\n+\t\t SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_45(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(0),\n+\t\t SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_0B(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(1),\n+\t\t SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_0B(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(0),\n+\t\t SD25G_LANE_CMU_19_R_CK_RESETB,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_19(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_19_R_CK_RESETB_SET(1),\n+\t\t SD25G_LANE_CMU_19_R_CK_RESETB,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_19(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(0),\n+\t\t SD25G_LANE_CMU_18_R_PLL_RSTN,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_18(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_18_R_PLL_RSTN_SET(1),\n+\t\t SD25G_LANE_CMU_18_R_PLL_RSTN,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_18(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(params->r_d_width_ctrl_2_0),\n+\t\t SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_1A(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET\n+\t\t (params->r_txfifo_ck_div_pmad_2_0) |\n+\t\t SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET\n+\t\t (params->r_rxfifo_ck_div_pmad_2_0),\n+\t\t SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 |\n+\t\t SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_30(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(params->cfg_pll_lol_set) |\n+\t\t SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET\n+\t\t (params->cfg_vco_div_mode_1_0),\n+\t\t SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET |\n+\t\t SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_0C(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET\n+\t\t (params->cfg_pre_divsel_1_0),\n+\t\t SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_0D(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(params->cfg_sel_div_3_0),\n+\t\t SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_0E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0x00),\n+\t\t SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_FF(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET\n+\t\t (params->cfg_pma_tx_ck_bitwidth_2_0),\n+\t\t SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_0C(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET\n+\t\t (params->cfg_tx_prediv_1_0),\n+\t\t SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_01(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET\n+\t\t (params->cfg_rxdiv_sel_2_0),\n+\t\t SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_18(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET\n+\t\t (params->cfg_tx_subrate_2_0),\n+\t\t SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2C(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET\n+\t\t (params->cfg_rx_subrate_2_0),\n+\t\t SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_28(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),\n+\t\t SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_18(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET\n+\t\t (params->cfg_dfetap_en_5_1),\n+\t\t SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_0F(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),\n+\t\t SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_18(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(params->cfg_pi_dfe_en),\n+\t\t SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1D(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(params->cfg_ecdr_pd),\n+\t\t SD25G_LANE_LANE_19_LN_CFG_ECDR_PD,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_19(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET\n+\t\t (params->cfg_itx_ipdriver_base_2_0),\n+\t\t SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_01(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(params->cfg_tap_dly_4_0),\n+\t\t SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_03(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(params->cfg_tap_adv_3_0),\n+\t\t SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_06(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(params->cfg_en_adv) |\n+\t\t SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(params->cfg_en_dly),\n+\t\t SD25G_LANE_LANE_07_LN_CFG_EN_ADV |\n+\t\t SD25G_LANE_LANE_07_LN_CFG_EN_DLY,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_07(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET\n+\t\t (params->cfg_tx_reserve_15_8),\n+\t\t SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_43(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET\n+\t\t (params->cfg_tx_reserve_7_0),\n+\t\t SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_42(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(params->cfg_bw_1_0),\n+\t\t SD25G_LANE_LANE_05_LN_CFG_BW_1_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_05(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET\n+\t\t (params->cfg_txcal_man_en),\n+\t\t SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_0B(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET\n+\t\t (params->cfg_txcal_shift_code_5_0),\n+\t\t SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_0A(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET\n+\t\t (params->cfg_txcal_valid_sel_3_0),\n+\t\t SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_09(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(params->cfg_cdr_kf_2_0),\n+\t\t SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1A(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(params->cfg_cdr_m_7_0),\n+\t\t SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1B(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(params->cfg_pi_bw_3_0),\n+\t\t SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2B(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET\n+\t\t (params->cfg_dis_2ndorder),\n+\t\t SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2C(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(params->cfg_ctle_rstn),\n+\t\t SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET\n+\t\t (params->cfg_itx_ipcml_base_1_0),\n+\t\t SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_00(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET\n+\t\t (params->cfg_rx_reserve_7_0),\n+\t\t SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_44(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET\n+\t\t (params->cfg_rx_reserve_15_8),\n+\t\t SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_45(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(params->cfg_dfeck_en) |\n+\t\t SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(params->cfg_rxterm_2_0),\n+\t\t SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN |\n+\t\t SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_0D(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET\n+\t\t (params->cfg_vga_ctrl_byp_4_0),\n+\t\t SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_21(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET\n+\t\t (params->cfg_eqr_force_3_0),\n+\t\t SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_22(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET\n+\t\t (params->cfg_eqc_force_3_0) |\n+\t\t SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(params->cfg_dfe_pd),\n+\t\t SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0 |\n+\t\t SD25G_LANE_LANE_1C_LN_CFG_DFE_PD,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1C(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET\n+\t\t (params->cfg_sum_setcm_en),\n+\t\t SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET\n+\t\t (params->cfg_init_pos_iscan_6_0),\n+\t\t SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_25(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET\n+\t\t (params->cfg_init_pos_ipi_6_0),\n+\t\t SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_26(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(params->cfg_erramp_pd),\n+\t\t SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_18(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET\n+\t\t (params->cfg_dfedig_m_2_0),\n+\t\t SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_0E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(params->cfg_en_dfedig),\n+\t\t SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_0E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(params->r_tx_pol_inv) |\n+\t\t SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(params->r_rx_pol_inv),\n+\t\t SD25G_LANE_LANE_40_LN_R_TX_POL_INV |\n+\t\t SD25G_LANE_LANE_40_LN_R_RX_POL_INV,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_40(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(params->cfg_rx2tx_lp_en) |\n+\t\t SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(params->cfg_tx2rx_lp_en),\n+\t\t SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN |\n+\t\t SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_04(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(params->cfg_rxlb_en),\n+\t\t SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(params->cfg_txlb_en),\n+\t\t SD25G_LANE_LANE_19_LN_CFG_TXLB_EN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_19(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(0),\n+\t\t SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(1),\n+\t\t SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2E(sd_index));\n+\n+\tsdx5_rmw(SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(0),\n+\t\t SD_LANE_25G_SD_LANE_CFG_MACRO_RST,\n+\t\t priv,\n+\t\t SD_LANE_25G_SD_LANE_CFG(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(0),\n+\t\t SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1C(sd_index));\n+\n+\tudelay(2000);\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(1),\n+\t\t SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_1C(sd_index));\n+\n+\tudelay(20000);\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0xff),\n+\t\t SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_FF(sd_index));\n+\n+\tvalue = readl(sdx5_addr(regs, SD25G_LANE_CMU_C0(sd_index)));\n+\tvalue = SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(value);\n+\n+\tif (value) {\n+\t\tdev_err(dev, \"25G PLL Loss of Lock: 0x%x\\n\", value);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tvalue = readl(sdx5_addr(regs, SD_LANE_25G_SD_LANE_STAT(sd_index)));\n+\tvalue = SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(value);\n+\n+\tif (value != 0x1) {\n+\t\tdev_err(dev, \"25G PMA Reset failed: 0x%x\\n\", value);\n+\t\treturn -EINVAL;\n+\t}\n+\tsdx5_rmw(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(0x1),\n+\t\t SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_2A(sd_index));\n+\n+\tsdx5_rmw(SD_LANE_25G_SD_SER_RST_SER_RST_SET(0x0),\n+\t\t SD_LANE_25G_SD_SER_RST_SER_RST,\n+\t\t priv,\n+\t\t SD_LANE_25G_SD_SER_RST(sd_index));\n+\n+\tsdx5_rmw(SD_LANE_25G_SD_DES_RST_DES_RST_SET(0x0),\n+\t\t SD_LANE_25G_SD_DES_RST_DES_RST,\n+\t\t priv,\n+\t\t SD_LANE_25G_SD_DES_RST(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(0),\n+\t\t SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX,\n+\t\t priv,\n+\t\t SD25G_LANE_CMU_FF(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET\n+\t\t (params->cfg_alos_thr_2_0),\n+\t\t SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2D(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(0),\n+\t\t SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2E(sd_index));\n+\n+\tsdx5_rmw(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(0),\n+\t\t SD25G_LANE_LANE_2E_LN_CFG_PD_SQ,\n+\t\t priv,\n+\t\t SD25G_LANE_LANE_2E(sd_index));\n+\n+\treturn 0;\n+}\n+\n+static void sparx5_sd10g28_reset(void __iomem *regs[], u32 lane_index)\n+{\n+\t/* Note: SerDes SD10G_LANE_1 is configured in 10G_LAN mode */\n+\tsdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(1),\n+\t\t      SD_LANE_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t      sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index)));\n+\n+\tudelay(2000);\n+\n+\tsdx5_rmw_addr(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0),\n+\t\t      SD_LANE_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t      sdx5_addr(regs, SD_LANE_SD_LANE_CFG(lane_index)));\n+}\n+\n+static int sparx5_sd10g28_apply_params(struct sparx5_serdes_macro *macro,\n+\t\t\t\t       struct sparx5_sd10g28_params *params)\n+{\n+\tstruct sparx5_serdes_private *priv = macro->priv;\n+\tvoid __iomem **regs = priv->regs;\n+\tstruct udevice *dev = priv->dev;\n+\tu32 lane_index = macro->sidx;\n+\tu32 sd_index = macro->stpidx;\n+\tvoid __iomem *sd_inst;\n+\tu32 value, cmu_idx;\n+\tint err;\n+\n+\tcmu_idx = priv->data->ops.serdes_cmu_get(params->cmu_sel, macro->sidx);\n+\terr = sparx5_cmu_cfg(priv, cmu_idx);\n+\tif (err)\n+\t\treturn err;\n+\n+\tif (params->is_6g)\n+\t\tsd_inst = sdx5_inst_get(priv, TARGET_SD6G_LANE, sd_index);\n+\telse\n+\t\tsd_inst = sdx5_inst_get(priv, TARGET_SD10G_LANE, sd_index);\n+\n+\tsdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(1),\n+\t\t SD_LANE_SD_LANE_CFG_MACRO_RST,\n+\t\t priv,\n+\t\t SD_LANE_SD_LANE_CFG(lane_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(0x0) |\n+\t\t      SD10G_LANE_LANE_93_R_REG_MANUAL_SET(0x1) |\n+\t\t      SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(0x1) |\n+\t\t      SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(0x1) |\n+\t\t      SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(0x0),\n+\t\t      SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT |\n+\t\t      SD10G_LANE_LANE_93_R_REG_MANUAL |\n+\t\t      SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT |\n+\t\t      SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT |\n+\t\t      SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_93(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_94_R_ISCAN_REG_SET(0x1) |\n+\t\t      SD10G_LANE_LANE_94_R_TXEQ_REG_SET(0x1) |\n+\t\t      SD10G_LANE_LANE_94_R_MISC_REG_SET(0x1) |\n+\t\t      SD10G_LANE_LANE_94_R_SWING_REG_SET(0x1),\n+\t\t      SD10G_LANE_LANE_94_R_ISCAN_REG |\n+\t\t      SD10G_LANE_LANE_94_R_TXEQ_REG |\n+\t\t      SD10G_LANE_LANE_94_R_MISC_REG |\n+\t\t      SD10G_LANE_LANE_94_R_SWING_REG,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_94(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(0x1),\n+\t\t      SD10G_LANE_LANE_9E_R_RXEQ_REG,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_9E(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(0x0) |\n+\t\t      SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(0x0) |\n+\t\t      SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(0x1),\n+\t\t      SD10G_LANE_LANE_A1_R_SSC_FROM_HWT |\n+\t\t      SD10G_LANE_LANE_A1_R_CDR_FROM_HWT |\n+\t\t      SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_A1(sd_index));\n+\n+\tsdx5_rmw(SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(params->cmu_sel) |\n+\t\t SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(params->cmu_sel),\n+\t\t SD_LANE_SD_LANE_CFG_RX_REF_SEL |\n+\t\t SD_LANE_SD_LANE_CFG_TX_REF_SEL,\n+\t\t priv,\n+\t\t SD_LANE_SD_LANE_CFG(lane_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET\n+\t\t      (params->cfg_lane_reserve_7_0),\n+\t\t      SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_40(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET\n+\t\t      (params->cfg_ssc_rtl_clk_sel),\n+\t\t      SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_50(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET\n+\t\t      (params->cfg_txrate_1_0) |\n+\t\t      SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET\n+\t\t      (params->cfg_rxrate_1_0),\n+\t\t      SD10G_LANE_LANE_35_CFG_TXRATE_1_0 |\n+\t\t      SD10G_LANE_LANE_35_CFG_RXRATE_1_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_35(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET\n+\t\t      (params->r_d_width_ctrl_2_0),\n+\t\t      SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_94(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET\n+\t\t      (params->cfg_pma_tx_ck_bitwidth_2_0),\n+\t\t      SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_01(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET\n+\t\t      (params->cfg_rxdiv_sel_2_0),\n+\t\t      SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_30(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET\n+\t\t      (params->r_pcs2pma_phymode_4_0),\n+\t\t      SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_A2(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(params->cfg_cdrck_en),\n+\t\t      SD10G_LANE_LANE_13_CFG_CDRCK_EN,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_13(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_DFECK_EN_SET\n+\t\t      (params->cfg_dfeck_en) |\n+\t\t      SD10G_LANE_LANE_23_CFG_DFE_PD_SET(params->cfg_dfe_pd) |\n+\t\t      SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET\n+\t\t      (params->cfg_erramp_pd),\n+\t\t      SD10G_LANE_LANE_23_CFG_DFECK_EN |\n+\t\t      SD10G_LANE_LANE_23_CFG_DFE_PD |\n+\t\t      SD10G_LANE_LANE_23_CFG_ERRAMP_PD,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_23(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET\n+\t\t      (params->cfg_dfetap_en_5_1),\n+\t\t      SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_22(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET\n+\t\t      (params->cfg_pi_DFE_en),\n+\t\t      SD10G_LANE_LANE_1A_CFG_PI_DFE_EN,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_1A(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_02_CFG_EN_ADV_SET(params->cfg_en_adv) |\n+\t\t      SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(params->cfg_en_main) |\n+\t\t      SD10G_LANE_LANE_02_CFG_EN_DLY_SET(params->cfg_en_dly) |\n+\t\t      SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET\n+\t\t      (params->cfg_tap_adv_3_0),\n+\t\t      SD10G_LANE_LANE_02_CFG_EN_ADV |\n+\t\t      SD10G_LANE_LANE_02_CFG_EN_MAIN |\n+\t\t      SD10G_LANE_LANE_02_CFG_EN_DLY |\n+\t\t      SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_02(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(params->cfg_tap_main),\n+\t\t      SD10G_LANE_LANE_03_CFG_TAP_MAIN,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_03(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET\n+\t\t      (params->cfg_tap_dly_4_0),\n+\t\t      SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_04(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET\n+\t\t      (params->cfg_vga_ctrl_3_0),\n+\t\t      SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_2F(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET\n+\t\t      (params->cfg_vga_cp_2_0),\n+\t\t      SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_2F(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET\n+\t\t      (params->cfg_eq_res_3_0),\n+\t\t      SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0B(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(params->cfg_eq_r_byp),\n+\t\t      SD10G_LANE_LANE_0D_CFG_EQR_BYP,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0D(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET\n+\t\t      (params->cfg_eq_c_force_3_0) |\n+\t\t      SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET\n+\t\t      (params->cfg_sum_setcm_en),\n+\t\t      SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0 |\n+\t\t      SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0E(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET\n+\t\t      (params->cfg_en_dfedig),\n+\t\t      SD10G_LANE_LANE_23_CFG_EN_DFEDIG,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_23(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET\n+\t\t      (params->cfg_en_preemph),\n+\t\t      SD10G_LANE_LANE_06_CFG_EN_PREEMPH,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_06(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET\n+\t\t      (params->cfg_itx_ippreemp_base_1_0) |\n+\t\t      SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET\n+\t\t      (params->cfg_itx_ipdriver_base_2_0),\n+\t\t      SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 |\n+\t\t      SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_33(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET\n+\t\t      (params->cfg_ibias_tune_reserve_5_0),\n+\t\t      SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_52(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET\n+\t\t      (params->cfg_txswing_half),\n+\t\t      SD10G_LANE_LANE_37_CFG_TXSWING_HALF,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_37(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET\n+\t\t      (params->cfg_dis_2nd_order),\n+\t\t      SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_3C(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET\n+\t\t      (params->cfg_rx_ssc_lh),\n+\t\t      SD10G_LANE_LANE_39_CFG_RX_SSC_LH,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_39(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET\n+\t\t      (params->cfg_pi_floop_steps_1_0),\n+\t\t      SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_1A(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET\n+\t\t      (params->cfg_pi_ext_dac_23_16),\n+\t\t      SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_16(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET\n+\t\t      (params->cfg_pi_ext_dac_15_8),\n+\t\t      SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_15(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET\n+\t\t      (params->cfg_iscan_ext_dac_7_0),\n+\t\t      SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_26(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET\n+\t\t      (params->cfg_cdr_kf_gen1_2_0),\n+\t\t      SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_42(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET\n+\t\t      (params->r_cdr_m_gen1_7_0),\n+\t\t      SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0F(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET\n+\t\t      (params->cfg_pi_bw_gen1_3_0),\n+\t\t      SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_24(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET\n+\t\t      (params->cfg_pi_ext_dac_7_0),\n+\t\t      SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_14(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(params->cfg_pi_steps),\n+\t\t      SD10G_LANE_LANE_1A_CFG_PI_STEPS,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_1A(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET\n+\t\t      (params->cfg_mp_max_3_0),\n+\t\t      SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_3A(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET\n+\t\t      (params->cfg_rstn_dfedig),\n+\t\t      SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_31(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET\n+\t\t      (params->cfg_alos_thr_3_0),\n+\t\t      SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_48(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET\n+\t\t      (params->cfg_predrv_slewrate_1_0),\n+\t\t      SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_36(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET\n+\t\t      (params->cfg_itx_ipcml_base_1_0),\n+\t\t      SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_32(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET\n+\t\t      (params->cfg_ip_pre_base_1_0),\n+\t\t      SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_37(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET\n+\t\t      (params->cfg_lane_reserve_15_8),\n+\t\t      SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_41(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET\n+\t\t      (params->r_en_auto_cdr_rstn),\n+\t\t      SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_9E(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET\n+\t\t      (params->cfg_oscal_afe) |\n+\t\t      SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET\n+\t\t      (params->cfg_pd_osdac_afe),\n+\t\t      SD10G_LANE_LANE_0C_CFG_OSCAL_AFE |\n+\t\t      SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0C(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET\n+\t\t      (params->cfg_resetb_oscal_afe[0]),\n+\t\t      SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0B(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET\n+\t\t      (params->cfg_resetb_oscal_afe[1]),\n+\t\t      SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0B(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_83_R_TX_POL_INV_SET\n+\t\t      (params->r_tx_pol_inv) |\n+\t\t      SD10G_LANE_LANE_83_R_RX_POL_INV_SET\n+\t\t      (params->r_rx_pol_inv),\n+\t\t      SD10G_LANE_LANE_83_R_TX_POL_INV |\n+\t\t      SD10G_LANE_LANE_83_R_RX_POL_INV,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_83(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET\n+\t\t      (params->cfg_rx2tx_lp_en) |\n+\t\t      SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET\n+\t\t      (params->cfg_tx2rx_lp_en),\n+\t\t      SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN |\n+\t\t      SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_06(sd_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(params->cfg_rxlb_en) |\n+\t\t      SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(params->cfg_txlb_en),\n+\t\t      SD10G_LANE_LANE_0E_CFG_RXLB_EN |\n+\t\t      SD10G_LANE_LANE_0E_CFG_TXLB_EN,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_0E(sd_index));\n+\n+\tsdx5_rmw(SD_LANE_SD_LANE_CFG_MACRO_RST_SET(0),\n+\t\t SD_LANE_SD_LANE_CFG_MACRO_RST,\n+\t\t priv,\n+\t\t SD_LANE_SD_LANE_CFG(lane_index));\n+\n+\tsdx5_inst_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),\n+\t\t      SD10G_LANE_LANE_50_CFG_SSC_RESETB,\n+\t\t      sd_inst,\n+\t\t      SD10G_LANE_LANE_50(sd_index));\n+\n+\tsdx5_rmw(SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(1),\n+\t\t SD10G_LANE_LANE_50_CFG_SSC_RESETB,\n+\t\t priv,\n+\t\t SD10G_LANE_LANE_50(sd_index));\n+\n+\tsdx5_rmw(SD_LANE_MISC_SD_125_RST_DIS_SET(params->fx_100),\n+\t\t SD_LANE_MISC_SD_125_RST_DIS,\n+\t\t priv,\n+\t\t SD_LANE_MISC(lane_index));\n+\n+\tsdx5_rmw(SD_LANE_MISC_RX_ENA_SET(params->fx_100),\n+\t\t SD_LANE_MISC_RX_ENA,\n+\t\t priv,\n+\t\t SD_LANE_MISC(lane_index));\n+\n+\tsdx5_rmw(SD_LANE_MISC_MUX_ENA_SET(params->fx_100),\n+\t\t SD_LANE_MISC_MUX_ENA,\n+\t\t priv,\n+\t\t SD_LANE_MISC(lane_index));\n+\n+\tudelay(6000);\n+\n+\tvalue = readl(sdx5_addr(regs, SD_LANE_SD_LANE_STAT(lane_index)));\n+\tvalue = SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(value);\n+\tif (value != 1) {\n+\t\tdev_err(dev, \"10G PMA Reset failed: 0x%x\\n\", value);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tsdx5_rmw(SD_LANE_SD_SER_RST_SER_RST_SET(0x0),\n+\t\t SD_LANE_SD_SER_RST_SER_RST,\n+\t\t priv,\n+\t\t SD_LANE_SD_SER_RST(lane_index));\n+\n+\tsdx5_rmw(SD_LANE_SD_DES_RST_DES_RST_SET(0x0),\n+\t\t SD_LANE_SD_DES_RST_DES_RST,\n+\t\t priv,\n+\t\t SD_LANE_SD_DES_RST(lane_index));\n+\n+\treturn 0;\n+}\n+\n+static int sparx5_sd25g28_config(struct sparx5_serdes_macro *macro, bool reset)\n+{\n+\tstruct sparx5_sd25g28_media_preset media = media_presets_25g[macro->media];\n+\tstruct sparx5_sd25g28_mode_preset mode;\n+\tstruct sparx5_sd25g28_args args = {\n+\t\t.rxinvert = 1,\n+\t\t.txinvert = 0,\n+\t\t.txswing = 240,\n+\t\t.com_pll_reserve = 0xf,\n+\t\t.reg_rst = reset,\n+\t};\n+\tstruct sparx5_sd25g28_params params;\n+\tint err;\n+\n+\terr = sparx5_sd10g25_get_mode_preset(macro, &mode);\n+\tif (err)\n+\t\treturn err;\n+\tsparx5_sd25g28_get_params(macro, &media, &mode, &args, &params);\n+\tsparx5_sd25g28_reset(macro->priv->regs, &params, macro->stpidx);\n+\treturn sparx5_sd25g28_apply_params(macro, &params);\n+}\n+\n+static int sparx5_sd10g28_config(struct sparx5_serdes_macro *macro, bool reset)\n+{\n+\tstruct sparx5_sd10g28_media_preset media = media_presets_10g[macro->media];\n+\tstruct sparx5_sd10g28_mode_preset mode;\n+\tstruct sparx5_sd10g28_params params;\n+\tstruct sparx5_sd10g28_args args = {\n+\t\t.is_6g = (macro->serdestype == SPX5_SDT_6G),\n+\t\t.txinvert = 0,\n+\t\t.rxinvert = 1,\n+\t\t.txswing = 240,\n+\t\t.reg_rst = reset,\n+\t};\n+\tint err;\n+\n+\terr = sparx5_sd10g28_get_mode_preset(macro, &mode, &args);\n+\tif (err)\n+\t\treturn err;\n+\tsparx5_sd10g28_get_params(macro, &media, &mode, &args, &params);\n+\tsparx5_sd10g28_reset(macro->priv->regs, macro->sidx);\n+\treturn sparx5_sd10g28_apply_params(macro, &params);\n+}\n+\n+/* Power down serdes TX driver */\n+static int sparx5_serdes_power_save(struct sparx5_serdes_macro *macro, u32 pwdn)\n+{\n+\tstruct sparx5_serdes_private *priv = macro->priv;\n+\tvoid __iomem *sd_lane_inst;\n+\n+\tif (macro->serdestype == SPX5_SDT_6G ||\n+\t    macro->serdestype == SPX5_SDT_10G)\n+\t\tsd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE,\n+\t\t\t\t\t     macro->sidx);\n+\telse\n+\t\tsd_lane_inst = sdx5_inst_get(priv, TARGET_SD_LANE_25G,\n+\t\t\t\t\t     macro->stpidx);\n+\n+\tif (macro->serdestype == SPX5_SDT_25G) { /* 25G */\n+\t\t/* Take serdes out of reset */\n+\t\tsdx5_inst_rmw(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(0),\n+\t\t\t      SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t\t      sd_lane_inst, SD_LANE_25G_SD_LANE_CFG(0));\n+\n+\t\t/* Set power down settings for quiet mode */\n+\t\tsdx5_inst_rmw(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL),\n+\t\t\t      SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE,\n+\t\t\t      sd_lane_inst, SD_LANE_25G_QUIET_MODE_6G(0));\n+\t} else { /* 6G and 10G */\n+\t\t/* Take serdes out of reset */\n+\t\tsdx5_inst_rmw(SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(0),\n+\t\t\t      SD_LANE_SD_LANE_CFG_EXT_CFG_RST,\n+\t\t\t      sd_lane_inst, SD_LANE_SD_LANE_CFG(0));\n+\n+\t\t/* Set power down settings for quiet mode */\n+\t\tsdx5_inst_rmw(SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(SPX5_SERDES_QUIET_MODE_VAL),\n+\t\t\t      SD_LANE_QUIET_MODE_6G_QUIET_MODE,\n+\t\t\t      sd_lane_inst, SD_LANE_QUIET_MODE_6G(0));\n+\t}\n+\treturn 0;\n+}\n+\n+static int sparx5_serdes_clock_config(struct sparx5_serdes_macro *macro)\n+{\n+\tstruct sparx5_serdes_private *priv = macro->priv;\n+\n+\t/* Clock is auto-detected in 100Base-FX mode on lan969x */\n+\tif (priv->data->type == SPX5_TARGET_LAN969X)\n+\t\treturn 0;\n+\n+\tif (macro->serdesmode == SPX5_SD_MODE_100FX) {\n+\t\tu32 freq = priv->coreclock == 250000000 ? 2 :\n+\t\t\tpriv->coreclock == 500000000 ? 1 : 0;\n+\n+\t\tsdx5_rmw(SD_LANE_MISC_CORE_CLK_FREQ_SET(freq),\n+\t\t\t SD_LANE_MISC_CORE_CLK_FREQ,\n+\t\t\t priv,\n+\t\t\t SD_LANE_MISC(macro->sidx));\n+\t}\n+\treturn 0;\n+}\n+\n+static int sparx5_serdes_get_serdesmode(phy_interface_t portmode, int speed)\n+{\n+\tswitch (portmode) {\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\t\tif (speed == SPEED_2500)\n+\t\t\treturn SPX5_SD_MODE_2G5;\n+\t\tif (speed == SPEED_100)\n+\t\t\treturn SPX5_SD_MODE_100FX;\n+\t\treturn SPX5_SD_MODE_1000BASEX;\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\t\t/* The same Serdes mode is used for both SGMII and 1000BaseX */\n+\t\treturn SPX5_SD_MODE_1000BASEX;\n+\tcase PHY_INTERFACE_MODE_QSGMII:\n+\t\treturn SPX5_SD_MODE_QSGMII;\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\treturn SPX5_SD_MODE_SFI;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+static int sparx5_serdes_config(struct sparx5_serdes_macro *macro)\n+{\n+\tstruct udevice *dev = macro->priv->dev;\n+\tint serdesmode;\n+\tint err;\n+\n+\tserdesmode = sparx5_serdes_get_serdesmode(macro->portmode, macro->speed);\n+\tif (serdesmode < 0) {\n+\t\tdev_err(dev, \"SerDes %u, interface not supported: %s\\n\",\n+\t\t\tmacro->sidx,\n+\t\t\tphy_modes(macro->portmode));\n+\t\treturn serdesmode;\n+\t}\n+\tmacro->serdesmode = serdesmode;\n+\n+\tsparx5_serdes_clock_config(macro);\n+\n+\tif (macro->serdestype == SPX5_SDT_25G)\n+\t\terr = sparx5_sd25g28_config(macro, false);\n+\telse\n+\t\terr = sparx5_sd10g28_config(macro, false);\n+\tif (err) {\n+\t\tdev_err(dev, \"SerDes %u, config error: %d\\n\",\n+\t\t\tmacro->sidx, err);\n+\t}\n+\treturn err;\n+}\n+\n+static int sparx5_serdes_power_off(struct sparx5_serdes_phy *phy)\n+{\n+\tstruct sparx5_serdes_macro *macro = phy->data;\n+\n+\treturn sparx5_serdes_power_save(macro, true);\n+}\n+\n+static int sparx5_serdes_set_mode(struct sparx5_serdes_phy *phy, int submode)\n+{\n+\tstruct sparx5_serdes_macro *macro;\n+\n+\tswitch (submode) {\n+\tcase PHY_INTERFACE_MODE_1000BASEX:\n+\tcase PHY_INTERFACE_MODE_2500BASEX:\n+\tcase PHY_INTERFACE_MODE_SGMII:\n+\tcase PHY_INTERFACE_MODE_QSGMII:\n+\tcase PHY_INTERFACE_MODE_10GBASER:\n+\t\tmacro = phy->data;\n+\t\tmacro->portmode = submode;\n+\t\tsparx5_serdes_config(macro);\n+\t\treturn 0;\n+\tdefault:\n+\t\treturn -EINVAL;\n+\t}\n+}\n+\n+int sparx5_serdes_reset(struct sparx5_serdes_phy *phy)\n+{\n+\tstruct sparx5_serdes_macro *macro = phy->data;\n+\tint err;\n+\n+\tif (macro->serdestype == SPX5_SDT_25G)\n+\t\terr = sparx5_sd25g28_config(macro, true);\n+\telse\n+\t\terr = sparx5_sd10g28_config(macro, true);\n+\tif (err) {\n+\t\tdev_err(phy->dev, \"SerDes %u, reset error: %d\\n\",\n+\t\t\tmacro->sidx, err);\n+\t}\n+\treturn err;\n+}\n+\n+static void sparx5_serdes_type_set(struct sparx5_serdes_macro *macro, int sidx)\n+{\n+\tif (sidx < SPX5_SERDES_10G_START) {\n+\t\tmacro->serdestype = SPX5_SDT_6G;\n+\t\tmacro->stpidx = macro->sidx;\n+\t} else if (sidx < SPX5_SERDES_25G_START) {\n+\t\tmacro->serdestype = SPX5_SDT_10G;\n+\t\tmacro->stpidx = macro->sidx - SPX5_SERDES_10G_START;\n+\t} else {\n+\t\tmacro->serdestype = SPX5_SDT_25G;\n+\t\tmacro->stpidx = macro->sidx - SPX5_SERDES_25G_START;\n+\t}\n+}\n+\n+static void lan969x_set_serdes_type(struct sparx5_serdes_macro *macro, int sidx)\n+{\n+\tmacro->serdestype = SPX5_SDT_10G;\n+\tmacro->stpidx = macro->sidx;\n+}\n+\n+static int sparx5_phy_create(struct sparx5_serdes_private *priv,\n+\t\t\t   int idx, struct sparx5_serdes_phy **phy)\n+{\n+\tstruct sparx5_serdes_macro *macro;\n+\n+\t*phy = devm_kzalloc(priv->dev, sizeof(struct sparx5_serdes_phy),\n+\t\t\t    GFP_KERNEL);\n+\tif (!*phy)\n+\t\treturn -ENOMEM;\n+\n+\tmacro = devm_kzalloc(priv->dev, sizeof(*macro), GFP_KERNEL);\n+\tif (!macro)\n+\t\treturn -ENOMEM;\n+\n+\tmacro->sidx = idx;\n+\tmacro->priv = priv;\n+\tmacro->speed = -1;\n+\n+\tpriv->data->ops.serdes_type_set(macro, idx);\n+\n+\t(*phy)->ops = priv->data->ops;\n+\t(*phy)->data = macro;\n+\t(*phy)->dev = priv->dev;\n+\n+\t/* Power down serdes by default */\n+\tsparx5_serdes_power_off(*phy);\n+\n+\treturn 0;\n+}\n+\n+static struct sparx5_serdes_io_resource sparx5_serdes_iomap[] =  {\n+\t{ TARGET_SD_CMU,          0x0 },      /* 0x610808000: sd_cmu_0 */\n+\t{ TARGET_SD_CMU + 1,      0x8000 },   /* 0x610810000: sd_cmu_1 */\n+\t{ TARGET_SD_CMU + 2,      0x10000 },  /* 0x610818000: sd_cmu_2 */\n+\t{ TARGET_SD_CMU + 3,      0x18000 },  /* 0x610820000: sd_cmu_3 */\n+\t{ TARGET_SD_CMU + 4,      0x20000 },  /* 0x610828000: sd_cmu_4 */\n+\t{ TARGET_SD_CMU + 5,      0x28000 },  /* 0x610830000: sd_cmu_5 */\n+\t{ TARGET_SD_CMU + 6,      0x30000 },  /* 0x610838000: sd_cmu_6 */\n+\t{ TARGET_SD_CMU + 7,      0x38000 },  /* 0x610840000: sd_cmu_7 */\n+\t{ TARGET_SD_CMU + 8,      0x40000 },  /* 0x610848000: sd_cmu_8 */\n+\t{ TARGET_SD_CMU_CFG,      0x48000 },  /* 0x610850000: sd_cmu_cfg_0 */\n+\t{ TARGET_SD_CMU_CFG + 1,  0x50000 },  /* 0x610858000: sd_cmu_cfg_1 */\n+\t{ TARGET_SD_CMU_CFG + 2,  0x58000 },  /* 0x610860000: sd_cmu_cfg_2 */\n+\t{ TARGET_SD_CMU_CFG + 3,  0x60000 },  /* 0x610868000: sd_cmu_cfg_3 */\n+\t{ TARGET_SD_CMU_CFG + 4,  0x68000 },  /* 0x610870000: sd_cmu_cfg_4 */\n+\t{ TARGET_SD_CMU_CFG + 5,  0x70000 },  /* 0x610878000: sd_cmu_cfg_5 */\n+\t{ TARGET_SD_CMU_CFG + 6,  0x78000 },  /* 0x610880000: sd_cmu_cfg_6 */\n+\t{ TARGET_SD_CMU_CFG + 7,  0x80000 },  /* 0x610888000: sd_cmu_cfg_7 */\n+\t{ TARGET_SD_CMU_CFG + 8,  0x88000 },  /* 0x610890000: sd_cmu_cfg_8 */\n+\t{ TARGET_SD6G_LANE,       0x90000 },  /* 0x610898000: sd6g_lane_0 */\n+\t{ TARGET_SD6G_LANE + 1,   0x98000 },  /* 0x6108a0000: sd6g_lane_1 */\n+\t{ TARGET_SD6G_LANE + 2,   0xa0000 },  /* 0x6108a8000: sd6g_lane_2 */\n+\t{ TARGET_SD6G_LANE + 3,   0xa8000 },  /* 0x6108b0000: sd6g_lane_3 */\n+\t{ TARGET_SD6G_LANE + 4,   0xb0000 },  /* 0x6108b8000: sd6g_lane_4 */\n+\t{ TARGET_SD6G_LANE + 5,   0xb8000 },  /* 0x6108c0000: sd6g_lane_5 */\n+\t{ TARGET_SD6G_LANE + 6,   0xc0000 },  /* 0x6108c8000: sd6g_lane_6 */\n+\t{ TARGET_SD6G_LANE + 7,   0xc8000 },  /* 0x6108d0000: sd6g_lane_7 */\n+\t{ TARGET_SD6G_LANE + 8,   0xd0000 },  /* 0x6108d8000: sd6g_lane_8 */\n+\t{ TARGET_SD6G_LANE + 9,   0xd8000 },  /* 0x6108e0000: sd6g_lane_9 */\n+\t{ TARGET_SD6G_LANE + 10,  0xe0000 },  /* 0x6108e8000: sd6g_lane_10 */\n+\t{ TARGET_SD6G_LANE + 11,  0xe8000 },  /* 0x6108f0000: sd6g_lane_11 */\n+\t{ TARGET_SD6G_LANE + 12,  0xf0000 },  /* 0x6108f8000: sd6g_lane_12 */\n+\t{ TARGET_SD10G_LANE,      0xf8000 },  /* 0x610900000: sd10g_lane_0 */\n+\t{ TARGET_SD10G_LANE + 1,  0x100000 }, /* 0x610908000: sd10g_lane_1 */\n+\t{ TARGET_SD10G_LANE + 2,  0x108000 }, /* 0x610910000: sd10g_lane_2 */\n+\t{ TARGET_SD10G_LANE + 3,  0x110000 }, /* 0x610918000: sd10g_lane_3 */\n+\t{ TARGET_SD_LANE,         0x1a0000 }, /* 0x6109a8000: sd_lane_0 */\n+\t{ TARGET_SD_LANE + 1,     0x1a8000 }, /* 0x6109b0000: sd_lane_1 */\n+\t{ TARGET_SD_LANE + 2,     0x1b0000 }, /* 0x6109b8000: sd_lane_2 */\n+\t{ TARGET_SD_LANE + 3,     0x1b8000 }, /* 0x6109c0000: sd_lane_3 */\n+\t{ TARGET_SD_LANE + 4,     0x1c0000 }, /* 0x6109c8000: sd_lane_4 */\n+\t{ TARGET_SD_LANE + 5,     0x1c8000 }, /* 0x6109d0000: sd_lane_5 */\n+\t{ TARGET_SD_LANE + 6,     0x1d0000 }, /* 0x6109d8000: sd_lane_6 */\n+\t{ TARGET_SD_LANE + 7,     0x1d8000 }, /* 0x6109e0000: sd_lane_7 */\n+\t{ TARGET_SD_LANE + 8,     0x1e0000 }, /* 0x6109e8000: sd_lane_8 */\n+\t{ TARGET_SD_LANE + 9,     0x1e8000 }, /* 0x6109f0000: sd_lane_9 */\n+\t{ TARGET_SD_LANE + 10,    0x1f0000 }, /* 0x6109f8000: sd_lane_10 */\n+\t{ TARGET_SD_LANE + 11,    0x1f8000 }, /* 0x610a00000: sd_lane_11 */\n+\t{ TARGET_SD_LANE + 12,    0x200000 }, /* 0x610a08000: sd_lane_12 */\n+\t{ TARGET_SD_LANE + 13,    0x208000 }, /* 0x610a10000: sd_lane_13 */\n+\t{ TARGET_SD_LANE + 14,    0x210000 }, /* 0x610a18000: sd_lane_14 */\n+\t{ TARGET_SD_LANE + 15,    0x218000 }, /* 0x610a20000: sd_lane_15 */\n+\t{ TARGET_SD_LANE + 16,    0x220000 }, /* 0x610a28000: sd_lane_16 */\n+\t{ TARGET_SD_CMU + 9,      0x400000 }, /* 0x610c08000: sd_cmu_9 */\n+\t{ TARGET_SD_CMU + 10,     0x408000 }, /* 0x610c10000: sd_cmu_10 */\n+\t{ TARGET_SD_CMU + 11,     0x410000 }, /* 0x610c18000: sd_cmu_11 */\n+\t{ TARGET_SD_CMU + 12,     0x418000 }, /* 0x610c20000: sd_cmu_12 */\n+\t{ TARGET_SD_CMU + 13,     0x420000 }, /* 0x610c28000: sd_cmu_13 */\n+\t{ TARGET_SD_CMU_CFG + 9,  0x428000 }, /* 0x610c30000: sd_cmu_cfg_9 */\n+\t{ TARGET_SD_CMU_CFG + 10, 0x430000 }, /* 0x610c38000: sd_cmu_cfg_10 */\n+\t{ TARGET_SD_CMU_CFG + 11, 0x438000 }, /* 0x610c40000: sd_cmu_cfg_11 */\n+\t{ TARGET_SD_CMU_CFG + 12, 0x440000 }, /* 0x610c48000: sd_cmu_cfg_12 */\n+\t{ TARGET_SD_CMU_CFG + 13, 0x448000 }, /* 0x610c50000: sd_cmu_cfg_13 */\n+\t{ TARGET_SD10G_LANE + 4,  0x450000 }, /* 0x610c58000: sd10g_lane_4 */\n+\t{ TARGET_SD10G_LANE + 5,  0x458000 }, /* 0x610c60000: sd10g_lane_5 */\n+\t{ TARGET_SD10G_LANE + 6,  0x460000 }, /* 0x610c68000: sd10g_lane_6 */\n+\t{ TARGET_SD10G_LANE + 7,  0x468000 }, /* 0x610c70000: sd10g_lane_7 */\n+\t{ TARGET_SD10G_LANE + 8,  0x470000 }, /* 0x610c78000: sd10g_lane_8 */\n+\t{ TARGET_SD10G_LANE + 9,  0x478000 }, /* 0x610c80000: sd10g_lane_9 */\n+\t{ TARGET_SD10G_LANE + 10, 0x480000 }, /* 0x610c88000: sd10g_lane_10 */\n+\t{ TARGET_SD10G_LANE + 11, 0x488000 }, /* 0x610c90000: sd10g_lane_11 */\n+\t{ TARGET_SD25G_LANE,      0x490000 }, /* 0x610c98000: sd25g_lane_0 */\n+\t{ TARGET_SD25G_LANE + 1,  0x498000 }, /* 0x610ca0000: sd25g_lane_1 */\n+\t{ TARGET_SD25G_LANE + 2,  0x4a0000 }, /* 0x610ca8000: sd25g_lane_2 */\n+\t{ TARGET_SD25G_LANE + 3,  0x4a8000 }, /* 0x610cb0000: sd25g_lane_3 */\n+\t{ TARGET_SD25G_LANE + 4,  0x4b0000 }, /* 0x610cb8000: sd25g_lane_4 */\n+\t{ TARGET_SD25G_LANE + 5,  0x4b8000 }, /* 0x610cc0000: sd25g_lane_5 */\n+\t{ TARGET_SD25G_LANE + 6,  0x4c0000 }, /* 0x610cc8000: sd25g_lane_6 */\n+\t{ TARGET_SD25G_LANE + 7,  0x4c8000 }, /* 0x610cd0000: sd25g_lane_7 */\n+\t{ TARGET_SD_LANE + 17,    0x550000 }, /* 0x610d58000: sd_lane_17 */\n+\t{ TARGET_SD_LANE + 18,    0x558000 }, /* 0x610d60000: sd_lane_18 */\n+\t{ TARGET_SD_LANE + 19,    0x560000 }, /* 0x610d68000: sd_lane_19 */\n+\t{ TARGET_SD_LANE + 20,    0x568000 }, /* 0x610d70000: sd_lane_20 */\n+\t{ TARGET_SD_LANE + 21,    0x570000 }, /* 0x610d78000: sd_lane_21 */\n+\t{ TARGET_SD_LANE + 22,    0x578000 }, /* 0x610d80000: sd_lane_22 */\n+\t{ TARGET_SD_LANE + 23,    0x580000 }, /* 0x610d88000: sd_lane_23 */\n+\t{ TARGET_SD_LANE + 24,    0x588000 }, /* 0x610d90000: sd_lane_24 */\n+\t{ TARGET_SD_LANE_25G,     0x590000 }, /* 0x610d98000: sd_lane_25g_25 */\n+\t{ TARGET_SD_LANE_25G + 1, 0x598000 }, /* 0x610da0000: sd_lane_25g_26 */\n+\t{ TARGET_SD_LANE_25G + 2, 0x5a0000 }, /* 0x610da8000: sd_lane_25g_27 */\n+\t{ TARGET_SD_LANE_25G + 3, 0x5a8000 }, /* 0x610db0000: sd_lane_25g_28 */\n+\t{ TARGET_SD_LANE_25G + 4, 0x5b0000 }, /* 0x610db8000: sd_lane_25g_29 */\n+\t{ TARGET_SD_LANE_25G + 5, 0x5b8000 }, /* 0x610dc0000: sd_lane_25g_30 */\n+\t{ TARGET_SD_LANE_25G + 6, 0x5c0000 }, /* 0x610dc8000: sd_lane_25g_31 */\n+\t{ TARGET_SD_LANE_25G + 7, 0x5c8000 }, /* 0x610dd0000: sd_lane_25g_32 */\n+};\n+\n+static const struct sparx5_serdes_io_resource lan969x_serdes_iomap[] =  {\n+\t{ TARGET_SD_CMU,               0x0     }, /* 0xe3410000 */\n+\t{ TARGET_SD_CMU +  1,          0x8000  }, /* 0xe3418000 */\n+\t{ TARGET_SD_CMU +  2,          0x10000 }, /* 0xe3420000 */\n+\t{ TARGET_SD_CMU +  3,          0x18000 }, /* 0xe3428000 */\n+\t{ TARGET_SD_CMU +  4,          0x20000 }, /* 0xe3430000 */\n+\t{ TARGET_SD_CMU +  5,          0x28000 }, /* 0xe3438000 */\n+\t{ TARGET_SD_CMU_CFG,           0x30000 }, /* 0xe3440000 */\n+\t{ TARGET_SD_CMU_CFG +  1,      0x38000 }, /* 0xe3448000 */\n+\t{ TARGET_SD_CMU_CFG +  2,      0x40000 }, /* 0xe3450000 */\n+\t{ TARGET_SD_CMU_CFG +  3,      0x48000 }, /* 0xe3458000 */\n+\t{ TARGET_SD_CMU_CFG +  4,      0x50000 }, /* 0xe3460000 */\n+\t{ TARGET_SD_CMU_CFG +  5,      0x58000 }, /* 0xe3468000 */\n+\t{ TARGET_SD10G_LANE,           0x60000 }, /* 0xe3470000 */\n+\t{ TARGET_SD10G_LANE +  1,      0x68000 }, /* 0xe3478000 */\n+\t{ TARGET_SD10G_LANE +  2,      0x70000 }, /* 0xe3480000 */\n+\t{ TARGET_SD10G_LANE +  3,      0x78000 }, /* 0xe3488000 */\n+\t{ TARGET_SD10G_LANE +  4,      0x80000 }, /* 0xe3490000 */\n+\t{ TARGET_SD10G_LANE +  5,      0x88000 }, /* 0xe3498000 */\n+\t{ TARGET_SD10G_LANE +  6,      0x90000 }, /* 0xe34a0000 */\n+\t{ TARGET_SD10G_LANE +  7,      0x98000 }, /* 0xe34a8000 */\n+\t{ TARGET_SD10G_LANE +  8,      0xa0000 }, /* 0xe34b0000 */\n+\t{ TARGET_SD10G_LANE +  9,      0xa8000 }, /* 0xe34b8000 */\n+\t{ TARGET_SD_LANE,             0x100000 }, /* 0xe3510000 */\n+\t{ TARGET_SD_LANE +  1,        0x108000 }, /* 0xe3518000 */\n+\t{ TARGET_SD_LANE +  2,        0x110000 }, /* 0xe3520000 */\n+\t{ TARGET_SD_LANE +  3,        0x118000 }, /* 0xe3528000 */\n+\t{ TARGET_SD_LANE +  4,        0x120000 }, /* 0xe3530000 */\n+\t{ TARGET_SD_LANE +  5,        0x128000 }, /* 0xe3538000 */\n+\t{ TARGET_SD_LANE +  6,        0x130000 }, /* 0xe3540000 */\n+\t{ TARGET_SD_LANE +  7,        0x138000 }, /* 0xe3548000 */\n+\t{ TARGET_SD_LANE +  8,        0x140000 }, /* 0xe3550000 */\n+\t{ TARGET_SD_LANE +  9,        0x148000 }, /* 0xe3558000 */\n+};\n+\n+static struct sparx5_serdes_match_data sparx5_desc = {\n+\t.type = SPX5_TARGET_SPARX5,\n+\t.iomap = sparx5_serdes_iomap,\n+\t.iomap_size = ARRAY_SIZE(sparx5_serdes_iomap),\n+\t.tsize = sparx5_serdes_tsize,\n+\t.consts = {\n+\t\t.sd_max       = 33,\n+\t\t.cmu_max      = 14,\n+\t},\n+\t.ops = {\n+\t\t.serdes_type_set      = &sparx5_serdes_type_set,\n+\t\t.serdes_cmu_get       = &sparx5_serdes_cmu_get,\n+\t},\n+};\n+\n+static struct sparx5_serdes_match_data lan969x_desc = {\n+\t.type = SPX5_TARGET_LAN969X,\n+\t.iomap = lan969x_serdes_iomap,\n+\t.iomap_size = ARRAY_SIZE(lan969x_serdes_iomap),\n+\t.tsize = lan969x_serdes_tsize,\n+\t.consts = {\n+\t\t.sd_max       = 10,\n+\t\t.cmu_max      = 6,\n+\t},\n+\t.ops = {\n+\t\t.serdes_type_set      = &lan969x_set_serdes_type,\n+\t\t.serdes_cmu_get       = &lan969x_serdes_cmu_get,\n+\t}\n+};\n+\n+void *sparx5_serdes_probe(struct udevice *dev)\n+{\n+\tstruct sparx5_serdes_private *serdes;\n+\tstruct mscc_match_data *data;\n+\tvoid __iomem *iomem;\n+\tunsigned long clock;\n+\tstruct clk clk;\n+\tint idx;\n+\tint err;\n+\n+\tserdes = devm_kzalloc(dev, sizeof(*serdes), GFP_KERNEL);\n+\tif (!serdes)\n+\t\treturn ERR_PTR(-ENOMEM);\n+\n+\tdata = (struct mscc_match_data*)dev_get_driver_data(dev);\n+\tif (!data)\n+\t\treturn ERR_PTR(-EINVAL);\n+\n+\tif (data->target == SPARX5_TARGET)\n+\t\tserdes->data = &sparx5_desc;\n+\tif (data->target == LAN969X_TARGET)\n+\t\tserdes->data = &lan969x_desc;\n+\n+\tserdes->dev = dev;\n+\ttsize = serdes->data->tsize;\n+\n+\t/* Get coreclock */\n+\terr = clk_get_by_index(dev, 0, &clk);\n+\tif (err < 0) {\n+\t\tdev_err(serdes->dev, \"Failed to get coreclock\\n\");\n+\t\treturn ERR_PTR(err);\n+\t}\n+\n+\tclock = clk_get_rate(&clk);\n+\tif (clock == 0) {\n+\t\tdev_err(serdes->dev, \"Invalid coreclock %lu\\n\", clock);\n+\t\treturn ERR_PTR(-EINVAL);\n+\t}\n+\tserdes->coreclock = clock;\n+\n+\tiomem = dev_remap_addr_index(dev, data->num_regs);\n+\tif (!iomem) {\n+\t\tdev_err(serdes->dev, \"Unable to get serdes registers\");\n+\t\treturn ERR_PTR(-ENOMEM);\n+\t}\n+\n+\tfor (idx = 0; idx < serdes->data->iomap_size; idx++) {\n+\t\tconst struct sparx5_serdes_io_resource *iomap =\n+\t\t\t&serdes->data->iomap[idx];\n+\n+\t\tserdes->regs[iomap->id] = iomem + iomap->offset;\n+\t}\n+\n+\tfor (idx = 0; idx < serdes->data->consts.sd_max; idx++) {\n+\t\terr = sparx5_phy_create(serdes, idx, &serdes->phys[idx]);\n+\t\tif (err)\n+\t\t\treturn ERR_PTR(err);\n+\t}\n+\n+\t/* Power down all CMU's by default */\n+\tif (serdes->data->type == SPX5_TARGET_SPARX5)\n+\t\tsparx5_serdes_cmu_power_off(serdes);\n+\n+\treturn serdes;\n+}\n+\n+struct sparx5_serdes_phy *sparx5_serdes_phy_get(void *data, u32 serdes_type, u32 serdes_idx)\n+{\n+\tstruct sparx5_serdes_private *serdes = data;\n+\n+\treturn serdes->phys[serdes_idx];\n+}\n+\n+void sparx5_serdes_port_init(struct sparx5_serdes_phy *phy, u32 mac_type)\n+{\n+\tswitch (mac_type) {\n+\tcase IF_SGMII:\n+\tcase IF_SGMII_CISCO:\n+\t\tsparx5_serdes_set_mode(phy, PHY_INTERFACE_MODE_SGMII);\n+\t\tbreak;\n+\tcase IF_QSGMII:\n+\t\tsparx5_serdes_set_mode(phy, PHY_INTERFACE_MODE_QSGMII);\n+\t\tbreak;\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\ndiff --git a/drivers/net/mscc_eswitch/sparx5_serdes.h b/drivers/net/mscc_eswitch/sparx5_serdes.h\nnew file mode 100644\nindex 00000000000..5fd047f1b14\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_serdes.h\n@@ -0,0 +1,69 @@\n+/* SPDX-License-Identifier: GPL-2.0+\n+ * Microchip Sparx5 SerDes driver\n+ *\n+ * Copyright (c) 2020 Microchip Technology Inc.\n+ */\n+\n+#ifndef _SPARX5_SERDES_H_\n+#define _SPARX5_SERDES_H_\n+\n+enum phy_media {\n+\tPHY_MEDIA_DEFAULT,\n+\tPHY_MEDIA_SR,\n+\tPHY_MEDIA_DAC,\n+};\n+\n+enum sparx5_serdes_type {\n+\tSPX5_SDT_6G  = 6,\n+\tSPX5_SDT_10G = 10,\n+\tSPX5_SDT_25G = 25,\n+};\n+\n+enum sparx5_serdes_mode {\n+\tSPX5_SD_MODE_NONE,\n+\tSPX5_SD_MODE_2G5,\n+\tSPX5_SD_MODE_QSGMII,\n+\tSPX5_SD_MODE_100FX,\n+\tSPX5_SD_MODE_1000BASEX,\n+\tSPX5_SD_MODE_SFI,\n+};\n+\n+enum sparx5_10g28cmu_mode {\n+\tSPX5_SD10G28_CMU_MAIN = 0,\n+\tSPX5_SD10G28_CMU_AUX1 = 1,\n+\tSPX5_SD10G28_CMU_AUX2 = 3,\n+\tSPX5_SD10G28_CMU_NONE = 4,\n+\tSPX5_SD10G28_CMU_MAX,\n+};\n+\n+struct sparx5_serdes_macro {\n+\tstruct sparx5_serdes_private *priv;\n+\tu32 sidx;\n+\tu32 stpidx;\n+\tenum sparx5_serdes_type serdestype;\n+\tenum sparx5_serdes_mode serdesmode;\n+\tphy_interface_t portmode;\n+\tint speed;\n+\tenum phy_media media;\n+};\n+\n+struct sparx5_serdes_ops {\n+\tvoid (*serdes_type_set)(struct sparx5_serdes_macro *macro, int sidx);\n+\tint (*serdes_cmu_get)(enum sparx5_10g28cmu_mode mode, int sd_index);\n+};\n+\n+struct sparx5_serdes_phy {\n+\tvoid *data;\n+\tstruct udevice *dev;\n+\tstruct sparx5_serdes_ops ops;\n+};\n+\n+// This is the old API just to be able to compile\n+void sparx5_serdes_port_init(struct sparx5_serdes_phy *phy, u32 mac_type);\n+\n+// This is the new API, add more functions here\n+void *sparx5_serdes_probe(struct udevice *dev);\n+struct sparx5_serdes_phy *sparx5_serdes_phy_get(void *data, u32 serdes_type, u32 serdes_idx);\n+int sparx5_serdes_reset(struct sparx5_serdes_phy *phy);\n+\n+#endif /* _SPARX5_SERDES_H_ */\ndiff --git a/drivers/net/mscc_eswitch/sparx5_serdes_priv.h b/drivers/net/mscc_eswitch/sparx5_serdes_priv.h\nnew file mode 100644\nindex 00000000000..65b67f190ee\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_serdes_priv.h\n@@ -0,0 +1,130 @@\n+#ifndef _SPARX5_SERDES_PRIV_H_\n+#define _SPARX5_SERDES_PRIV_H_\n+\n+#include <phy_interface.h>\n+\n+#include \"sparx5_serdes_regs.h\"\n+\n+#define SPX5_SERDES_MAX       33\n+\n+enum sparx5_target {\n+\tSPX5_TARGET_SPARX5,\n+\tSPX5_TARGET_LAN969X,\n+};\n+\n+struct sparx5_serdes_io_resource {\n+\tenum sparx5_serdes_target id;\n+\tphys_addr_t offset;\n+};\n+\n+struct sparx5_serdes_consts {\n+\tint sd_max;\n+\tint cmu_max;\n+};\n+\n+struct sparx5_serdes_match_data {\n+\tenum sparx5_target type;\n+\tconst struct sparx5_serdes_consts consts;\n+\tconst struct sparx5_serdes_ops ops;\n+\tconst struct sparx5_serdes_io_resource *iomap;\n+\tint iomap_size;\n+\tconst unsigned int *tsize;\n+};\n+\n+struct sparx5_serdes_private {\n+\tstruct udevice *dev;\n+\tvoid __iomem *regs[NUM_TARGETS];\n+\tstruct sparx5_serdes_phy *phys[SPX5_SERDES_MAX];\n+\tbool cmu_enabled;\n+\tunsigned long coreclock;\n+\tstruct sparx5_serdes_match_data *data;\n+};\n+\n+/* Read, Write and modify registers content.\n+ * The register definition macros start at the id\n+ */\n+static inline void __iomem *sdx5_addr(void __iomem *base[],\n+\t\t\t\t      int id, int tinst, int tcnt,\n+\t\t\t\t      int gbase, int ginst,\n+\t\t\t\t      int gcnt, int gwidth,\n+\t\t\t\t      int raddr, int rinst,\n+\t\t\t\t      int rcnt, int rwidth)\n+{\n+\tWARN_ON((tinst) >= tcnt);\n+\tWARN_ON((ginst) >= gcnt);\n+\tWARN_ON((rinst) >= rcnt);\n+\treturn base[id + (tinst)] +\n+\t\tgbase + ((ginst) * gwidth) +\n+\t\traddr + ((rinst) * rwidth);\n+}\n+\n+static inline void __iomem *sdx5_inst_baseaddr(void __iomem *base,\n+\t\t\t\t\t       int gbase, int ginst,\n+\t\t\t\t\t       int gcnt, int gwidth,\n+\t\t\t\t\t       int raddr, int rinst,\n+\t\t\t\t\t       int rcnt, int rwidth)\n+{\n+\tWARN_ON((ginst) >= gcnt);\n+\tWARN_ON((rinst) >= rcnt);\n+\treturn base +\n+\t\tgbase + ((ginst) * gwidth) +\n+\t\traddr + ((rinst) * rwidth);\n+}\n+\n+static inline void sdx5_rmw(u32 val, u32 mask, struct sparx5_serdes_private *priv,\n+\t\t\t    int id, int tinst, int tcnt,\n+\t\t\t    int gbase, int ginst, int gcnt, int gwidth,\n+\t\t\t    int raddr, int rinst, int rcnt, int rwidth)\n+{\n+\tu32 nval;\n+\tvoid __iomem *addr =\n+\t\tsdx5_addr(priv->regs, id, tinst, tcnt,\n+\t\t\t  gbase, ginst, gcnt, gwidth,\n+\t\t\t  raddr, rinst, rcnt, rwidth);\n+\tnval = readl(addr);\n+\tnval = (nval & ~mask) | (val & mask);\n+\twritel(nval, addr);\n+}\n+\n+static inline void sdx5_inst_rmw(u32 val, u32 mask, void __iomem *iomem,\n+\t\t\t\t int id, int tinst, int tcnt,\n+\t\t\t\t int gbase, int ginst, int gcnt, int gwidth,\n+\t\t\t\t int raddr, int rinst, int rcnt, int rwidth)\n+{\n+\tu32 nval;\n+\tvoid __iomem *addr =\n+\t\tsdx5_inst_baseaddr(iomem,\n+\t\t\t\t   gbase, ginst, gcnt, gwidth,\n+\t\t\t\t   raddr, rinst, rcnt, rwidth);\n+\tnval = readl(addr);\n+\tnval = (nval & ~mask) | (val & mask);\n+\twritel(nval, addr);\n+}\n+\n+static inline void sdx5_rmw_addr(u32 val, u32 mask, void __iomem *addr)\n+{\n+\tu32 nval;\n+\n+\tnval = readl(addr);\n+\tnval = (nval & ~mask) | (val & mask);\n+\twritel(nval, addr);\n+}\n+\n+static inline void __iomem *sdx5_inst_get(struct sparx5_serdes_private *priv,\n+\t\t\t\t\t  int id, int tinst)\n+{\n+\treturn priv->regs[id + tinst];\n+}\n+\n+static inline void __iomem *sdx5_inst_addr(void __iomem *iomem,\n+\t\t\t\t\t   int id, int tinst, int tcnt,\n+\t\t\t\t\t   int gbase,\n+\t\t\t\t\t   int ginst, int gcnt, int gwidth,\n+\t\t\t\t\t   int raddr,\n+\t\t\t\t\t   int rinst, int rcnt, int rwidth)\n+{\n+\treturn sdx5_inst_baseaddr(iomem, gbase, ginst, gcnt, gwidth,\n+\t\t\t\t  raddr, rinst, rcnt, rwidth);\n+}\n+\n+#endif /* _SPARX5_SERDES_PRIV_H_ */\ndiff --git a/drivers/net/mscc_eswitch/sparx5_serdes_regs.h b/drivers/net/mscc_eswitch/sparx5_serdes_regs.h\nnew file mode 100644\nindex 00000000000..544f0386d5a\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_serdes_regs.h\n@@ -0,0 +1,3047 @@\n+/* SPDX-License-Identifier: GPL-2.0+\n+ * Microchip Sparx5 SerDes driver\n+ *\n+ * Copyright (c) 2023 Microchip Technology Inc.\n+ */\n+\n+/* This file is autogenerated by cml-utils 2023-04-13 15:02:00 +0200.\n+ * Commit ID: 5ac560288d46048f872ecdb8add53717f1efc0e1 (dirty)\n+ */\n+\n+#ifndef _SPARX5_MAIN_REGS_H_\n+#define _SPARX5_MAIN_REGS_H_\n+\n+#include <linux/bitfield.h>\n+#include <linux/types.h>\n+#include <linux/bug.h>\n+\n+#include \"sparx5_serdes.h\"\n+\n+enum sparx5_serdes_target {\n+\tTARGET_SD10G_LANE = 200,\n+\tTARGET_SD25G_LANE = 212,\n+\tTARGET_SD6G_LANE = 233,\n+\tTARGET_SD_CMU = 248,\n+\tTARGET_SD_CMU_CFG = 262,\n+\tTARGET_SD_LANE = 276,\n+\tTARGET_SD_LANE_25G = 301,\n+\tNUM_TARGETS = 332\n+};\n+\n+enum sparx5_serdes_tsize_enum {\n+\tTC_SD10G_LANE,\n+\tTC_SD_CMU,\n+\tTC_SD_CMU_CFG,\n+\tTC_SD_LANE,\n+\tTSIZE_LAST,\n+};\n+\n+const unsigned int *tsize;\n+\n+#define TSIZE(o) tsize[o]\n+\n+#define __REG(...)    __VA_ARGS__\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_01 */\n+#define SD10G_LANE_LANE_01(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 4, 0,  \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)\n+#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)\n+#define SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_01_CFG_PMA_TX_CK_BITWIDTH_2_0, x)\n+\n+#define SD10G_LANE_LANE_01_CFG_RXDET_EN          BIT(4)\n+#define SD10G_LANE_LANE_01_CFG_RXDET_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)\n+#define SD10G_LANE_LANE_01_CFG_RXDET_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_EN, x)\n+\n+#define SD10G_LANE_LANE_01_CFG_RXDET_STR         BIT(5)\n+#define SD10G_LANE_LANE_01_CFG_RXDET_STR_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)\n+#define SD10G_LANE_LANE_01_CFG_RXDET_STR_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_01_CFG_RXDET_STR, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_02 */\n+#define SD10G_LANE_LANE_02(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 8, 0,  \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_02_CFG_EN_ADV            BIT(0)\n+#define SD10G_LANE_LANE_02_CFG_EN_ADV_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_ADV, x)\n+#define SD10G_LANE_LANE_02_CFG_EN_ADV_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_02_CFG_EN_ADV, x)\n+\n+#define SD10G_LANE_LANE_02_CFG_EN_MAIN           BIT(1)\n+#define SD10G_LANE_LANE_02_CFG_EN_MAIN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)\n+#define SD10G_LANE_LANE_02_CFG_EN_MAIN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_02_CFG_EN_MAIN, x)\n+\n+#define SD10G_LANE_LANE_02_CFG_EN_DLY            BIT(2)\n+#define SD10G_LANE_LANE_02_CFG_EN_DLY_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY, x)\n+#define SD10G_LANE_LANE_02_CFG_EN_DLY_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY, x)\n+\n+#define SD10G_LANE_LANE_02_CFG_EN_DLY2           BIT(3)\n+#define SD10G_LANE_LANE_02_CFG_EN_DLY2_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)\n+#define SD10G_LANE_LANE_02_CFG_EN_DLY2_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_02_CFG_EN_DLY2, x)\n+\n+#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0       GENMASK(7, 4)\n+#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)\n+#define SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_02_CFG_TAP_ADV_3_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_03 */\n+#define SD10G_LANE_LANE_03(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 12, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_03_CFG_TAP_MAIN          BIT(0)\n+#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)\n+#define SD10G_LANE_LANE_03_CFG_TAP_MAIN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_03_CFG_TAP_MAIN, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_04 */\n+#define SD10G_LANE_LANE_04(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 16, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0       GENMASK(4, 0)\n+#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)\n+#define SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_04_CFG_TAP_DLY_4_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_06 */\n+#define SD10G_LANE_LANE_06(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 24, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_06_CFG_PD_DRIVER         BIT(0)\n+#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)\n+#define SD10G_LANE_LANE_06_CFG_PD_DRIVER_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_06_CFG_PD_DRIVER, x)\n+\n+#define SD10G_LANE_LANE_06_CFG_PD_CLK            BIT(1)\n+#define SD10G_LANE_LANE_06_CFG_PD_CLK_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CLK, x)\n+#define SD10G_LANE_LANE_06_CFG_PD_CLK_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CLK, x)\n+\n+#define SD10G_LANE_LANE_06_CFG_PD_CML            BIT(2)\n+#define SD10G_LANE_LANE_06_CFG_PD_CML_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_06_CFG_PD_CML, x)\n+#define SD10G_LANE_LANE_06_CFG_PD_CML_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_06_CFG_PD_CML, x)\n+\n+#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN       BIT(3)\n+#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)\n+#define SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_06_CFG_TX2RX_LP_EN, x)\n+\n+#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN       BIT(4)\n+#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)\n+#define SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_06_CFG_RX2TX_LP_EN, x)\n+\n+#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH        BIT(5)\n+#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)\n+#define SD10G_LANE_LANE_06_CFG_EN_PREEMPH_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_06_CFG_EN_PREEMPH, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0B */\n+#define SD10G_LANE_LANE_0B(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 44, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0        GENMASK(3, 0)\n+#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)\n+#define SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0B_CFG_EQ_RES_3_0, x)\n+\n+#define SD10G_LANE_LANE_0B_CFG_PD_CTLE           BIT(4)\n+#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)\n+#define SD10G_LANE_LANE_0B_CFG_PD_CTLE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0B_CFG_PD_CTLE, x)\n+\n+#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN        BIT(5)\n+#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)\n+#define SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0B_CFG_CTLE_TP_EN, x)\n+\n+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE  BIT(6)\n+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)\n+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_AFE, x)\n+\n+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ   BIT(7)\n+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)\n+#define SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0B_CFG_RESETB_OSCAL_SQ, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0C */\n+#define SD10G_LANE_LANE_0C(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 48, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE         BIT(0)\n+#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)\n+#define SD10G_LANE_LANE_0C_CFG_OSCAL_AFE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_AFE, x)\n+\n+#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ          BIT(1)\n+#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)\n+#define SD10G_LANE_LANE_0C_CFG_OSCAL_SQ_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_OSCAL_SQ, x)\n+\n+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE      BIT(2)\n+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)\n+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_AFE, x)\n+\n+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ       BIT(3)\n+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)\n+#define SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_OSDAC_2X_SQ, x)\n+\n+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE      BIT(4)\n+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)\n+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_AFE, x)\n+\n+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ       BIT(5)\n+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)\n+#define SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_OSDAC_SQ, x)\n+\n+#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS          BIT(6)\n+#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)\n+#define SD10G_LANE_LANE_0C_CFG_PD_RX_LS_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_PD_RX_LS, x)\n+\n+#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12     BIT(7)\n+#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)\n+#define SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0C_CFG_RX_PCIE_GEN12, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0D */\n+#define SD10G_LANE_LANE_0D(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 52, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0    GENMASK(1, 0)\n+#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)\n+#define SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0D_CFG_CTLE_M_THR_1_0, x)\n+\n+#define SD10G_LANE_LANE_0D_CFG_EQR_BYP           BIT(4)\n+#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)\n+#define SD10G_LANE_LANE_0D_CFG_EQR_BYP_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0D_CFG_EQR_BYP, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0E */\n+#define SD10G_LANE_LANE_0E(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 56, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0     GENMASK(3, 0)\n+#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)\n+#define SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0E_CFG_EQC_FORCE_3_0, x)\n+\n+#define SD10G_LANE_LANE_0E_CFG_RXLB_EN           BIT(4)\n+#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)\n+#define SD10G_LANE_LANE_0E_CFG_RXLB_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0E_CFG_RXLB_EN, x)\n+\n+#define SD10G_LANE_LANE_0E_CFG_TXLB_EN           BIT(5)\n+#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)\n+#define SD10G_LANE_LANE_0E_CFG_TXLB_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0E_CFG_TXLB_EN, x)\n+\n+#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN      BIT(6)\n+#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)\n+#define SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0E_CFG_SUM_SETCM_EN, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_0F */\n+#define SD10G_LANE_LANE_0F(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 60, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0      GENMASK(7, 0)\n+#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)\n+#define SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_0F_R_CDR_M_GEN1_7_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_13 */\n+#define SD10G_LANE_LANE_13(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 76, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_13_CFG_DCDR_PD           BIT(0)\n+#define SD10G_LANE_LANE_13_CFG_DCDR_PD_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)\n+#define SD10G_LANE_LANE_13_CFG_DCDR_PD_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_13_CFG_DCDR_PD, x)\n+\n+#define SD10G_LANE_LANE_13_CFG_PHID_1T           BIT(1)\n+#define SD10G_LANE_LANE_13_CFG_PHID_1T_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_13_CFG_PHID_1T, x)\n+#define SD10G_LANE_LANE_13_CFG_PHID_1T_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_13_CFG_PHID_1T, x)\n+\n+#define SD10G_LANE_LANE_13_CFG_CDRCK_EN          BIT(2)\n+#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)\n+#define SD10G_LANE_LANE_13_CFG_CDRCK_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_13_CFG_CDRCK_EN, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_14 */\n+#define SD10G_LANE_LANE_14(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 80, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0    GENMASK(7, 0)\n+#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)\n+#define SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_14_CFG_PI_EXT_DAC_7_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_15 */\n+#define SD10G_LANE_LANE_15(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 84, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8   GENMASK(7, 0)\n+#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)\n+#define SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_15_CFG_PI_EXT_DAC_15_8, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_16 */\n+#define SD10G_LANE_LANE_16(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 88, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16  GENMASK(7, 0)\n+#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)\n+#define SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_16_CFG_PI_EXT_DAC_23_16, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_1A */\n+#define SD10G_LANE_LANE_1A(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 104, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN      BIT(0)\n+#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)\n+#define SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_R_SCAN_EN, x)\n+\n+#define SD10G_LANE_LANE_1A_CFG_PI_EN             BIT(1)\n+#define SD10G_LANE_LANE_1A_CFG_PI_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_EN, x)\n+#define SD10G_LANE_LANE_1A_CFG_PI_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_EN, x)\n+\n+#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN         BIT(2)\n+#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)\n+#define SD10G_LANE_LANE_1A_CFG_PI_DFE_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_DFE_EN, x)\n+\n+#define SD10G_LANE_LANE_1A_CFG_PI_STEPS          BIT(3)\n+#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)\n+#define SD10G_LANE_LANE_1A_CFG_PI_STEPS_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_STEPS, x)\n+\n+#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0 GENMASK(5, 4)\n+#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)\n+#define SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_1A_CFG_PI_FLOOP_STEPS_1_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_22 */\n+#define SD10G_LANE_LANE_22(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 136, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1     GENMASK(4, 0)\n+#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)\n+#define SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_22_CFG_DFETAP_EN_5_1, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_23 */\n+#define SD10G_LANE_LANE_23(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 140, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_23_CFG_DFE_PD            BIT(0)\n+#define SD10G_LANE_LANE_23_CFG_DFE_PD_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_23_CFG_DFE_PD, x)\n+#define SD10G_LANE_LANE_23_CFG_DFE_PD_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_23_CFG_DFE_PD, x)\n+\n+#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG         BIT(1)\n+#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)\n+#define SD10G_LANE_LANE_23_CFG_EN_DFEDIG_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_23_CFG_EN_DFEDIG, x)\n+\n+#define SD10G_LANE_LANE_23_CFG_DFECK_EN          BIT(2)\n+#define SD10G_LANE_LANE_23_CFG_DFECK_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)\n+#define SD10G_LANE_LANE_23_CFG_DFECK_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_23_CFG_DFECK_EN, x)\n+\n+#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD         BIT(3)\n+#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)\n+#define SD10G_LANE_LANE_23_CFG_ERRAMP_PD_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_23_CFG_ERRAMP_PD, x)\n+\n+#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0      GENMASK(6, 4)\n+#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)\n+#define SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_23_CFG_DFEDIG_M_2_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_24 */\n+#define SD10G_LANE_LANE_24(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 144, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0    GENMASK(3, 0)\n+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)\n+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN1_3_0, x)\n+\n+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0    GENMASK(7, 4)\n+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)\n+#define SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_24_CFG_PI_BW_GEN2_3_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_26 */\n+#define SD10G_LANE_LANE_26(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 152, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0 GENMASK(7, 0)\n+#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)\n+#define SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_26_CFG_ISCAN_EXT_DAC_7_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_2F */\n+#define SD10G_LANE_LANE_2F(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 188, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0        GENMASK(2, 0)\n+#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)\n+#define SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CP_2_0, x)\n+\n+#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0      GENMASK(7, 4)\n+#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)\n+#define SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_2F_CFG_VGA_CTRL_3_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_30 */\n+#define SD10G_LANE_LANE_30(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 192, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_30_CFG_SUMMER_EN         BIT(0)\n+#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)\n+#define SD10G_LANE_LANE_30_CFG_SUMMER_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_30_CFG_SUMMER_EN, x)\n+\n+#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0     GENMASK(6, 4)\n+#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)\n+#define SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_30_CFG_RXDIV_SEL_2_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_31 */\n+#define SD10G_LANE_LANE_31(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 196, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_31_CFG_PI_RSTN           BIT(0)\n+#define SD10G_LANE_LANE_31_CFG_PI_RSTN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)\n+#define SD10G_LANE_LANE_31_CFG_PI_RSTN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_31_CFG_PI_RSTN, x)\n+\n+#define SD10G_LANE_LANE_31_CFG_CDR_RSTN          BIT(1)\n+#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)\n+#define SD10G_LANE_LANE_31_CFG_CDR_RSTN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_31_CFG_CDR_RSTN, x)\n+\n+#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG       BIT(2)\n+#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)\n+#define SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DFEDIG, x)\n+\n+#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN         BIT(3)\n+#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)\n+#define SD10G_LANE_LANE_31_CFG_CTLE_RSTN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_31_CFG_CTLE_RSTN, x)\n+\n+#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8       BIT(4)\n+#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)\n+#define SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_31_CFG_RSTN_DIV5_8, x)\n+\n+#define SD10G_LANE_LANE_31_CFG_R50_EN            BIT(5)\n+#define SD10G_LANE_LANE_31_CFG_R50_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_31_CFG_R50_EN, x)\n+#define SD10G_LANE_LANE_31_CFG_R50_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_31_CFG_R50_EN, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_32 */\n+#define SD10G_LANE_LANE_32(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 200, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0 GENMASK(1, 0)\n+#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)\n+#define SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCLK_BASE_1_0, x)\n+\n+#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)\n+#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)\n+#define SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_32_CFG_ITX_IPCML_BASE_1_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_33 */\n+#define SD10G_LANE_LANE_33(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 204, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)\n+#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)\n+#define SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPDRIVER_BASE_2_0, x)\n+\n+#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0 GENMASK(5, 4)\n+#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)\n+#define SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_33_CFG_ITX_IPPREEMP_BASE_1_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_35 */\n+#define SD10G_LANE_LANE_35(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 212, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0        GENMASK(1, 0)\n+#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)\n+#define SD10G_LANE_LANE_35_CFG_TXRATE_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_35_CFG_TXRATE_1_0, x)\n+\n+#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0        GENMASK(5, 4)\n+#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)\n+#define SD10G_LANE_LANE_35_CFG_RXRATE_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_35_CFG_RXRATE_1_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_36 */\n+#define SD10G_LANE_LANE_36(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 216, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0 GENMASK(1, 0)\n+#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)\n+#define SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_36_CFG_PREDRV_SLEWRATE_1_0, x)\n+\n+#define SD10G_LANE_LANE_36_CFG_EID_LP            BIT(4)\n+#define SD10G_LANE_LANE_36_CFG_EID_LP_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_36_CFG_EID_LP, x)\n+#define SD10G_LANE_LANE_36_CFG_EID_LP_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_36_CFG_EID_LP, x)\n+\n+#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH    BIT(5)\n+#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)\n+#define SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_36_CFG_EN_PREDRV_EMPH, x)\n+\n+#define SD10G_LANE_LANE_36_CFG_PRBS_SEL          BIT(6)\n+#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)\n+#define SD10G_LANE_LANE_36_CFG_PRBS_SEL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SEL, x)\n+\n+#define SD10G_LANE_LANE_36_CFG_PRBS_SETB         BIT(7)\n+#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)\n+#define SD10G_LANE_LANE_36_CFG_PRBS_SETB_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_36_CFG_PRBS_SETB, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_37 */\n+#define SD10G_LANE_LANE_37(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 220, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD     BIT(0)\n+#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)\n+#define SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_37_CFG_RXDET_COMP_PD, x)\n+\n+#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE      BIT(1)\n+#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)\n+#define SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_37_CFG_PD_RX_CKTREE, x)\n+\n+#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF      BIT(2)\n+#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)\n+#define SD10G_LANE_LANE_37_CFG_TXSWING_HALF_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_37_CFG_TXSWING_HALF, x)\n+\n+#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0   GENMASK(5, 4)\n+#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)\n+#define SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_37_CFG_IP_PRE_BASE_1_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_39 */\n+#define SD10G_LANE_LANE_39(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 228, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0      GENMASK(2, 0)\n+#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)\n+#define SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_39_CFG_RXFILT_Y_2_0, x)\n+\n+#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH         BIT(4)\n+#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)\n+#define SD10G_LANE_LANE_39_CFG_RX_SSC_LH_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_39_CFG_RX_SSC_LH, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3A */\n+#define SD10G_LANE_LANE_3A(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 232, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0        GENMASK(3, 0)\n+#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)\n+#define SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MIN_3_0, x)\n+\n+#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0        GENMASK(7, 4)\n+#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)\n+#define SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_3A_CFG_MP_MAX_3_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_3C */\n+#define SD10G_LANE_LANE_3C(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 240, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_3C_CFG_DIS_ACC           BIT(0)\n+#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)\n+#define SD10G_LANE_LANE_3C_CFG_DIS_ACC_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_ACC, x)\n+\n+#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER      BIT(1)\n+#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)\n+#define SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_3C_CFG_DIS_2NDORDER, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_40 */\n+#define SD10G_LANE_LANE_40(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 256, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0  GENMASK(7, 0)\n+#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)\n+#define SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_40_CFG_LANE_RESERVE_7_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_41 */\n+#define SD10G_LANE_LANE_41(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 260, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8 GENMASK(7, 0)\n+#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)\n+#define SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_41_CFG_LANE_RESERVE_15_8, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_0:LANE_42 */\n+#define SD10G_LANE_LANE_42(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 0, 0, 1, 288, 264, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0   GENMASK(2, 0)\n+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)\n+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN1_2_0, x)\n+\n+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0   GENMASK(6, 4)\n+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)\n+#define SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_42_CFG_CDR_KF_GEN2_2_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_48 */\n+#define SD10G_LANE_LANE_48(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 0, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0      GENMASK(3, 0)\n+#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)\n+#define SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_48_CFG_ALOS_THR_3_0, x)\n+\n+#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL      BIT(4)\n+#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)\n+#define SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_48_CFG_AUX_RXCK_SEL, x)\n+\n+#define SD10G_LANE_LANE_48_CFG_CLK_ENQ           BIT(5)\n+#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)\n+#define SD10G_LANE_LANE_48_CFG_CLK_ENQ_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_48_CFG_CLK_ENQ, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_1:LANE_50 */\n+#define SD10G_LANE_LANE_50(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 288, 0, 1, 40, 32, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0   GENMASK(1, 0)\n+#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)\n+#define SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_PI_STEP_1_0, x)\n+\n+#define SD10G_LANE_LANE_50_CFG_SSC_RESETB        BIT(4)\n+#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)\n+#define SD10G_LANE_LANE_50_CFG_SSC_RESETB_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RESETB, x)\n+\n+#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL   BIT(5)\n+#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)\n+#define SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_50_CFG_SSC_RTL_CLK_SEL, x)\n+\n+#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL      BIT(6)\n+#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)\n+#define SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_50_CFG_AUX_TXCK_SEL, x)\n+\n+#define SD10G_LANE_LANE_50_CFG_JT_EN             BIT(7)\n+#define SD10G_LANE_LANE_50_CFG_JT_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_50_CFG_JT_EN, x)\n+#define SD10G_LANE_LANE_50_CFG_JT_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_50_CFG_JT_EN, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_2:LANE_52 */\n+#define SD10G_LANE_LANE_52(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 328, 0, 1, 24, 0, 0, \\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0 GENMASK(5, 0)\n+#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)\n+#define SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_52_CFG_IBIAS_TUNE_RESERVE_5_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_4:LANE_83 */\n+#define SD10G_LANE_LANE_83(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 464, 0, 1, 112, 60,  \\\n+\t      0, 1, 4)\n+\n+#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE      BIT(0)\n+#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)\n+#define SD10G_LANE_LANE_83_R_TX_BIT_REVERSE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_83_R_TX_BIT_REVERSE, x)\n+\n+#define SD10G_LANE_LANE_83_R_TX_POL_INV          BIT(1)\n+#define SD10G_LANE_LANE_83_R_TX_POL_INV_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_83_R_TX_POL_INV, x)\n+#define SD10G_LANE_LANE_83_R_TX_POL_INV_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_83_R_TX_POL_INV, x)\n+\n+#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE      BIT(2)\n+#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)\n+#define SD10G_LANE_LANE_83_R_RX_BIT_REVERSE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_83_R_RX_BIT_REVERSE, x)\n+\n+#define SD10G_LANE_LANE_83_R_RX_POL_INV          BIT(3)\n+#define SD10G_LANE_LANE_83_R_RX_POL_INV_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_83_R_RX_POL_INV, x)\n+#define SD10G_LANE_LANE_83_R_RX_POL_INV_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_83_R_RX_POL_INV, x)\n+\n+#define SD10G_LANE_LANE_83_R_DFE_RSTN            BIT(4)\n+#define SD10G_LANE_LANE_83_R_DFE_RSTN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_83_R_DFE_RSTN, x)\n+#define SD10G_LANE_LANE_83_R_DFE_RSTN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_83_R_DFE_RSTN, x)\n+\n+#define SD10G_LANE_LANE_83_R_CDR_RSTN            BIT(5)\n+#define SD10G_LANE_LANE_83_R_CDR_RSTN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_83_R_CDR_RSTN, x)\n+#define SD10G_LANE_LANE_83_R_CDR_RSTN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_83_R_CDR_RSTN, x)\n+\n+#define SD10G_LANE_LANE_83_R_CTLE_RSTN           BIT(6)\n+#define SD10G_LANE_LANE_83_R_CTLE_RSTN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)\n+#define SD10G_LANE_LANE_83_R_CTLE_RSTN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_83_R_CTLE_RSTN, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_93 */\n+#define SD10G_LANE_LANE_93(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 12, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN    BIT(0)\n+#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)\n+#define SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_RXEI_FIFO_RST_EN, x)\n+\n+#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT BIT(1)\n+#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)\n+#define SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_DWIDTHCTRL_FROM_HWT, x)\n+\n+#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE     BIT(2)\n+#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)\n+#define SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_DIS_RESTORE_DFE, x)\n+\n+#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL     BIT(3)\n+#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)\n+#define SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_EN_RATECHG_CTRL, x)\n+\n+#define SD10G_LANE_LANE_93_R_REG_MANUAL          BIT(4)\n+#define SD10G_LANE_LANE_93_R_REG_MANUAL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_REG_MANUAL, x)\n+#define SD10G_LANE_LANE_93_R_REG_MANUAL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_REG_MANUAL, x)\n+\n+#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT   BIT(5)\n+#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)\n+#define SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_AUXCKSEL_FROM_HWT, x)\n+\n+#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT    BIT(6)\n+#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)\n+#define SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_LANE_ID_FROM_HWT, x)\n+\n+#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT BIT(7)\n+#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)\n+#define SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_93_R_RX_PCIE_GEN12_FROM_HWT, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_94 */\n+#define SD10G_LANE_LANE_94(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 16, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0      GENMASK(2, 0)\n+#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)\n+#define SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_94_R_DWIDTHCTRL_2_0, x)\n+\n+#define SD10G_LANE_LANE_94_R_ISCAN_REG           BIT(4)\n+#define SD10G_LANE_LANE_94_R_ISCAN_REG_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_94_R_ISCAN_REG, x)\n+#define SD10G_LANE_LANE_94_R_ISCAN_REG_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_94_R_ISCAN_REG, x)\n+\n+#define SD10G_LANE_LANE_94_R_TXEQ_REG            BIT(5)\n+#define SD10G_LANE_LANE_94_R_TXEQ_REG_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_94_R_TXEQ_REG, x)\n+#define SD10G_LANE_LANE_94_R_TXEQ_REG_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_94_R_TXEQ_REG, x)\n+\n+#define SD10G_LANE_LANE_94_R_MISC_REG            BIT(6)\n+#define SD10G_LANE_LANE_94_R_MISC_REG_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_94_R_MISC_REG, x)\n+#define SD10G_LANE_LANE_94_R_MISC_REG_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_94_R_MISC_REG, x)\n+\n+#define SD10G_LANE_LANE_94_R_SWING_REG           BIT(7)\n+#define SD10G_LANE_LANE_94_R_SWING_REG_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_94_R_SWING_REG, x)\n+#define SD10G_LANE_LANE_94_R_SWING_REG_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_94_R_SWING_REG, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_5:LANE_9E */\n+#define SD10G_LANE_LANE_9E(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 576, 0, 1, 64, 56, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_9E_R_RXEQ_REG            BIT(0)\n+#define SD10G_LANE_LANE_9E_R_RXEQ_REG_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)\n+#define SD10G_LANE_LANE_9E_R_RXEQ_REG_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_9E_R_RXEQ_REG, x)\n+\n+#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN BIT(1)\n+#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)\n+#define SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_9E_R_AUTO_RST_TREE_PD_MAN, x)\n+\n+#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN    BIT(2)\n+#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)\n+#define SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_9E_R_EN_AUTO_CDR_RSTN, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A1 */\n+#define SD10G_LANE_LANE_A1(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 4, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0 GENMASK(1, 0)\n+#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)\n+#define SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_A1_R_PMA_TXCK_DIV_SEL_1_0, x)\n+\n+#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT        BIT(4)\n+#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)\n+#define SD10G_LANE_LANE_A1_R_SSC_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_A1_R_SSC_FROM_HWT, x)\n+\n+#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT        BIT(5)\n+#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)\n+#define SD10G_LANE_LANE_A1_R_CDR_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_A1_R_CDR_FROM_HWT, x)\n+\n+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT BIT(6)\n+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)\n+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING_FROM_HWT, x)\n+\n+#define SD10G_LANE_LANE_A1_R_PCLK_GATING         BIT(7)\n+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)\n+#define SD10G_LANE_LANE_A1_R_PCLK_GATING_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_A1_R_PCLK_GATING, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_6:LANE_A2 */\n+#define SD10G_LANE_LANE_A2(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 640, 0, 1, 128, 8, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0 GENMASK(4, 0)\n+#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)\n+#define SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_A2_R_PCS2PMA_PHYMODE_4_0, x)\n+\n+/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */\n+#define SD10G_LANE_LANE_DF(t)                                                  \\\n+\t__REG(TARGET_SD10G_LANE, t, TSIZE(TC_SD10G_LANE), 832, 0, 1, 84, 60, 0,\\\n+\t      1, 4)\n+\n+#define SD10G_LANE_LANE_DF_LOL_UDL               BIT(0)\n+#define SD10G_LANE_LANE_DF_LOL_UDL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_DF_LOL_UDL, x)\n+#define SD10G_LANE_LANE_DF_LOL_UDL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_DF_LOL_UDL, x)\n+\n+#define SD10G_LANE_LANE_DF_LOL                   BIT(1)\n+#define SD10G_LANE_LANE_DF_LOL_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_DF_LOL, x)\n+#define SD10G_LANE_LANE_DF_LOL_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_DF_LOL, x)\n+\n+#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED BIT(2)\n+#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)\n+#define SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)\n+\n+#define SD10G_LANE_LANE_DF_SQUELCH               BIT(3)\n+#define SD10G_LANE_LANE_DF_SQUELCH_SET(x)\\\n+\tFIELD_PREP(SD10G_LANE_LANE_DF_SQUELCH, x)\n+#define SD10G_LANE_LANE_DF_SQUELCH_GET(x)\\\n+\tFIELD_GET(SD10G_LANE_LANE_DF_SQUELCH, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_09 */\n+#define SD25G_LANE_CMU_09(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 36, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN      BIT(0)\n+#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)\n+#define SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_09_CFG_REFCK_TERM_EN, x)\n+\n+#define SD25G_LANE_CMU_09_CFG_EN_DUMMY           BIT(1)\n+#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)\n+#define SD25G_LANE_CMU_09_CFG_EN_DUMMY_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_09_CFG_EN_DUMMY, x)\n+\n+#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET        BIT(2)\n+#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)\n+#define SD25G_LANE_CMU_09_CFG_PLL_LOS_SET_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_LOS_SET, x)\n+\n+#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD      BIT(3)\n+#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)\n+#define SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_09_CFG_CTRL_LOGIC_PD, x)\n+\n+#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0     GENMASK(5, 4)\n+#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)\n+#define SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_09_CFG_PLL_TP_SEL_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_0B */\n+#define SD25G_LANE_CMU_0B(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 44, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT      BIT(0)\n+#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)\n+#define SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_FORCE_RX_FILT, x)\n+\n+#define SD25G_LANE_CMU_0B_CFG_DISLOL             BIT(1)\n+#define SD25G_LANE_CMU_0B_CFG_DISLOL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOL, x)\n+#define SD25G_LANE_CMU_0B_CFG_DISLOL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOL, x)\n+\n+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN BIT(2)\n+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)\n+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_EN, x)\n+\n+#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN     BIT(3)\n+#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)\n+#define SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_VCO_CAL_RESETN, x)\n+\n+#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD          BIT(4)\n+#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)\n+#define SD25G_LANE_CMU_0B_CFG_VFILT2PAD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_VFILT2PAD, x)\n+\n+#define SD25G_LANE_CMU_0B_CFG_DISLOS             BIT(5)\n+#define SD25G_LANE_CMU_0B_CFG_DISLOS_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_DISLOS, x)\n+#define SD25G_LANE_CMU_0B_CFG_DISLOS_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_DISLOS, x)\n+\n+#define SD25G_LANE_CMU_0B_CFG_DCLOL              BIT(6)\n+#define SD25G_LANE_CMU_0B_CFG_DCLOL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_DCLOL, x)\n+#define SD25G_LANE_CMU_0B_CFG_DCLOL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_DCLOL, x)\n+\n+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN    BIT(7)\n+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)\n+#define SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0B_CFG_RST_TREE_PD_MAN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_0C */\n+#define SD25G_LANE_CMU_0C(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 48, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET        BIT(0)\n+#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)\n+#define SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0C_CFG_PLL_LOL_SET, x)\n+\n+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN        BIT(1)\n+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)\n+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_DN, x)\n+\n+#define SD25G_LANE_CMU_0C_CFG_VCO_PD             BIT(2)\n+#define SD25G_LANE_CMU_0C_CFG_VCO_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)\n+#define SD25G_LANE_CMU_0C_CFG_VCO_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_PD, x)\n+\n+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP        BIT(3)\n+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)\n+#define SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0C_CFG_EN_TX_CK_UP, x)\n+\n+#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0   GENMASK(5, 4)\n+#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)\n+#define SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0C_CFG_VCO_DIV_MODE_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_0D */\n+#define SD25G_LANE_CMU_0D(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 52, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD         BIT(0)\n+#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)\n+#define SD25G_LANE_CMU_0D_CFG_CK_TREE_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0D_CFG_CK_TREE_PD, x)\n+\n+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN        BIT(1)\n+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)\n+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_DN, x)\n+\n+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP        BIT(2)\n+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)\n+#define SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0D_CFG_EN_RX_CK_UP, x)\n+\n+#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP        BIT(3)\n+#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)\n+#define SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0D_CFG_VCO_CAL_BYP, x)\n+\n+#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0     GENMASK(5, 4)\n+#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)\n+#define SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0D_CFG_PRE_DIVSEL_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_0E */\n+#define SD25G_LANE_CMU_0E(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 56, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0        GENMASK(3, 0)\n+#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)\n+#define SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0E_CFG_SEL_DIV_3_0, x)\n+\n+#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD   BIT(4)\n+#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)\n+#define SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_0E_CFG_PMAA_CENTR_CK_PD, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_13 */\n+#define SD25G_LANE_CMU_13(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 76, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0    GENMASK(3, 0)\n+#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)\n+#define SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_13_CFG_PLL_RESERVE_3_0, x)\n+\n+#define SD25G_LANE_CMU_13_CFG_JT_EN              BIT(4)\n+#define SD25G_LANE_CMU_13_CFG_JT_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_13_CFG_JT_EN, x)\n+#define SD25G_LANE_CMU_13_CFG_JT_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_13_CFG_JT_EN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_18 */\n+#define SD25G_LANE_CMU_18(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 96, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_18_R_PLL_RSTN             BIT(0)\n+#define SD25G_LANE_CMU_18_R_PLL_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_18_R_PLL_RSTN, x)\n+#define SD25G_LANE_CMU_18_R_PLL_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_18_R_PLL_RSTN, x)\n+\n+#define SD25G_LANE_CMU_18_R_PLL_LOL_SET          BIT(1)\n+#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)\n+#define SD25G_LANE_CMU_18_R_PLL_LOL_SET_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOL_SET, x)\n+\n+#define SD25G_LANE_CMU_18_R_PLL_LOS_SET          BIT(2)\n+#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)\n+#define SD25G_LANE_CMU_18_R_PLL_LOS_SET_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_18_R_PLL_LOS_SET, x)\n+\n+#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0       GENMASK(5, 4)\n+#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)\n+#define SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_18_R_PLL_TP_SEL_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_19 */\n+#define SD25G_LANE_CMU_19(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 100, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_19_R_CK_RESETB            BIT(0)\n+#define SD25G_LANE_CMU_19_R_CK_RESETB_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_19_R_CK_RESETB, x)\n+#define SD25G_LANE_CMU_19_R_CK_RESETB_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_19_R_CK_RESETB, x)\n+\n+#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN          BIT(1)\n+#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)\n+#define SD25G_LANE_CMU_19_R_PLL_DLOL_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_19_R_PLL_DLOL_EN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_0:CMU_1A */\n+#define SD25G_LANE_CMU_1A(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 0, 0, 1, 132, 104, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0       GENMASK(2, 0)\n+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)\n+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_2_0, x)\n+\n+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT  BIT(4)\n+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)\n+#define SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_1A_R_DWIDTHCTRL_FROM_HWT, x)\n+\n+#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE       BIT(5)\n+#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)\n+#define SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_1A_R_MASK_EI_SOURCE, x)\n+\n+#define SD25G_LANE_CMU_1A_R_REG_MANUAL           BIT(6)\n+#define SD25G_LANE_CMU_1A_R_REG_MANUAL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)\n+#define SD25G_LANE_CMU_1A_R_REG_MANUAL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_1A_R_REG_MANUAL, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_1:CMU_2A */\n+#define SD25G_LANE_CMU_2A(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 36, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0          GENMASK(1, 0)\n+#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)\n+#define SD25G_LANE_CMU_2A_R_DBG_SEL_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_2A_R_DBG_SEL_1_0, x)\n+\n+#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE        BIT(4)\n+#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)\n+#define SD25G_LANE_CMU_2A_R_DBG_LINK_LANE_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LINK_LANE, x)\n+\n+#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS       BIT(5)\n+#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)\n+#define SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_2A_R_DBG_LOL_STATUS, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_1:CMU_30 */\n+#define SD25G_LANE_CMU_30(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 60, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0 GENMASK(2, 0)\n+#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)\n+#define SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_30_R_TXFIFO_CK_DIV_PMAD_2_0, x)\n+\n+#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0 GENMASK(6, 4)\n+#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)\n+#define SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_30_R_RXFIFO_CK_DIV_PMAD_2_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_1:CMU_31 */\n+#define SD25G_LANE_CMU_31(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 132, 0, 1, 124, 64, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0 GENMASK(7, 0)\n+#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)\n+#define SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_31_CFG_COMMON_RESERVE_7_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_2:CMU_40 */\n+#define SD25G_LANE_CMU_40(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 0, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL     BIT(0)\n+#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)\n+#define SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_40_L0_CFG_CKSKEW_CTRL, x)\n+\n+#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD      BIT(1)\n+#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)\n+#define SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_40_L0_CFG_ISCAN_HOLD, x)\n+\n+#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK          BIT(2)\n+#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)\n+#define SD25G_LANE_CMU_40_L0_CFG_PD_CLK_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_40_L0_CFG_PD_CLK, x)\n+\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN        BIT(3)\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_EN, x)\n+\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN    BIT(4)\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_MAN_EN, x)\n+\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST       BIT(5)\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)\n+#define SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_40_L0_CFG_TXCAL_RST, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_2:CMU_45 */\n+#define SD25G_LANE_CMU_45(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 20, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0  GENMASK(7, 0)\n+#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)\n+#define SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_45_L0_CFG_TX_RESERVE_7_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_2:CMU_46 */\n+#define SD25G_LANE_CMU_46(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 256, 0, 1, 512, 24, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8 GENMASK(7, 0)\n+#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)\n+#define SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_46_L0_CFG_TX_RESERVE_15_8, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_3:CMU_C0 */\n+#define SD25G_LANE_CMU_C0(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 768, 0, 1, 252, 0, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0     GENMASK(3, 0)\n+#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)\n+#define SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_C0_READ_VCO_CTUNE_3_0, x)\n+\n+#define SD25G_LANE_CMU_C0_PLL_LOL_UDL            BIT(4)\n+#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)\n+#define SD25G_LANE_CMU_C0_PLL_LOL_UDL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_C0_PLL_LOL_UDL, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:CMU_GRP_4:CMU_FF */\n+#define SD25G_LANE_CMU_FF(t)                                                   \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1020, 0, 1, 4, 0, 0, 1, 4)\n+\n+#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX   GENMASK(7, 0)\n+#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)\n+#define SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_CMU_FF_REGISTER_TABLE_INDEX, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_00 */\n+#define SD25G_LANE_LANE_00(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 0, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0 GENMASK(3, 0)\n+#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)\n+#define SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_VC_DRIVER_3_0, x)\n+\n+#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0 GENMASK(5, 4)\n+#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)\n+#define SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_00_LN_CFG_ITX_IPCML_BASE_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_01 */\n+#define SD25G_LANE_LANE_01(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 4, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0 GENMASK(2, 0)\n+#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)\n+#define SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_01_LN_CFG_ITX_IPDRIVER_BASE_2_0, x)\n+\n+#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0  GENMASK(5, 4)\n+#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)\n+#define SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_01_LN_CFG_TX_PREDIV_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_03 */\n+#define SD25G_LANE_LANE_03(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 12, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0    GENMASK(4, 0)\n+#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)\n+#define SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_03_LN_CFG_TAP_DLY_4_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_04 */\n+#define SD25G_LANE_LANE_04(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 16, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN    BIT(0)\n+#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)\n+#define SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TX2RX_LP_EN, x)\n+\n+#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN    BIT(1)\n+#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)\n+#define SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_04_LN_CFG_RX2TX_LP_EN, x)\n+\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_CML         BIT(2)\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_CML_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CML, x)\n+\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK         BIT(3)\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_CLK_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_CLK, x)\n+\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER      BIT(4)\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)\n+#define SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_04_LN_CFG_PD_DRIVER, x)\n+\n+#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN       BIT(5)\n+#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)\n+#define SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_04_LN_CFG_TAP_MAIN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_05 */\n+#define SD25G_LANE_LANE_05(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 20, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0   GENMASK(3, 0)\n+#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)\n+#define SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_05_LN_CFG_TAP_DLY2_3_0, x)\n+\n+#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0         GENMASK(5, 4)\n+#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)\n+#define SD25G_LANE_LANE_05_LN_CFG_BW_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_05_LN_CFG_BW_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_06 */\n+#define SD25G_LANE_LANE_06(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 24, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN        BIT(0)\n+#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)\n+#define SD25G_LANE_LANE_06_LN_CFG_EN_MAIN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_06_LN_CFG_EN_MAIN, x)\n+\n+#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0    GENMASK(7, 4)\n+#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)\n+#define SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_06_LN_CFG_TAP_ADV_3_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_07 */\n+#define SD25G_LANE_LANE_07(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 28, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV         BIT(0)\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_ADV_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_ADV, x)\n+\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2        BIT(1)\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY2_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY2, x)\n+\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY         BIT(2)\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)\n+#define SD25G_LANE_LANE_07_LN_CFG_EN_DLY_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_07_LN_CFG_EN_DLY, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_09 */\n+#define SD25G_LANE_LANE_09(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 36, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0 GENMASK(3, 0)\n+#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)\n+#define SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_09_LN_CFG_TXCAL_VALID_SEL_3_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_0A */\n+#define SD25G_LANE_LANE_0A(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 40, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0 GENMASK(5, 0)\n+#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)\n+#define SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0A_LN_CFG_TXCAL_SHIFT_CODE_5_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_0B */\n+#define SD25G_LANE_LANE_0B(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 44, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN   BIT(0)\n+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)\n+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_MAN_EN, x)\n+\n+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST      BIT(1)\n+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)\n+#define SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_TXCAL_RST, x)\n+\n+#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0   GENMASK(5, 4)\n+#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)\n+#define SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0B_LN_CFG_QUAD_MAN_1_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_0C */\n+#define SD25G_LANE_LANE_0C(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 48, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0 GENMASK(2, 0)\n+#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)\n+#define SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_PMA_TX_CK_BITWIDTH_2_0, x)\n+\n+#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN       BIT(4)\n+#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)\n+#define SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_TXCAL_EN, x)\n+\n+#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD      BIT(5)\n+#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)\n+#define SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0C_LN_CFG_RXTERM_PD, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_0D */\n+#define SD25G_LANE_LANE_0D(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 52, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0     GENMASK(2, 0)\n+#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)\n+#define SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RXTERM_2_0, x)\n+\n+#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8    BIT(4)\n+#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)\n+#define SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_RSTN_DIV5_8, x)\n+\n+#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN      BIT(5)\n+#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)\n+#define SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_SUMMER_EN, x)\n+\n+#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD        BIT(6)\n+#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)\n+#define SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DMUX_PD, x)\n+\n+#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN       BIT(7)\n+#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)\n+#define SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0D_LN_CFG_DFECK_EN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_0E */\n+#define SD25G_LANE_LANE_0E(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 56, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN       BIT(0)\n+#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)\n+#define SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_ISCAN_EN, x)\n+\n+#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD    BIT(1)\n+#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)\n+#define SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DMUX_CLK_PD, x)\n+\n+#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG      BIT(2)\n+#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)\n+#define SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_EN_DFEDIG, x)\n+\n+#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0   GENMASK(6, 4)\n+#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)\n+#define SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0E_LN_CFG_DFEDIG_M_2_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_0F */\n+#define SD25G_LANE_LANE_0F(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 60, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1  GENMASK(4, 0)\n+#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)\n+#define SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_0F_LN_CFG_DFETAP_EN_5_1, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_18 */\n+#define SD25G_LANE_LANE_18(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 96, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN       BIT(0)\n+#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)\n+#define SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_18_LN_CFG_CDRCK_EN, x)\n+\n+#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT       BIT(1)\n+#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)\n+#define SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ADD_VOLT, x)\n+\n+#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN    BIT(2)\n+#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)\n+#define SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_18_LN_CFG_MAN_VOLT_EN, x)\n+\n+#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD      BIT(3)\n+#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)\n+#define SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_18_LN_CFG_ERRAMP_PD, x)\n+\n+#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0  GENMASK(6, 4)\n+#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)\n+#define SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_18_LN_CFG_RXDIV_SEL_2_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_19 */\n+#define SD25G_LANE_LANE_19(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 100, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD        BIT(0)\n+#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_DCDR_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_DCDR_PD, x)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD        BIT(1)\n+#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_ECDR_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ECDR_PD, x)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL      BIT(2)\n+#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_ISCAN_SEL, x)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN        BIT(3)\n+#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_TXLB_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_TXLB_EN, x)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU      BIT(4)\n+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_PU, x)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP     BIT(5)\n+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_RX_REG_BYP, x)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET     BIT(6)\n+#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_RMS_DET, x)\n+\n+#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE        BIT(7)\n+#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)\n+#define SD25G_LANE_LANE_19_LN_CFG_PD_CTLE_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_19_LN_CFG_PD_CTLE, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_1A */\n+#define SD25G_LANE_LANE_1A(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 104, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN     BIT(0)\n+#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)\n+#define SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CTLE_TP_EN, x)\n+\n+#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0     GENMASK(6, 4)\n+#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)\n+#define SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1A_LN_CFG_CDR_KF_2_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_1B */\n+#define SD25G_LANE_LANE_1B(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 108, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0      GENMASK(7, 0)\n+#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)\n+#define SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1B_LN_CFG_CDR_M_7_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_1C */\n+#define SD25G_LANE_LANE_1C(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 112, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN       BIT(0)\n+#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)\n+#define SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_CDR_RSTN, x)\n+\n+#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD         BIT(1)\n+#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)\n+#define SD25G_LANE_LANE_1C_LN_CFG_DFE_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFE_PD, x)\n+\n+#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD      BIT(2)\n+#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)\n+#define SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_DFEDMX_PD, x)\n+\n+#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0  GENMASK(7, 4)\n+#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)\n+#define SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1C_LN_CFG_EQC_FORCE_3_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_1D */\n+#define SD25G_LANE_LANE_1D(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 116, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR  BIT(0)\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_EXT_OVR, x)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD     BIT(1)\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_HOLD, x)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN     BIT(2)\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_ISCAN_RSTN, x)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP   BIT(3)\n+#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_AGC_ADPT_BYP, x)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T        BIT(4)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PHID_1T_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PHID_1T, x)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN      BIT(5)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_DFE_EN, x)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR     BIT(6)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_EXT_OVR, x)\n+\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD        BIT(7)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)\n+#define SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1D_LN_CFG_PI_HOLD, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_1E */\n+#define SD25G_LANE_LANE_1E(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 120, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0   GENMASK(1, 0)\n+#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)\n+#define SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PI_STEPS_1_0, x)\n+\n+#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN        BIT(4)\n+#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)\n+#define SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_RXLB_EN, x)\n+\n+#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN   BIT(5)\n+#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)\n+#define SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_SUM_SETCM_EN, x)\n+\n+#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR   BIT(6)\n+#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)\n+#define SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_R_OFFSET_DIR, x)\n+\n+#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD     BIT(7)\n+#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)\n+#define SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_1E_LN_CFG_PMAD_CK_PD, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_21 */\n+#define SD25G_LANE_LANE_21(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 132, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0 GENMASK(4, 0)\n+#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)\n+#define SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_21_LN_CFG_VGA_CTRL_BYP_4_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_22 */\n+#define SD25G_LANE_LANE_22(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 136, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0  GENMASK(3, 0)\n+#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)\n+#define SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_22_LN_CFG_EQR_FORCE_3_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_25 */\n+#define SD25G_LANE_LANE_25(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 148, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0 GENMASK(6, 0)\n+#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)\n+#define SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_25_LN_CFG_INIT_POS_ISCAN_6_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_26 */\n+#define SD25G_LANE_LANE_26(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 152, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0 GENMASK(6, 0)\n+#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)\n+#define SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_26_LN_CFG_INIT_POS_IPI_6_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_28 */\n+#define SD25G_LANE_LANE_28(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 160, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN  BIT(0)\n+#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)\n+#define SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_28_LN_CFG_ISCAN_MODE_EN, x)\n+\n+#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH      BIT(1)\n+#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)\n+#define SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SSC_LH, x)\n+\n+#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL   BIT(2)\n+#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)\n+#define SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_28_LN_CFG_FIGMERIT_SEL, x)\n+\n+#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0 GENMASK(6, 4)\n+#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)\n+#define SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_28_LN_CFG_RX_SUBRATE_2_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_2B */\n+#define SD25G_LANE_LANE_2B(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 172, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0      GENMASK(3, 0)\n+#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)\n+#define SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_PI_BW_3_0, x)\n+\n+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR BIT(4)\n+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)\n+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_DMUX_SUBR, x)\n+\n+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU    BIT(5)\n+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)\n+#define SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2B_LN_CFG_RSTN_TXDUPU, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_2C */\n+#define SD25G_LANE_LANE_2C(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 176, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0 GENMASK(2, 0)\n+#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)\n+#define SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_TX_SUBRATE_2_0, x)\n+\n+#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER   BIT(4)\n+#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)\n+#define SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2C_LN_CFG_DIS_2NDORDER, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_2D */\n+#define SD25G_LANE_LANE_2D(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 180, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0   GENMASK(2, 0)\n+#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)\n+#define SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_ALOS_THR_2_0, x)\n+\n+#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0 GENMASK(6, 4)\n+#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)\n+#define SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2D_LN_CFG_SAT_CNTSEL_2_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_2E */\n+#define SD25G_LANE_LANE_2E(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 184, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN  BIT(0)\n+#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_EN_FAST_ISCAN, x)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ         BIT(1)\n+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_SQ, x)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ          BIT(2)\n+#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_PD_SQ_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PD_SQ, x)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS       BIT(3)\n+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_DIS_ALOS, x)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC     BIT(4)\n+#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RESETN_AGC, x)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG    BIT(5)\n+#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_RSTN_DFEDIG, x)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN        BIT(6)\n+#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_PI_RSTN, x)\n+\n+#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN      BIT(7)\n+#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)\n+#define SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_2E_LN_CFG_CTLE_RSTN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_40 */\n+#define SD25G_LANE_LANE_40(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 256, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE   BIT(0)\n+#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)\n+#define SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_BIT_REVERSE, x)\n+\n+#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV       BIT(1)\n+#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)\n+#define SD25G_LANE_LANE_40_LN_R_TX_POL_INV_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_40_LN_R_TX_POL_INV, x)\n+\n+#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE   BIT(2)\n+#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)\n+#define SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_BIT_REVERSE, x)\n+\n+#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV       BIT(3)\n+#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)\n+#define SD25G_LANE_LANE_40_LN_R_RX_POL_INV_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_40_LN_R_RX_POL_INV, x)\n+\n+#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN         BIT(4)\n+#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)\n+#define SD25G_LANE_LANE_40_LN_R_CDR_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_40_LN_R_CDR_RSTN, x)\n+\n+#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN         BIT(5)\n+#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)\n+#define SD25G_LANE_LANE_40_LN_R_DFE_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_40_LN_R_DFE_RSTN, x)\n+\n+#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN        BIT(6)\n+#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)\n+#define SD25G_LANE_LANE_40_LN_R_CTLE_RSTN_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_40_LN_R_CTLE_RSTN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_42 */\n+#define SD25G_LANE_LANE_42(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 264, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0 GENMASK(7, 0)\n+#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)\n+#define SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_42_LN_CFG_TX_RESERVE_7_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_43 */\n+#define SD25G_LANE_LANE_43(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 268, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8 GENMASK(7, 0)\n+#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)\n+#define SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_43_LN_CFG_TX_RESERVE_15_8, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_44 */\n+#define SD25G_LANE_LANE_44(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 272, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0 GENMASK(7, 0)\n+#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)\n+#define SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_44_LN_CFG_RX_RESERVE_7_0, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_0:LANE_45 */\n+#define SD25G_LANE_LANE_45(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1024, 0, 1, 768, 276, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8 GENMASK(7, 0)\n+#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)\n+#define SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_45_LN_CFG_RX_RESERVE_15_8, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_TARGET:LANE_GRP_1:LANE_DE */\n+#define SD25G_LANE_LANE_DE(t)                                                  \\\n+\t__REG(TARGET_SD25G_LANE, t, 8, 1792, 0, 1, 128, 120, 0, 1, 4)\n+\n+#define SD25G_LANE_LANE_DE_LN_LOL_UDL            BIT(0)\n+#define SD25G_LANE_LANE_DE_LN_LOL_UDL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)\n+#define SD25G_LANE_LANE_DE_LN_LOL_UDL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_DE_LN_LOL_UDL, x)\n+\n+#define SD25G_LANE_LANE_DE_LN_LOL                BIT(1)\n+#define SD25G_LANE_LANE_DE_LN_LOL_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_DE_LN_LOL, x)\n+#define SD25G_LANE_LANE_DE_LN_LOL_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_DE_LN_LOL, x)\n+\n+#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED BIT(2)\n+#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)\n+#define SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_DE_LN_PMA2PCS_RXEI_FILTERED, x)\n+\n+#define SD25G_LANE_LANE_DE_LN_PMA_RXEI           BIT(3)\n+#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_SET(x)\\\n+\tFIELD_PREP(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)\n+#define SD25G_LANE_LANE_DE_LN_PMA_RXEI_GET(x)\\\n+\tFIELD_GET(SD25G_LANE_LANE_DE_LN_PMA_RXEI, x)\n+\n+/* SPARX5 ONLY */\n+/* SD10G_LANE_TARGET:LANE_GRP_8:LANE_DF */\n+#define SD6G_LANE_LANE_DF(t)                                                   \\\n+\t__REG(TARGET_SD6G_LANE, t, 13, 832, 0, 1, 84, 60, 0, 1, 4)\n+\n+#define SD6G_LANE_LANE_DF_LOL_UDL                BIT(0)\n+#define SD6G_LANE_LANE_DF_LOL_UDL_SET(x)\\\n+\tFIELD_PREP(SD6G_LANE_LANE_DF_LOL_UDL, x)\n+#define SD6G_LANE_LANE_DF_LOL_UDL_GET(x)\\\n+\tFIELD_GET(SD6G_LANE_LANE_DF_LOL_UDL, x)\n+\n+#define SD6G_LANE_LANE_DF_LOL                    BIT(1)\n+#define SD6G_LANE_LANE_DF_LOL_SET(x)\\\n+\tFIELD_PREP(SD6G_LANE_LANE_DF_LOL, x)\n+#define SD6G_LANE_LANE_DF_LOL_GET(x)\\\n+\tFIELD_GET(SD6G_LANE_LANE_DF_LOL, x)\n+\n+#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED  BIT(2)\n+#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_SET(x)\\\n+\tFIELD_PREP(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)\n+#define SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED_GET(x)\\\n+\tFIELD_GET(SD6G_LANE_LANE_DF_PMA2PCS_RXEI_FILTERED, x)\n+\n+#define SD6G_LANE_LANE_DF_SQUELCH                BIT(3)\n+#define SD6G_LANE_LANE_DF_SQUELCH_SET(x)\\\n+\tFIELD_PREP(SD6G_LANE_LANE_DF_SQUELCH, x)\n+#define SD6G_LANE_LANE_DF_SQUELCH_GET(x)\\\n+\tFIELD_GET(SD6G_LANE_LANE_DF_SQUELCH, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_0:CMU_00 */\n+#define SD_CMU_CMU_00(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 0, 0, 1, 20, 0, 0, 1, 4)\n+\n+#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE      BIT(0)\n+#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)\n+#define SD_CMU_CMU_00_R_HWT_SIMULATION_MODE_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_00_R_HWT_SIMULATION_MODE, x)\n+\n+#define SD_CMU_CMU_00_CFG_PLL_LOL_SET            BIT(1)\n+#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)\n+#define SD_CMU_CMU_00_CFG_PLL_LOL_SET_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOL_SET, x)\n+\n+#define SD_CMU_CMU_00_CFG_PLL_LOS_SET            BIT(2)\n+#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)\n+#define SD_CMU_CMU_00_CFG_PLL_LOS_SET_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_00_CFG_PLL_LOS_SET, x)\n+\n+#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0         GENMASK(5, 4)\n+#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)\n+#define SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_00_CFG_PLL_TP_SEL_1_0, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_05 */\n+#define SD_CMU_CMU_05(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 0, 0, 1, 4)\n+\n+#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN          BIT(0)\n+#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)\n+#define SD_CMU_CMU_05_CFG_REFCK_TERM_EN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_05_CFG_REFCK_TERM_EN, x)\n+\n+#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0        GENMASK(5, 4)\n+#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)\n+#define SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_05_CFG_BIAS_TP_SEL_1_0, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_06 */\n+#define SD_CMU_CMU_06(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 4, 0, 1, 4)\n+\n+#define SD_CMU_CMU_06_CFG_DISLOS                 BIT(0)\n+#define SD_CMU_CMU_06_CFG_DISLOS_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_DISLOS, x)\n+#define SD_CMU_CMU_06_CFG_DISLOS_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_DISLOS, x)\n+\n+#define SD_CMU_CMU_06_CFG_DISLOL                 BIT(1)\n+#define SD_CMU_CMU_06_CFG_DISLOL_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_DISLOL, x)\n+#define SD_CMU_CMU_06_CFG_DISLOL_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_DISLOL, x)\n+\n+#define SD_CMU_CMU_06_CFG_DCLOL                  BIT(2)\n+#define SD_CMU_CMU_06_CFG_DCLOL_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_DCLOL, x)\n+#define SD_CMU_CMU_06_CFG_DCLOL_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_DCLOL, x)\n+\n+#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT          BIT(3)\n+#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)\n+#define SD_CMU_CMU_06_CFG_FORCE_RX_FILT_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_FORCE_RX_FILT, x)\n+\n+#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD          BIT(4)\n+#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)\n+#define SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_CTRL_LOGIC_PD, x)\n+\n+#define SD_CMU_CMU_06_CFG_VCO_PD                 BIT(5)\n+#define SD_CMU_CMU_06_CFG_VCO_PD_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_VCO_PD, x)\n+#define SD_CMU_CMU_06_CFG_VCO_PD_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_VCO_PD, x)\n+\n+#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN         BIT(6)\n+#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)\n+#define SD_CMU_CMU_06_CFG_VCO_CAL_RESETN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_RESETN, x)\n+\n+#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP            BIT(7)\n+#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)\n+#define SD_CMU_CMU_06_CFG_VCO_CAL_BYP_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_06_CFG_VCO_CAL_BYP, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_08 */\n+#define SD_CMU_CMU_08(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 12, 0, 1, 4)\n+\n+#define SD_CMU_CMU_08_CFG_VFILT2PAD              BIT(0)\n+#define SD_CMU_CMU_08_CFG_VFILT2PAD_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_08_CFG_VFILT2PAD, x)\n+#define SD_CMU_CMU_08_CFG_VFILT2PAD_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_08_CFG_VFILT2PAD, x)\n+\n+#define SD_CMU_CMU_08_CFG_EN_DUMMY               BIT(1)\n+#define SD_CMU_CMU_08_CFG_EN_DUMMY_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_08_CFG_EN_DUMMY, x)\n+#define SD_CMU_CMU_08_CFG_EN_DUMMY_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_08_CFG_EN_DUMMY, x)\n+\n+#define SD_CMU_CMU_08_CFG_CK_TREE_PD             BIT(2)\n+#define SD_CMU_CMU_08_CFG_CK_TREE_PD_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)\n+#define SD_CMU_CMU_08_CFG_CK_TREE_PD_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_08_CFG_CK_TREE_PD, x)\n+\n+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN        BIT(3)\n+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)\n+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN, x)\n+\n+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN     BIT(4)\n+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)\n+#define SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_08_CFG_RST_TREE_PD_MAN_EN, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_09 */\n+#define SD_CMU_CMU_09(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 16, 0, 1, 4)\n+\n+#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP            BIT(0)\n+#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)\n+#define SD_CMU_CMU_09_CFG_EN_TX_CK_UP_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_UP, x)\n+\n+#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN            BIT(1)\n+#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)\n+#define SD_CMU_CMU_09_CFG_EN_TX_CK_DN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_09_CFG_EN_TX_CK_DN, x)\n+\n+#define SD_CMU_CMU_09_CFG_SW_8G                  BIT(4)\n+#define SD_CMU_CMU_09_CFG_SW_8G_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_09_CFG_SW_8G, x)\n+#define SD_CMU_CMU_09_CFG_SW_8G_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_09_CFG_SW_8G, x)\n+\n+#define SD_CMU_CMU_09_CFG_SW_10G                 BIT(5)\n+#define SD_CMU_CMU_09_CFG_SW_10G_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_09_CFG_SW_10G, x)\n+#define SD_CMU_CMU_09_CFG_SW_10G_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_09_CFG_SW_10G, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_1:CMU_0D */\n+#define SD_CMU_CMU_0D(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 20, 0, 1, 72, 32, 0, 1, 4)\n+\n+#define SD_CMU_CMU_0D_CFG_PD_DIV64               BIT(0)\n+#define SD_CMU_CMU_0D_CFG_PD_DIV64_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV64, x)\n+#define SD_CMU_CMU_0D_CFG_PD_DIV64_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV64, x)\n+\n+#define SD_CMU_CMU_0D_CFG_PD_DIV66               BIT(1)\n+#define SD_CMU_CMU_0D_CFG_PD_DIV66_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_0D_CFG_PD_DIV66, x)\n+#define SD_CMU_CMU_0D_CFG_PD_DIV66_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_0D_CFG_PD_DIV66, x)\n+\n+#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD           BIT(2)\n+#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)\n+#define SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_0D_CFG_PMA_TX_CK_PD, x)\n+\n+#define SD_CMU_CMU_0D_CFG_JC_BYP                 BIT(3)\n+#define SD_CMU_CMU_0D_CFG_JC_BYP_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_0D_CFG_JC_BYP, x)\n+#define SD_CMU_CMU_0D_CFG_JC_BYP_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_0D_CFG_JC_BYP, x)\n+\n+#define SD_CMU_CMU_0D_CFG_REFCK_PD               BIT(4)\n+#define SD_CMU_CMU_0D_CFG_REFCK_PD_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_0D_CFG_REFCK_PD, x)\n+#define SD_CMU_CMU_0D_CFG_REFCK_PD_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_0D_CFG_REFCK_PD, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_3:CMU_1B */\n+#define SD_CMU_CMU_1B(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 104, 0, 1, 20, 4, 0, 1, 4)\n+\n+#define SD_CMU_CMU_1B_CFG_RESERVE_7_0            GENMASK(7, 0)\n+#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)\n+#define SD_CMU_CMU_1B_CFG_RESERVE_7_0_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_1B_CFG_RESERVE_7_0, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_4:CMU_1F */\n+#define SD_CMU_CMU_1F(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 124, 0, 1, 68, 0, 0, 1, 4)\n+\n+#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN             BIT(0)\n+#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)\n+#define SD_CMU_CMU_1F_CFG_BIAS_DN_EN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_DN_EN, x)\n+\n+#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN             BIT(1)\n+#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)\n+#define SD_CMU_CMU_1F_CFG_BIAS_UP_EN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_1F_CFG_BIAS_UP_EN, x)\n+\n+#define SD_CMU_CMU_1F_CFG_IC2IP_N                BIT(2)\n+#define SD_CMU_CMU_1F_CFG_IC2IP_N_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_1F_CFG_IC2IP_N, x)\n+#define SD_CMU_CMU_1F_CFG_IC2IP_N_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_1F_CFG_IC2IP_N, x)\n+\n+#define SD_CMU_CMU_1F_CFG_VTUNE_SEL              BIT(3)\n+#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)\n+#define SD_CMU_CMU_1F_CFG_VTUNE_SEL_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_1F_CFG_VTUNE_SEL, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_5:CMU_30 */\n+#define SD_CMU_CMU_30(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 192, 0, 1, 72, 0, 0, 1, 4)\n+\n+#define SD_CMU_CMU_30_R_PLL_DLOL_EN              BIT(0)\n+#define SD_CMU_CMU_30_R_PLL_DLOL_EN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)\n+#define SD_CMU_CMU_30_R_PLL_DLOL_EN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_30_R_PLL_DLOL_EN, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_44 */\n+#define SD_CMU_CMU_44(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 8, 0, 1, 4)\n+\n+#define SD_CMU_CMU_44_R_PLL_RSTN                 BIT(0)\n+#define SD_CMU_CMU_44_R_PLL_RSTN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_44_R_PLL_RSTN, x)\n+#define SD_CMU_CMU_44_R_PLL_RSTN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_44_R_PLL_RSTN, x)\n+\n+#define SD_CMU_CMU_44_R_CK_RESETB                BIT(1)\n+#define SD_CMU_CMU_44_R_CK_RESETB_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_44_R_CK_RESETB, x)\n+#define SD_CMU_CMU_44_R_CK_RESETB_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_44_R_CK_RESETB, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_45 */\n+#define SD_CMU_CMU_45(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 12, 0, 1, 4)\n+\n+#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL          BIT(0)\n+#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)\n+#define SD_CMU_CMU_45_R_EN_RATECHG_CTRL_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_R_EN_RATECHG_CTRL, x)\n+\n+#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT      BIT(1)\n+#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)\n+#define SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_R_DWIDTHCTRL_FROM_HWT, x)\n+\n+#define SD_CMU_CMU_45_RESERVED                   BIT(2)\n+#define SD_CMU_CMU_45_RESERVED_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_RESERVED, x)\n+#define SD_CMU_CMU_45_RESERVED_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_RESERVED, x)\n+\n+#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT    BIT(3)\n+#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)\n+#define SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_R_REFCK_SSC_EN_FROM_HWT, x)\n+\n+#define SD_CMU_CMU_45_RESERVED_2                 BIT(4)\n+#define SD_CMU_CMU_45_RESERVED_2_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_RESERVED_2, x)\n+#define SD_CMU_CMU_45_RESERVED_2_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_RESERVED_2, x)\n+\n+#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT     BIT(5)\n+#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)\n+#define SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_R_LINK_BUF_EN_FROM_HWT, x)\n+\n+#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT         BIT(6)\n+#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)\n+#define SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_R_BIAS_EN_FROM_HWT, x)\n+\n+#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN     BIT(7)\n+#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)\n+#define SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_45_R_AUTO_RST_TREE_PD_MAN, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_6:CMU_47 */\n+#define SD_CMU_CMU_47(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 264, 0, 1, 632, 20, 0, 1, 4)\n+\n+#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0      GENMASK(4, 0)\n+#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)\n+#define SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_47_R_PCS2PMA_PHYMODE_4_0, x)\n+\n+/* SD10G_CMU_TARGET:CMU_GRP_7:CMU_E0 */\n+#define SD_CMU_CMU_E0(t)                                                       \\\n+\t__REG(TARGET_SD_CMU, t, TSIZE(TC_SD_CMU), 896, 0, 1, 8, 0, 0, 1, 4)\n+\n+#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0         GENMASK(3, 0)\n+#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)\n+#define SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_E0_READ_VCO_CTUNE_3_0, x)\n+\n+#define SD_CMU_CMU_E0_PLL_LOL_UDL                BIT(4)\n+#define SD_CMU_CMU_E0_PLL_LOL_UDL_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CMU_E0_PLL_LOL_UDL, x)\n+#define SD_CMU_CMU_E0_PLL_LOL_UDL_GET(x)\\\n+\tFIELD_GET(SD_CMU_CMU_E0_PLL_LOL_UDL, x)\n+\n+/* SD_CMU_TARGET:SD_CMU_CFG:SD_CMU_CFG */\n+#define SD_CMU_CFG_SD_CMU_CFG(t)                                               \\\n+\t__REG(TARGET_SD_CMU_CFG, t, TSIZE(TC_SD_CMU_CFG), 0, 0, 1, 8, 0, 0, 1, \\\n+\t      4)\n+\n+#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST            BIT(0)\n+#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)\n+#define SD_CMU_CFG_SD_CMU_CFG_CMU_RST_GET(x)\\\n+\tFIELD_GET(SD_CMU_CFG_SD_CMU_CFG_CMU_RST, x)\n+\n+#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST        BIT(1)\n+#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_SET(x)\\\n+\tFIELD_PREP(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)\n+#define SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST_GET(x)\\\n+\tFIELD_GET(SD_CMU_CFG_SD_CMU_CFG_EXT_CFG_RST, x)\n+\n+/* SD_LANE_TARGET:SD_RESET:SD_SER_RST */\n+#define SD_LANE_SD_SER_RST(t)                                                  \\\n+\t__REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 0, 0, 1, 4)\n+\n+#define SD_LANE_SD_SER_RST_SER_RST               BIT(0)\n+#define SD_LANE_SD_SER_RST_SER_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_SER_RST_SER_RST, x)\n+#define SD_LANE_SD_SER_RST_SER_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_SER_RST_SER_RST, x)\n+\n+/* SD_LANE_TARGET:SD_RESET:SD_DES_RST */\n+#define SD_LANE_SD_DES_RST(t)                                                  \\\n+\t__REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 0, 0, 1, 8, 4, 0, 1, 4)\n+\n+#define SD_LANE_SD_DES_RST_DES_RST               BIT(0)\n+#define SD_LANE_SD_DES_RST_DES_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_DES_RST_DES_RST, x)\n+#define SD_LANE_SD_DES_RST_DES_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_DES_RST_DES_RST, x)\n+\n+/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */\n+#define SD_LANE_SD_LANE_CFG(t)                                                 \\\n+\t__REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 0, 0, 1, 4)\n+\n+#define SD_LANE_SD_LANE_CFG_MACRO_RST            BIT(0)\n+#define SD_LANE_SD_LANE_CFG_MACRO_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_CFG_MACRO_RST, x)\n+#define SD_LANE_SD_LANE_CFG_MACRO_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_CFG_MACRO_RST, x)\n+\n+#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST          BIT(1)\n+#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)\n+#define SD_LANE_SD_LANE_CFG_EXT_CFG_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_CFG_EXT_CFG_RST, x)\n+\n+#define SD_LANE_SD_LANE_CFG_TX_REF_SEL           GENMASK(5, 4)\n+#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)\n+#define SD_LANE_SD_LANE_CFG_TX_REF_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_CFG_TX_REF_SEL, x)\n+\n+#define SD_LANE_SD_LANE_CFG_RX_REF_SEL           GENMASK(7, 6)\n+#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)\n+#define SD_LANE_SD_LANE_CFG_RX_REF_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_CFG_RX_REF_SEL, x)\n+\n+#define SD_LANE_SD_LANE_CFG_LANE_RST             BIT(8)\n+#define SD_LANE_SD_LANE_CFG_LANE_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RST, x)\n+#define SD_LANE_SD_LANE_CFG_LANE_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RST, x)\n+\n+#define SD_LANE_SD_LANE_CFG_LANE_TX_RST          BIT(9)\n+#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)\n+#define SD_LANE_SD_LANE_CFG_LANE_TX_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_CFG_LANE_TX_RST, x)\n+\n+#define SD_LANE_SD_LANE_CFG_LANE_RX_RST          BIT(10)\n+#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)\n+#define SD_LANE_SD_LANE_CFG_LANE_RX_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_CFG_LANE_RX_RST, x)\n+\n+/* SD_LANE_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */\n+#define SD_LANE_SD_LANE_STAT(t)                                                \\\n+\t__REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 8, 0, 1, 8, 4, 0, 1, 4)\n+\n+#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE        BIT(0)\n+#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)\n+#define SD_LANE_SD_LANE_STAT_PMA_RST_DONE_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_STAT_PMA_RST_DONE, x)\n+\n+#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE        BIT(1)\n+#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)\n+#define SD_LANE_SD_LANE_STAT_DFE_RST_DONE_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_STAT_DFE_RST_DONE, x)\n+\n+#define SD_LANE_SD_LANE_STAT_DBG_OBS             GENMASK(31, 16)\n+#define SD_LANE_SD_LANE_STAT_DBG_OBS_SET(x)\\\n+\tFIELD_PREP(SD_LANE_SD_LANE_STAT_DBG_OBS, x)\n+#define SD_LANE_SD_LANE_STAT_DBG_OBS_GET(x)\\\n+\tFIELD_GET(SD_LANE_SD_LANE_STAT_DBG_OBS, x)\n+\n+/* SD_LANE_TARGET:SD_PWR_CFG:QUIET_MODE_6G */\n+#define SD_LANE_QUIET_MODE_6G(t)                                               \\\n+\t__REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 24, 0, 1, 8, 4, 0, 1, 4)\n+\n+#define SD_LANE_QUIET_MODE_6G_QUIET_MODE         GENMASK(24, 0)\n+#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)\n+#define SD_LANE_QUIET_MODE_6G_QUIET_MODE_GET(x)\\\n+\tFIELD_GET(SD_LANE_QUIET_MODE_6G_QUIET_MODE, x)\n+\n+/* SD_LANE_TARGET:CFG_STAT_FX100:MISC */\n+#define SD_LANE_MISC(t)                                                        \\\n+\t__REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 0, 0, 1, 4)\n+\n+#define SD_LANE_MISC_SD_125_RST_DIS              BIT(0)\n+#define SD_LANE_MISC_SD_125_RST_DIS_SET(x)\\\n+\tFIELD_PREP(SD_LANE_MISC_SD_125_RST_DIS, x)\n+#define SD_LANE_MISC_SD_125_RST_DIS_GET(x)\\\n+\tFIELD_GET(SD_LANE_MISC_SD_125_RST_DIS, x)\n+\n+#define SD_LANE_MISC_RX_ENA                      BIT(1)\n+#define SD_LANE_MISC_RX_ENA_SET(x)\\\n+\tFIELD_PREP(SD_LANE_MISC_RX_ENA, x)\n+#define SD_LANE_MISC_RX_ENA_GET(x)\\\n+\tFIELD_GET(SD_LANE_MISC_RX_ENA, x)\n+\n+#define SD_LANE_MISC_MUX_ENA                     BIT(2)\n+#define SD_LANE_MISC_MUX_ENA_SET(x)\\\n+\tFIELD_PREP(SD_LANE_MISC_MUX_ENA, x)\n+#define SD_LANE_MISC_MUX_ENA_GET(x)\\\n+\tFIELD_GET(SD_LANE_MISC_MUX_ENA, x)\n+\n+/* SPARX5 ONLY */\n+#define SD_LANE_MISC_CORE_CLK_FREQ               GENMASK(5, 4)\n+#define SD_LANE_MISC_CORE_CLK_FREQ_SET(x)\\\n+\tFIELD_PREP(SD_LANE_MISC_CORE_CLK_FREQ, x)\n+#define SD_LANE_MISC_CORE_CLK_FREQ_GET(x)\\\n+\tFIELD_GET(SD_LANE_MISC_CORE_CLK_FREQ, x)\n+\n+/* LAN969X ONLY */\n+#define SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN         GENMASK(10, 8)\n+#define SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN_SET(x)\\\n+\tFIELD_PREP(SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN, x)\n+#define SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN_GET(x)\\\n+\tFIELD_GET(SD_LANE_MISC_FX_RX_CLK_CYCLE_LEN, x)\n+\n+/* SD_LANE_TARGET:CFG_STAT_FX100:M_STAT_MISC */\n+#define SD_LANE_M_STAT_MISC(t)                                                 \\\n+\t__REG(TARGET_SD_LANE, t, TSIZE(TC_SD_LANE), 56, 0, 1, 56, 36, 0, 1, 4)\n+\n+#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM GENMASK(21, 0)\n+#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_SET(x)\\\n+\tFIELD_PREP(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)\n+#define SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM_GET(x)\\\n+\tFIELD_GET(SD_LANE_M_STAT_MISC_M_RIS_EDGE_PTR_ADJ_SUM, x)\n+\n+#define SD_LANE_M_STAT_MISC_M_LOCK_CNT           GENMASK(31, 24)\n+#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_SET(x)\\\n+\tFIELD_PREP(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)\n+#define SD_LANE_M_STAT_MISC_M_LOCK_CNT_GET(x)\\\n+\tFIELD_GET(SD_LANE_M_STAT_MISC_M_LOCK_CNT, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_CFG_TARGET:SD_RESET:SD_SER_RST */\n+#define SD_LANE_25G_SD_SER_RST(t)                                              \\\n+\t__REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 0, 0, 1, 4)\n+\n+#define SD_LANE_25G_SD_SER_RST_SER_RST           BIT(0)\n+#define SD_LANE_25G_SD_SER_RST_SER_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_SER_RST_SER_RST, x)\n+#define SD_LANE_25G_SD_SER_RST_SER_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_SER_RST_SER_RST, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_CFG_TARGET:SD_RESET:SD_DES_RST */\n+#define SD_LANE_25G_SD_DES_RST(t)                                              \\\n+\t__REG(TARGET_SD_LANE_25G, t, 8, 0, 0, 1, 8, 4, 0, 1, 4)\n+\n+#define SD_LANE_25G_SD_DES_RST_DES_RST           BIT(0)\n+#define SD_LANE_25G_SD_DES_RST_DES_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_DES_RST_DES_RST, x)\n+#define SD_LANE_25G_SD_DES_RST_DES_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_DES_RST_DES_RST, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG */\n+#define SD_LANE_25G_SD_LANE_CFG(t)                                             \\\n+\t__REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 0, 0, 1, 4)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST        BIT(0)\n+#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)\n+#define SD_LANE_25G_SD_LANE_CFG_MACRO_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_MACRO_RST, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST      BIT(1)\n+#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)\n+#define SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_EXT_CFG_RST, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE BIT(4)\n+#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)\n+#define SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_HWT_MULTI_LANE_MODE, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE  GENMASK(7, 5)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_PHYMODE, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_LANE_RST         BIT(8)\n+#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)\n+#define SD_LANE_25G_SD_LANE_CFG_LANE_RST_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_LANE_RST, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV       BIT(9)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_ADV, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN      BIT(10)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_MAIN, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY       BIT(11)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_DLY, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV      GENMASK(15, 12)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_ADV, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN     BIT(16)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_MAIN, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY      GENMASK(21, 17)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_TAP_DLY, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN     BIT(22)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_ISCAN_EN, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN BIT(23)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS_EN_FAST_ISCAN, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING  BIT(24)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXSWING, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI     BIT(25)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXEI, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN GENMASK(28, 26)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)\n+#define SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG_PCS2PMA_TXMARGIN, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_CFG2 */\n+#define SD_LANE_25G_SD_LANE_CFG2(t)                                            \\\n+\t__REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 4, 0, 1, 4)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL  GENMASK(2, 0)\n+#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_DATA_WIDTH_SEL, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL    GENMASK(5, 3)\n+#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_TXCK_SEL, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL   GENMASK(8, 6)\n+#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PMA_RXDIV_SEL, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED GENMASK(10, 9)\n+#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_PCS2PMA_TX_SPEED, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV   GENMASK(13, 11)\n+#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXFIFO_CK_DIV, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV   GENMASK(16, 14)\n+#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXFIFO_CK_DIV, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL GENMASK(19, 17)\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_VCO_DIV_SEL, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV GENMASK(23, 20)\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_CFG_SEL_DIV, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL  GENMASK(25, 24)\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_HWT_PRE_DIVSEL, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL      GENMASK(28, 26)\n+#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_TXRATE_SEL, x)\n+\n+#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL      GENMASK(31, 29)\n+#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)\n+#define SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_CFG2_RXRATE_SEL, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_CFG_TARGET:SD_LANE_CFG_STAT:SD_LANE_STAT */\n+#define SD_LANE_25G_SD_LANE_STAT(t)                                            \\\n+\t__REG(TARGET_SD_LANE_25G, t, 8, 8, 0, 1, 12, 8, 0, 1, 4)\n+\n+#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE    BIT(0)\n+#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)\n+#define SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_STAT_PMA_RST_DONE, x)\n+\n+#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE   BIT(1)\n+#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)\n+#define SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_STAT_LANE_RST_DONE, x)\n+\n+#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS         GENMASK(31, 16)\n+#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)\n+#define SD_LANE_25G_SD_LANE_STAT_DBG_OBS_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_SD_LANE_STAT_DBG_OBS, x)\n+\n+/* SPARX5 ONLY */\n+/* SD25G_CFG_TARGET:SD_PWR_CFG:QUIET_MODE_6G */\n+#define SD_LANE_25G_QUIET_MODE_6G(t)                                           \\\n+\t__REG(TARGET_SD_LANE_25G, t, 8, 28, 0, 1, 8, 4, 0, 1, 4)\n+\n+#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE     GENMASK(24, 0)\n+#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_SET(x)\\\n+\tFIELD_PREP(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)\n+#define SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE_GET(x)\\\n+\tFIELD_GET(SD_LANE_25G_QUIET_MODE_6G_QUIET_MODE, x)\n+\n+#endif /* _SPARX5_MAIN_REGS_H_ */\ndiff --git a/drivers/net/mscc_eswitch/sparx5_switch.c b/drivers/net/mscc_eswitch/sparx5_switch.c\nnew file mode 100644\nindex 00000000000..4e36c983d35\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_switch.c\n@@ -0,0 +1,1181 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (c) 2019 Microsemi Corporation\n+ */\n+\n+#include <config.h>\n+#include <dm.h>\n+#include <dm/devres.h>\n+#include <dm/of_access.h>\n+#include <dm/of_addr.h>\n+#include <fdt_support.h>\n+#include <linux/io.h>\n+#include <linux/ioport.h>\n+#include <miiphy.h>\n+#include <net.h>\n+#include <wait_bit.h>\n+#include <command.h>\n+\n+#include \"sparx5_switch.h\"\n+\n+#include \"sparx5_regs.h\"\n+#include \"sparx5_reg_offset.h\"\n+\n+#include <dt-bindings/mscc/sparx5_data.h>\n+\n+static struct sparx5_private *dev_priv;\n+\n+#define MAC_VID\t\t\t1 /* Also = FID 1 */\n+#define ETH_ALEN\t\t6\n+\n+#define PGID_L2_UC(priv)\t\t(priv->data->num_ports + 0)\n+#define PGID_L2_MC(priv)\t\t(priv->data->num_ports + 1)\n+#define PGID_BROADCAST(priv)\t\t(priv->data->num_ports + 2)\n+#define PGID_HOST(priv)\t\t\t(priv->data->num_ports + 3)\n+\n+#define CONFIG_IFH_FMT_NONE\t0\n+\n+#define DSM_CAL_MAX_DEVS_PER_TAXI\t10\n+#define DSM_CAL_TAXIS\t\t\t5\n+#define DSM_CAL_LEN\t\t\t64\n+\n+#define SPX5_RGMII_TX_CLK_125MHZ\t1   /* 1000Mbps */\n+#define SPX5_RGMII_TX_CLK_25MHZ\t\t2   /* 100Mbps */\n+#define SPX5_RGMII_TX_CLK_2M5MHZ\t3   /* 10Mbps */\n+\n+static const char * const sparx5_reg_names[] = {\n+\t\"ana_ac\", \"ana_cl\", \"ana_l2\", \"ana_l3\",\n+\t\"asm\", \"lrn\", \"qfwd\", \"qs\",\n+\t\"qsys\", \"rew\", \"vop\", \"dsm\", \"eacl\",\n+\t\"vcap_super\", \"hsch\", \"port_conf\", \"xqs\", \"hsio\", \"gcb\", \"cpu\", \"ptp\",\n+\t\"port0\", \"port1\", \"port2\", \"port3\", \"port4\", \"port5\", \"port6\",\n+\t\"port7\", \"port8\", \"port9\", \"port10\", \"port11\", \"port12\", \"port13\",\n+\t\"port14\", \"port15\", \"port16\", \"port17\", \"port18\", \"port19\", \"port20\",\n+\t\"port21\", \"port22\", \"port23\", \"port24\", \"port25\", \"port26\", \"port27\",\n+\t\"port28\", \"port29\", \"port30\", \"port31\", \"port32\", \"port33\", \"port34\",\n+\t\"port35\", \"port36\", \"port37\", \"port38\", \"port39\", \"port40\", \"port41\",\n+\t\"port42\", \"port43\", \"port44\", \"port45\", \"port46\", \"port47\", \"port48\",\n+\t\"port49\", \"port50\", \"port51\", \"port52\", \"port53\", \"port54\", \"port55\",\n+\t\"port56\", \"port57\", \"port58\", \"port59\", \"port60\", \"port61\", \"port62\",\n+\t\"port63\", \"port64\",\n+};\n+\n+static const char * const lan969x_reg_names[] = {\n+\t\"ana_ac\", \"ana_cl\", \"ana_l2\", \"ana_l3\",\n+\t\"asm\", \"lrn\", \"qfwd\", \"qs\",\n+\t\"qsys\", \"rew\", \"vop\", \"dsm\", \"eacl\",\n+\t\"vcap_super\", \"hsch\", \"port_conf\", \"xqs\", \"hsio\", \"gcb\", \"cpu\", \"ptp\",\n+\t\"port0\", \"port1\", \"port2\", \"port3\", \"port4\", \"port5\", \"port6\",\n+\t\"port7\", \"port8\", \"port9\", \"port10\", \"port11\", \"port12\", \"port13\",\n+\t\"port14\", \"port15\", \"port16\", \"port17\", \"port18\", \"port19\", \"port20\",\n+\t\"port21\", \"port22\", \"port23\", \"port24\", \"port25\", \"port26\", \"port27\",\n+\t\"port28\", \"port29\",\n+};\n+\n+enum sparx5_ctrl_regs {\n+\tTARGET_ANA_AC,\n+\tTARGET_ANA_CL,\n+\tTARGET_ANA_L2,\n+\tTARGET_ANA_L3,\n+\tTARGET_ASM,\n+\tTARGET_LRN,\n+\tTARGET_QFWD,\n+\tTARGET_QS,\n+\tTARGET_QSYS,\n+\tTARGET_REW,\n+\tTARGET_VOP,\n+\tTARGET_DSM,\n+\tTARGET_EACL,\n+\tTARGET_VCAP_SUPER,\n+\tTARGET_HSCH,\n+\tTARGET_PORT_CONF,\n+\tTARGET_XQS,\n+\tTARGET_HSIO,\n+\tTARGET_GCB,\n+\tTARGET_CPU,\n+\tTARGET_PTP,\n+\t__REG_MAX,\n+\t/* This is used for all the ports even if it a 2.5G or RGMII */\n+\tTARGET_DEV2G5 = __REG_MAX,\n+};\n+\n+static const unsigned long sparx5_regs_qs[] = {\n+\t[MSCC_QS_XTR_RD] = 0x8,\n+\t[MSCC_QS_XTR_FLUSH] = 0x18,\n+\t[MSCC_QS_XTR_DATA_PRESENT] = 0x1c,\n+\t[MSCC_QS_INJ_WR] = 0x2c,\n+\t[MSCC_QS_INJ_CTRL] = 0x34,\n+};\n+\n+enum {\n+\tSERDES_ARG_MAC_TYPE,\n+\tSERDES_ARG_SERDES,\n+\tSERDES_ARG_SER_IDX,\n+\tSERDES_ARG_MAX,\n+};\n+\n+static struct mscc_match_data mscc_sparx5_data = {\n+\t.reg_names = sparx5_reg_names,\n+\t.regs = {\n+\t\t.reggrp_addr = sparx5_reggrp_addr,\n+\t\t.reggrp_cnt = sparx5_reggrp_cnt,\n+\t\t.reggrp_size = sparx5_reggrp_sz,\n+\t\t.reg_addr = sparx5_reg_addr,\n+\t\t.reg_cnt = sparx5_reg_cnt,\n+\t\t.regfield_addr = sparx5_regfield_addr,\n+\t},\n+\t.num_regs = 86,\n+\t.num_ports = 65,\n+\t.num_bus = 4,\n+\t.cpu_port = 65,\n+\t.npi_port = 64,\n+\t.ifh_len = 9,\n+\t.num_cal_auto = 7,\n+\t.target = SPARX5_TARGET,\n+};\n+\n+static struct mscc_match_data mscc_lan969x_data = {\n+\t.reg_names = lan969x_reg_names,\n+\t.regs = {\n+\t\t.reggrp_addr = lan969x_reggrp_addr,\n+\t\t.reggrp_cnt = lan969x_reggrp_cnt,\n+\t\t.reggrp_size = lan969x_reggrp_sz,\n+\t\t.reg_addr = lan969x_reg_addr,\n+\t\t.reg_cnt = lan969x_reg_cnt,\n+\t\t.regfield_addr = lan969x_regfield_addr,\n+\t},\n+\t.num_regs = 51,\n+\t.num_ports = 30,\n+\t.num_bus = 2,\n+\t.cpu_port = 30,\n+\t.npi_port = 24,\n+\t.ifh_len = 9,\n+\t.num_cal_auto = 4,\n+\t.target = LAN969X_TARGET,\n+};\n+\n+/* Keep the id, tinst and tcnt just to be able to use the same macros\n+ * as in the linux kernel\n+ */\n+static u32 spx5_rd(struct sparx5_private *priv,\n+\t\t   int id, int tinst, int tcnt,\n+\t\t   u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,\n+\t\t   u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)\n+{\n+\treturn readl(priv->regs[id + tinst] +\n+\t\t     gbase + ((ginst) * gwidth) +\n+\t\t     raddr + ((rinst) * rwidth));\n+}\n+\n+static void spx5_wr(u32 val, struct sparx5_private *priv,\n+\t\t    int id, int tinst, int tcnt,\n+\t\t    u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,\n+\t\t    u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)\n+{\n+\twritel(val,\n+\t       priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth));\n+}\n+\n+static void spx5_rmw(u32 val, u32 mask, struct sparx5_private *priv,\n+\t\t     int id, int tinst, int tcnt,\n+\t\t     u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,\n+\t\t     u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)\n+{\n+\tu32 nval;\n+\n+\tnval = readl(priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth));\n+\tnval = (nval & ~mask) | (val & mask);\n+\twritel(nval, priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth));\n+}\n+\n+static void __iomem *spx5_offset(struct sparx5_private *priv,\n+\t\t\t\t u32 id, u32 tinst, u32 tcnt,\n+\t\t\t\t u32 gbase, u32 ginst, u32 gcnt, u32 gwidth,\n+\t\t\t\t u32 raddr, u32 rinst, u32 rcnt, u32 rwidth)\n+{\n+\treturn priv->regs[id + tinst] + gbase + ((ginst) * gwidth) + raddr + ((rinst) * rwidth);\n+}\n+\n+static int ram_init(void __iomem *addr)\n+{\n+\twritel(BIT(1), addr);\n+\n+\tif (wait_for_bit_le32(addr, BIT(1), false, 2000, false)) {\n+\t\tprintf(\"Timeout in memory reset, addr: %p = 0x%08x\\n\", addr, readl(addr));\n+\t\treturn 1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int sparx5_switch_init(struct sparx5_private *priv)\n+{\n+\t/* Initialize memories */\n+\tram_init(spx5_offset(priv, QSYS_RAM_INIT));\n+\tram_init(spx5_offset(priv, ASM_RAM_INIT));\n+\tram_init(spx5_offset(priv, ANA_AC_RAM_INIT));\n+\tram_init(spx5_offset(priv, REW_RAM_INIT));\n+\tram_init(spx5_offset(priv, DSM_RAM_INIT));\n+\tram_init(spx5_offset(priv, EACL_RAM_INIT));\n+\tram_init(spx5_offset(priv, VCAP_SUPER_RAM_INIT));\n+\tram_init(spx5_offset(priv, VOP_RAM_INIT));\n+\n+\t/* Reset counters */\n+\tspx5_wr(0x1, priv, ANA_AC_STAT_RESET);\n+\tspx5_wr(0x1, priv, ASM_STAT_CFG);\n+\n+\treturn 0;\n+}\n+\n+static void sparx5_taxi2ports(u32 taxi, u32 *port_ptr) {\n+\tu32 taxi_ports[DSM_CAL_TAXIS][DSM_CAL_MAX_DEVS_PER_TAXI] = {\n+\t\t{0,4,1,2,3,5,6,7,28,29},\n+\t\t{8,12,9,13,10,11,14,15,99,99},\n+\t\t{16,20,17,21,18,19,22,23,99,99},\n+\t\t{24,25,99,99,99,99,99,99,99,99},\n+\t\t{26,27,99,99,99,99,99,99,99,99}};\n+\n+\tmemcpy(port_ptr, &taxi_ports[taxi],\n+\t       sizeof(u32) * DSM_CAL_MAX_DEVS_PER_TAXI);\n+}\n+\n+static int sparx5_dsm_calc_calendar(u32 *speeds, u32 ports, u32 freq_mhz,\n+\t\t\t\t    u32 *cal, u32 *cal_len) {\n+\tint bw = freq_mhz * 128 / 1.05;\n+\tint grps = 3;\n+\tint grp[ports];\n+\tint cnt[30];\n+\tint grpspd = 10000;\n+\tint bwavail[3], s_values[] = {5000, 2500, 1000};\n+\tint i, j, p, sp, win, grplen, lcs, s, found;\n+\n+\tif (bw < 30000) {\n+\t\tfor (i = 0; i < ports && speeds[i] != 10000; i++);\n+\t\tif (i == ports)\n+\t\t    grpspd = 5000;\n+\t\telse\n+\t\t    grps = 2;\n+\t}\n+\n+\tlcs = grpspd;\n+\tfor (i = 0; i < 3; i++) {\n+\t\ts = s_values[i];\n+\t\tfound = 0;\n+\t\tfor (j = 0; j < ports; j++) {\n+\t\t\tif (speeds[j] == s) {\n+\t\t\t\tfound = 1;\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\n+\t\tif (found) {\n+\t\t\tif (lcs == 2500) {\n+\t\t\t\tlcs = 500;\n+\t\t\t} else {\n+\t\t\t\tlcs = s;\n+\t\t\t}\n+\t\t}\n+\t}\n+\tgrplen = grpspd / lcs;\n+\n+\tfor (i = 0; i < grps; bwavail[i++] = grpspd);\n+\n+\tfor (i = 0; i < ports; i++) {\n+\t\tif (!speeds[i]) {\n+\t\t\tcontinue;\n+\t\t}\n+\t\tfor (j = 0; j < grps && bwavail[j] < speeds[i]; j++);\n+\t\tif (j == grps) {\n+\t\t\tprintf(\"Could not generate calendar at taxibw %d\\n\", bw);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tgrp[i] = j;\n+\t\tbwavail[j] -= speeds[i];\n+\t}\n+\n+\tmemset(cnt, 0, sizeof(cnt));\n+\tfor (i = 0; i < grplen; i++) {\n+\t\tfor (j = 0; j < grps; j++) {\n+\t\t\tsp = 1;\n+\t\t\twin = ports;\n+\t\t\tfor (p = 0; p < ports; p++) {\n+\t\t\t\tif (grp[p] != j) {\n+\t\t\t\t\tcontinue;\n+\t\t\t\t}\n+\t\t\t\tcnt[p] -= (cnt[p] > 0);\n+\t\t\t\tif (speeds[p] > sp && !cnt[p]) {\n+\t\t\t\t\twin = p;\n+\t\t\t\t\tsp = speeds[p];\n+\t\t\t\t}\n+\t\t\t}\n+\t\t\tif (win == ports) {\n+\t\t\t\twin = 10;\n+\t\t\t}\n+\n+\t\t\tcnt[win] = grpspd/sp;\n+\t\t\tcal[i * grps + j] = win;\n+\t\t}\n+\t}\n+\n+\t*cal_len = (cal[0] >= ports) ? 1 : (grps * grplen);\n+\treturn 0;\n+}\n+\n+static void sparx5_dsm_set_calendar(struct sparx5_private *priv,\n+\t\t\t\t    u32 taxi, u32 *calendar, u32 len)\n+{\n+\tu32 active_calendar;\n+\tu32 val;\n+\tu32 i;\n+\n+\tval = spx5_rd(priv, DSM_TAXI_CAL_CFG(taxi));\n+\tactive_calendar = DSM_TAXI_CAL_CFG_CAL_SEL_STAT_GET(val);\n+\n+\tspx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_SEL_SET(!active_calendar),\n+\t\t DSM_TAXI_CAL_CFG_CAL_PGM_SEL,\n+\t\t priv, DSM_TAXI_CAL_CFG(taxi));\n+\n+\tspx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(1),\n+\t\t DSM_TAXI_CAL_CFG_CAL_PGM_ENA,\n+\t\t priv, DSM_TAXI_CAL_CFG(taxi));\n+\n+\tfor (i = 0; i < len; i++) {\n+\t\tspx5_rmw(DSM_TAXI_CAL_CFG_CAL_IDX_SET(i),\n+\t\t\t DSM_TAXI_CAL_CFG_CAL_IDX,\n+\t\t\t priv, DSM_TAXI_CAL_CFG(taxi));\n+\n+\t\tspx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_VAL_SET(calendar[i]),\n+\t\t\t DSM_TAXI_CAL_CFG_CAL_PGM_VAL,\n+\t\t\t priv, DSM_TAXI_CAL_CFG(taxi));\n+\t}\n+\n+\tspx5_rmw(DSM_TAXI_CAL_CFG_CAL_PGM_ENA_SET(0),\n+\t\t DSM_TAXI_CAL_CFG_CAL_PGM_ENA,\n+\t\t priv, DSM_TAXI_CAL_CFG(taxi));\n+\n+\tval = spx5_rd(priv, DSM_TAXI_CAL_CFG(taxi));\n+\tval = DSM_TAXI_CAL_CFG_CAL_CUR_LEN_GET(val);\n+\tif (val != len - 1) {\n+\t\tprintf(\"Calendar length is not correct (%d) %d\\n\", val, len);\n+\t}\n+\n+\tspx5_rmw(DSM_TAXI_CAL_CFG_CAL_SWITCH_SET(1),\n+\t\t DSM_TAXI_CAL_CFG_CAL_SWITCH,\n+\t\t priv, DSM_TAXI_CAL_CFG(taxi));\n+}\n+\n+static void sparx5_lan969x_cal_cfg(struct sparx5_private *priv)\n+{\n+\tu32 taxi_speeds[DSM_CAL_MAX_DEVS_PER_TAXI] = {};\n+\tu32 taxi_ports[DSM_CAL_MAX_DEVS_PER_TAXI] = {0};\n+\tu32 calendar[DSM_CAL_LEN], taxi;\n+\tu32 freq_mhz = 328;\n+\tu32 *dev_speeds;\n+\tu32 cal_len, p;\n+\n+\tdev_speeds = devm_kzalloc(priv->dev,\n+\t\t\t\t  priv->data->num_ports * sizeof(u32),\n+\t\t\t\t  GFP_KERNEL);\n+\tif (!dev_speeds)\n+\t\treturn;\n+\n+\tfor (p = 0; p < priv->data->num_ports; p++) {\n+\t\tdev_speeds[p] = 1000;\n+\t}\n+\n+\tfor (taxi = 0; taxi < DSM_CAL_TAXIS; taxi++) {\n+\t\tsparx5_taxi2ports(taxi, taxi_ports);\n+\t\tfor (p = 0; p < DSM_CAL_MAX_DEVS_PER_TAXI; p++) {\n+\t\t\tif (taxi_ports[p] < priv->data->num_ports) {\n+\t\t\t\ttaxi_speeds[p] = dev_speeds[taxi_ports[p]];\n+\t\t\t} else {\n+\t\t\t\tbreak;\n+\t\t\t}\n+\t\t}\n+\t\tsparx5_dsm_calc_calendar(taxi_speeds, p, freq_mhz,\n+\t\t\t\t\t calendar, &cal_len);\n+\t\tsparx5_dsm_set_calendar(priv, taxi, calendar, cal_len);\n+\t}\n+\n+\tdevm_kfree(priv->dev, dev_speeds);\n+}\n+\n+static void sparx5_switch_config(struct sparx5_private *priv)\n+{\n+\tint i;\n+\n+\t/* Halt the calendar while changing it */\n+\tspx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(10),\n+\t\t QSYS_CAL_CTRL_CAL_MODE,\n+\t\t priv, QSYS_CAL_CTRL);\n+\n+\tfor (i = 0; i < priv->data->num_cal_auto; i++)\n+\t\t/* All ports to '001' - 1Gb/s */\n+\t\tspx5_wr(0x09249249, priv, QSYS_CAL_AUTO(i));\n+\n+\t/* Enable Auto mode */\n+\tspx5_rmw(QSYS_CAL_CTRL_CAL_MODE_SET(8),\n+\t\t QSYS_CAL_CTRL_CAL_MODE,\n+\t\t priv, QSYS_CAL_CTRL);\n+\n+\tif (priv->data->target == LAN969X_TARGET) {\n+\t\tsparx5_lan969x_cal_cfg(priv);\n+\n+\t\tspx5_wr(0x18624dd2, priv, PTP_CLK_PER_CFG(0, 1));\n+\t\tspx5_rmw(PTP_PTP_DOM_CFG_PTP_ENA_SET(1),\n+\t\t\t PTP_PTP_DOM_CFG_PTP_ENA,\n+\t\t\t priv, PTP_PTP_DOM_CFG);\n+\t}\n+\n+\t/* Configure NPI port */\n+\tswitch (priv->ports[priv->data->npi_port].mac_type) {\n+\tcase IF_SGMII:\n+\t\tif (priv->data->target == SPARX5_TARGET) {\n+\t\t\tspx5_rmw(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(1),\n+\t\t\t\t PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE,\n+\t\t\t\t priv, PORT_CONF_DEV5G_MODES);\n+\t\t}\n+\t\tbreak;\n+\tcase IF_RGMII:\n+\tcase IF_SGMII_CISCO:\n+\t\t/* Nothing to do here */\n+\t\tbreak;\n+\tdefault:\n+\t\tspx5_rmw(PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE_SET(0),\n+\t\t\t PORT_CONF_DEV5G_MODES_DEV5G_D64_MODE,\n+\t\t\t priv, PORT_CONF_DEV5G_MODES);\n+\t\tbreak;\n+\t}\n+\n+\t/* Enable all 5G, 10G and 25G ports to behave as 2.5G port */\n+\tif (priv->data->target == SPARX5_TARGET) {\n+\t\tspx5_wr(0x1fff, priv, PORT_CONF_DEV5G_MODES);\n+\t\tspx5_wr(0xfff, priv, PORT_CONF_DEV10G_MODES);\n+\t\tspx5_wr(0xff, priv, PORT_CONF_DEV25G_MODES);\n+\t}\n+\n+\t/* As we currently support speeds of 1G or less, then it is OK to set\n+\t * all the ports that we support lower speeds than 2.5G.\n+\t */\n+\tif (priv->data->target == LAN969X_TARGET) {\n+\t\tspx5_wr(0xf117001, priv, PORT_CONF_DEV10G_MODES);\n+\t\tspx5_wr(0x222200, priv, PORT_CONF_DEV5G_MODES);\n+\t}\n+\n+\tfor (i = 0; i < priv->data->num_ports; i++) {\n+\t\tstruct sparx5_phy_port *p = &priv->ports[i];\n+\n+\t\tif (p->active) {\n+\t\t\t/* Enable 10G shadow interfaces */\n+\t\t\tspx5_rmw(DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA_SET(1),\n+\t\t\t\t DSM_DEV_TX_STOP_WM_CFG_DEV10G_SHADOW_ENA,\n+\t\t\t\t priv, DSM_DEV_TX_STOP_WM_CFG(i));\n+\t\t}\n+\n+\t\tif (p->mac_type == IF_QSGMII) {\n+\t\t\t/* Enable the QSGMII interface */\n+\t\t\tu32 val = spx5_rd(priv, PORT_CONF_QSGMII_ENA);\n+\t\t\tval |= BIT(i / 4);\n+\t\t\tspx5_wr(val, priv, PORT_CONF_QSGMII_ENA);\n+\n+\t\t\t/* Must take the PCS out of reset for all 4 QSGMII instances,\n+\t\t\t */\n+\t\t\tfor (u32 cnt = 0; cnt < 4; ++cnt) {\n+\t\t\t\tu32 base = (i / 4) * 4;\n+\t\t\t\tspx5_rmw(DEV2G5_DEV_RST_CTRL_PCS_TX_RST_SET(0),\n+\t\t\t\t\t DEV2G5_DEV_RST_CTRL_PCS_TX_RST,\n+\t\t\t\t\t priv, DEV2G5_DEV_RST_CTRL(base + cnt));\n+\t\t\t}\n+\n+\t\t\tif (priv->data->target == SPARX5_TARGET) {\n+\t\t\t\tif (i < 12)\n+\t\t\t\t\tspx5_rmw(BIT(i), BIT(i),\n+\t\t\t\t\t\t priv, PORT_CONF_DEV5G_MODES);\n+\t\t\t\tif (i >= 12 && i <= 15)\n+\t\t\t\t\tspx5_rmw(BIT(i - 12), BIT(i - 12),\n+\t\t\t\t\t\t priv, PORT_CONF_DEV10G_MODES);\n+\n+\t\t\t\tif ((i / 4 % 2) == 0)\n+\t\t\t\t\t/* Affects d0-d3,d8-d11..d40-d43 */\n+\t\t\t\t\tspx5_wr(0x332, priv, PORT_CONF_USGMII_CFG(i / 8));\n+\t\t\t}\n+\t\t}\n+\t}\n+\n+\t/* BCAST/CPU pgid */\n+\tif (priv->data->target == SPARX5_TARGET) {\n+\t\tspx5_wr(0xffffffff, priv, ANA_AC_PGID_CFG(PGID_BROADCAST(priv)));\n+\t\tspx5_wr(0xffffffff, priv, ANA_AC_PGID_CFG1(PGID_BROADCAST(priv)));\n+\t\tspx5_wr(0x00000001, priv, ANA_AC_PGID_CFG2(PGID_BROADCAST(priv)));\n+\t\tspx5_wr(0x00000000, priv, ANA_AC_PGID_CFG(PGID_HOST(priv)));\n+\t\tspx5_wr(0x00000000, priv, ANA_AC_PGID_CFG1(PGID_HOST(priv)));\n+\t\tspx5_wr(0x00000000, priv, ANA_AC_PGID_CFG2(PGID_HOST(priv)));\n+\t}\n+\n+\tif (priv->data->target == LAN969X_TARGET) {\n+\t\tspx5_wr(0xffffffff, priv, ANA_AC_PGID_CFG(PGID_BROADCAST(priv)));\n+\t\tspx5_wr(0x00000000, priv, ANA_AC_PGID_CFG(PGID_HOST(priv)));\n+\t}\n+\n+\t/* Disable port-to-port by switching\n+\t * Put front ports in \"port isolation modes\" - i.e. they can't send\n+\t * to other ports - via the PGID sorce masks.\n+\t */\n+\tfor (i = 0; i < priv->data->num_ports; i++) {\n+\t\tif (priv->data->target == SPARX5_TARGET) {\n+\t\t\tspx5_wr(0, priv, ANA_AC_SRC_CFG(i));\n+\t\t\tspx5_wr(0, priv, ANA_AC_SRC_CFG1(i));\n+\t\t\tspx5_wr(0, priv, ANA_AC_SRC_CFG2(i));\n+\t\t}\n+\n+\t\tif (priv->data->target == LAN969X_TARGET) {\n+\t\t\tspx5_wr(0, priv, ANA_AC_SRC_CFG(i));\n+\t\t}\n+\t}\n+\n+\tspx5_wr(priv->data->cpu_port << 5, priv, XQS_STAT_CFG);\n+\n+\t/* VLAN aware CPU port */\n+\tspx5_wr(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(1) |\n+\t\tANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(1) |\n+\t\tANA_CL_VLAN_CTRL_PORT_VID_SET(MAC_VID),\n+\t\tpriv, ANA_CL_VLAN_CTRL(priv->data->cpu_port));\n+\n+\t/* Map PVID = FID, DISABLE LEARNING  */\n+\tspx5_wr(ANA_L3_VLAN_CFG_VLAN_FID_SET(MAC_VID) |\n+\t\tANA_L3_VLAN_CFG_VLAN_LRN_DIS_SET(1),\n+\t\tpriv, ANA_L3_VLAN_CFG(MAC_VID));\n+\n+\t/* Enable VLANs */\n+\tspx5_wr(ANA_L3_VLAN_CTRL_VLAN_ENA_SET(1),\n+\t\tpriv, ANA_L3_VLAN_CTRL);\n+\n+\t/* Enable switch-core and queue system */\n+\tspx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1),\n+\t\tpriv, HSCH_RESET_CFG);\n+\n+\t/* Flush queues */\n+\tmscc_flush(priv->regs[TARGET_QS], sparx5_regs_qs);\n+}\n+\n+static void sparx5_cpu_capture_setup(struct sparx5_private *priv)\n+{\n+\t/* ASM CPU port: No preamble/IFH, enable padding */\n+\tspx5_wr(ASM_PORT_CFG_NO_PREAMBLE_ENA_SET(1) |\n+\t\tASM_PORT_CFG_PAD_ENA_SET(1) |\n+\t\tASM_PORT_CFG_INJ_FORMAT_CFG_SET(CONFIG_IFH_FMT_NONE),\n+\t\tpriv, ASM_PORT_CFG(priv->data->cpu_port));\n+\n+\t/* Set Manual injection via DEVCPU_QS registers for CPU queue 0 */\n+\tspx5_wr(QS_INJ_GRP_CFG_MODE_SET(1) |\n+\t\tQS_INJ_GRP_CFG_BYTE_SWAP_SET(1),\n+\t\tpriv, QS_INJ_GRP_CFG(0));\n+\n+\t/* Set Manual extraction via DEVCPU_QS registers for CPU queue 0 */\n+\tspx5_wr(QS_XTR_GRP_CFG_MODE_SET(1) |\n+\t\tQS_XTR_GRP_CFG_STATUS_WORD_POS_SET(1) |\n+\t\tQS_XTR_GRP_CFG_BYTE_SWAP_SET(1),\n+\t\tpriv, QS_XTR_GRP_CFG(0));\n+\n+\t/* Enable CPU port for any frame transfer */\n+\tspx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),\n+\t\t QFWD_SWITCH_PORT_MODE_PORT_ENA,\n+\t\t priv, QFWD_SWITCH_PORT_MODE(priv->data->cpu_port));\n+\n+\t/* Recalc injected frame FCS */\n+\tspx5_rmw(ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA_SET(1),\n+\t\t ANA_CL_FILTER_CTRL_FORCE_FCS_UPDATE_ENA,\n+\t\t priv, ANA_CL_FILTER_CTRL(priv->data->cpu_port));\n+\n+\t/* Send a copy to CPU when found as forwarding entry */\n+\tspx5_rmw(ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA_SET(1),\n+\t\t ANA_L2_FWD_CFG_CPU_DMAC_COPY_ENA,\n+\t\t priv, ANA_L2_FWD_CFG);\n+}\n+\n+static void sparx5_port_sgmii_init(struct sparx5_private *priv, int port)\n+{\n+\tsparx5_serdes_port_init(priv->ports[port].serdes_phy,\n+\t\t\t\tpriv->ports[port].mac_type);\n+\n+\t/* Enable PCS */\n+\tspx5_wr(DEV2G5_PCS1G_CFG_PCS_ENA_SET(1),\n+\t\tpriv, DEV2G5_PCS1G_CFG(port));\n+\n+\t/* Disable Signal Detect */\n+\tspx5_wr(0, priv, DEV2G5_USXGMII_PCS_SD_CFG(port));\n+\n+\t/* Enable MAC RX and TX */\n+\tspx5_wr(DEV2G5_MAC_ENA_CFG_TX_ENA_SET(1) |\n+\t\tDEV2G5_MAC_ENA_CFG_RX_ENA_SET(1),\n+\t\tpriv, DEV2G5_MAC_ENA_CFG(port));\n+\n+\t/* Enable sgmii_mode_ena */\n+\tspx5_wr(DEV2G5_PCS1G_MODE_CFG_SGMII_MODE_ENA_SET(1),\n+\t\tpriv, DEV2G5_PCS1G_MODE_CFG(port));\n+\n+\tif (priv->ports[port].mac_type == IF_SGMII ||\n+\t    priv->ports[port].mac_type == IF_QSGMII) {\n+\t\t/*\n+\t\t * Clear sw_resolve_ena(bit 0) and set adv_ability to\n+\t\t * something meaningful just in case\n+\t\t */\n+\t\tspx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(0x20),\n+\t\t\tpriv, DEV2G5_PCS1G_ANEG_CFG(port));\n+\t} else {\n+\t\t/* IF_SGMII_CISCO */\n+\t\tspx5_wr(DEV2G5_PCS1G_ANEG_CFG_ADV_ABILITY_SET(0x0001) |\n+\t\t\tDEV2G5_PCS1G_ANEG_CFG_SW_RESOLVE_ENA_SET(1) |\n+\t\t\tDEV2G5_PCS1G_ANEG_CFG_ANEG_ENA_SET(1) |\n+\t\t\tDEV2G5_PCS1G_ANEG_CFG_ANEG_RESTART_ONE_SHOT_SET(1),\n+\t\t\tpriv, DEV2G5_PCS1G_ANEG_CFG(port));\n+\t}\n+\n+\t/* Set MAC IFG Gaps */\n+\tspx5_wr(DEV2G5_MAC_IFG_CFG_TX_IFG_SET(4) |\n+\t\tDEV2G5_MAC_IFG_CFG_RX_IFG1_SET(5) |\n+\t\tDEV2G5_MAC_IFG_CFG_RX_IFG2_SET(1),\n+\t\tpriv, DEV2G5_MAC_IFG_CFG(port));\n+\n+\t/* Set link speed and release all resets but USX */\n+\tspx5_wr(DEV2G5_DEV_RST_CTRL_SPEED_SEL_SET(2) |\n+\t\tDEV2G5_DEV_RST_CTRL_USX_PCS_TX_RST_SET(1) |\n+\t\tDEV2G5_DEV_RST_CTRL_USX_PCS_RX_RST_SET(1),\n+\t\tpriv, DEV2G5_DEV_RST_CTRL(port));\n+}\n+\n+static void sparx5_port_rgmii_init(struct sparx5_private *priv, int port)\n+{\n+\t/* This function is called only on lan969x, and the RGMII ports are only\n+\t * on the D28 and D29. They map in the DEVRGMII\n+\t */\n+\tint rgmii_index = port - 28;\n+\tstruct phy_device *phydev = priv->ports[port].phy;\n+\tint spd = phydev->speed;\n+\tint tx_clk_freq;\n+\tu32 clk_spd;\n+\n+\tclk_spd = spd == SPEED_10 ? 0 : spd == SPEED_100 ? 1 : 2;\n+\ttx_clk_freq = (spd == SPEED_10\t? SPX5_RGMII_TX_CLK_2M5MHZ :\n+\t\t       spd == SPEED_100\t? SPX5_RGMII_TX_CLK_25MHZ :\n+\t\t\t\t\t  SPX5_RGMII_TX_CLK_125MHZ);\n+\n+\t/* Enable the RGMII0 on the GPIOs */\n+\tspx5_wr(HSIO_WRAP_XMII_CFG_GPIO_XMII_CFG_SET(1),\n+\t\tpriv, HSIO_WRAP_XMII_CFG(!rgmii_index));\n+\n+\t/* Take the RGMII out of reset and set speed to 1G */\n+\tspx5_wr(HSIO_WRAP_RGMII_CFG_TX_CLK_CFG_SET(tx_clk_freq),\n+\t\tpriv, HSIO_WRAP_RGMII_CFG(rgmii_index));\n+\n+\t/* Enable the RGMII delays on the MAC both on the RX and TX.\n+\t * The signal is shft by 90 degress\n+\t */\n+\tspx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(0) |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(3),\n+\t\t HSIO_WRAP_DLL_CFG_DLL_ENA |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_RST |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,\n+\t\t priv, HSIO_WRAP_DLL_CFG(rgmii_index, 0));\n+\n+\tspx5_rmw(HSIO_WRAP_DLL_CFG_DLL_RST_SET(0) |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_ENA_SET(1) |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_ENA_SET(1) |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_SEL_SET(3),\n+\t\t HSIO_WRAP_DLL_CFG_DLL_ENA |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_RST |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_ENA |\n+\t\t HSIO_WRAP_DLL_CFG_DLL_CLK_SEL,\n+\t\t priv, HSIO_WRAP_DLL_CFG(rgmii_index, 1));\n+\n+\t/* Configure the port now */\n+\tspx5_wr(DEVRGMII_MAC_ENA_CFG_RX_ENA_SET(1) |\n+\t\tDEVRGMII_MAC_ENA_CFG_TX_ENA_SET(1),\n+\t\tpriv, DEVRGMII_MAC_ENA_CFG(port));\n+\n+\tspx5_wr(DEVRGMII_MAC_IFG_CFG_TX_IFG_SET(4) |\n+\t\tDEVRGMII_MAC_IFG_CFG_RX_IFG1_SET(5) |\n+\t\tDEVRGMII_MAC_IFG_CFG_RX_IFG2_SET(1),\n+\t\tpriv, DEVRGMII_MAC_IFG_CFG(port));\n+\n+\tspx5_wr(DEVRGMII_DEV_RST_CTRL_SPEED_SEL_SET(clk_spd),\n+\t\tpriv, DEVRGMII_DEV_RST_CTRL(port));\n+}\n+\n+static void sparx5_port_init(struct sparx5_private *priv, int port)\n+{\n+\tswitch (priv->ports[port].mac_type) {\n+\tcase IF_SGMII:\n+\tcase IF_QSGMII:\n+\tcase IF_SGMII_CISCO:\n+\t\tsparx5_port_sgmii_init(priv, port);\n+\t\tbreak;\n+\tcase IF_RGMII:\n+\t\tsparx5_port_rgmii_init(priv, port);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"Unknown interface type: %d\\n\",\n+\t\t       priv->ports[port].mac_type);\n+\t\treturn;\n+\t}\n+\n+\t/* Make VLAN aware for CPU traffic */\n+\tspx5_wr(ANA_CL_VLAN_CTRL_VLAN_AWARE_ENA_SET(1) |\n+\t\tANA_CL_VLAN_CTRL_VLAN_POP_CNT_SET(1) |\n+\t\tANA_CL_VLAN_CTRL_PORT_VID_SET(MAC_VID),\n+\t\tpriv, ANA_CL_VLAN_CTRL(port));\n+\n+\t/* Enable CPU port for any frame transfer */\n+\tspx5_rmw(QFWD_SWITCH_PORT_MODE_PORT_ENA_SET(1),\n+\t\t QFWD_SWITCH_PORT_MODE_PORT_ENA,\n+\t\t priv, QFWD_SWITCH_PORT_MODE(port));\n+}\n+\n+static inline int sparx5_vlant_wait_for_completion(struct sparx5_private *priv)\n+{\n+\tif (wait_for_bit_le32(spx5_offset(priv, LRN_COMMON_ACCESS_CTRL),\n+\t\t\t      LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT,\n+\t\t\t      false, 2000, false))\n+\t\treturn -ETIMEDOUT;\n+\n+\treturn 0;\n+}\n+\n+static void mac_table_write_entry(struct sparx5_private *priv,\n+\t\t\t\t  const unsigned char *mac,\n+\t\t\t\t  u16 vid)\n+{\n+\tu32 macl = 0, mach = 0;\n+\n+\t/*\n+\t * Set the MAC address to handle and the vlan associated in a format\n+\t * understood by the hardware.\n+\t */\n+\tmach |= vid << 16;\n+\tmach |= ((u32)mac[0]) << 8;\n+\tmach |= ((u32)mac[1]) << 0;\n+\tmacl |= ((u32)mac[2]) << 24;\n+\tmacl |= ((u32)mac[3]) << 16;\n+\tmacl |= ((u32)mac[4]) << 8;\n+\tmacl |= ((u32)mac[5]) << 0;\n+\n+\tspx5_wr(mach, priv, LRN_MAC_ACCESS_CFG_0);\n+\tspx5_wr(macl, priv, LRN_MAC_ACCESS_CFG_1);\n+}\n+\n+static int sparx5_mac_table_add(struct sparx5_private *priv,\n+\t\t\t\t const unsigned char *mac, int pgid)\n+{\n+\tmac_table_write_entry(priv, mac, MAC_VID);\n+\n+\tspx5_wr(LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_SET(pgid - priv->data->num_ports) |\n+\t\tLRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR_TYPE_SET(0x3) |\n+\t\tLRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_COPY_SET(1) |\n+\t\tLRN_MAC_ACCESS_CFG_2_MAC_ENTRY_CPU_QU_SET(0) |\n+\t\tLRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD_SET(1) |\n+\t\tLRN_MAC_ACCESS_CFG_2_MAC_ENTRY_LOCKED_SET(1),\n+\t\tpriv, LRN_MAC_ACCESS_CFG_2);\n+\n+\tspx5_wr(LRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(1),\n+\t\tpriv, LRN_COMMON_ACCESS_CTRL);\n+\n+\treturn sparx5_vlant_wait_for_completion(priv);\n+}\n+\n+static int sparx5_mac_table_getnext(struct sparx5_private *priv,\n+\t\t\t\t     unsigned char *mac,\n+\t\t\t\t     int *addr,\n+\t\t\t\t     u32 *pvid,\n+\t\t\t\t     u32 *cfg0p,\n+\t\t\t\t     u32 *cfg1p,\n+\t\t\t\t     u32 *cfg2p)\n+{\n+\tint ret;\n+\n+\tmac_table_write_entry(priv, mac, *pvid);\n+\n+\tspx5_wr(LRN_SCAN_NEXT_CFG_SCAN_NEXT_UNTIL_FOUND_ENA_SET(1) |\n+\t\tLRN_SCAN_NEXT_CFG_SCAN_NEXT_IGNORE_LOCKED_ENA_SET(1),\n+\t\tpriv, LRN_SCAN_NEXT_CFG);\n+\n+\tspx5_wr(LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_CMD_SET(6) |\n+\t\tLRN_COMMON_ACCESS_CTRL_MAC_TABLE_ACCESS_SHOT_SET(1),\n+\t\tpriv, LRN_COMMON_ACCESS_CTRL);\n+\n+\tret = sparx5_vlant_wait_for_completion(priv);\n+\n+\tif (ret == 0) {\n+\t\tu32 cfg0, cfg1, cfg2;\n+\t\tcfg2 = spx5_rd(priv, LRN_MAC_ACCESS_CFG_2);\n+\t\tif (cfg2 & LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_VLD) {\n+\t\t\tcfg0 = spx5_rd(priv, LRN_MAC_ACCESS_CFG_0);\n+\t\t\tcfg1 = spx5_rd(priv, LRN_MAC_ACCESS_CFG_1);\n+\t\t\tmac[0] = ((cfg0 >> 8)  & 0xff);\n+\t\t\tmac[1] = ((cfg0 >> 0)  & 0xff);\n+\t\t\tmac[2] = ((cfg1 >> 24) & 0xff);\n+\t\t\tmac[3] = ((cfg1 >> 16) & 0xff);\n+\t\t\tmac[4] = ((cfg1 >> 8)  & 0xff);\n+\t\t\tmac[5] = ((cfg1 >> 0)  & 0xff);\n+\t\t\t*addr = LRN_MAC_ACCESS_CFG_2_MAC_ENTRY_ADDR & cfg2;\n+\t\t\t*pvid = cfg0 >> 16;\n+\t\t\t*cfg0p = cfg0;\n+\t\t\t*cfg1p = cfg1;\n+\t\t\t*cfg2p = cfg2;\n+\t\t} else {\n+\t\t\tret = 1;\n+\t\t}\n+\t}\n+\n+\treturn ret;\n+}\n+\n+static int sparx5_initialize(struct sparx5_private *priv)\n+{\n+\tint ret, i;\n+\n+\t/* Initialize switch memories, enable core */\n+\tret = sparx5_switch_init(priv);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tboard_init();\n+\tsparx5_switch_config(priv);\n+\n+\tfor (i = 0; i < priv->data->num_ports; i++)\n+\t\tif (priv->ports[i].active)\n+\t\t\tsparx5_port_init(priv, i);\n+\n+\tsparx5_cpu_capture_setup(priv);\n+\n+\treturn 0;\n+}\n+\n+static bool sparx5_port_has_link(struct sparx5_private *priv, int port)\n+{\n+\tu32 mask, val;\n+\n+\tif (priv->ports[port].mac_type == IF_RGMII)\n+\t\treturn priv->ports[port].phy->link;\n+\n+\tif (priv->ports[port].mdio_dev) {\n+\t\tval = spx5_rd(priv, DEV2G5_PCS1G_LINK_STATUS(port));\n+\t\tmask = DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS;\n+\t} else {\n+\t\tval = spx5_rd(priv, DEV2G5_PCS1G_ANEG_STATUS(port));\n+\t\tmask = DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE;\n+\t}\n+\n+\treturn !!(val & mask);\n+}\n+\n+static int sparx5_start(struct udevice *dev)\n+{\n+\tconst u8 mac[ETH_ALEN] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff};\n+\tstruct sparx5_private *priv = dev_get_priv(dev);\n+\tstruct eth_pdata *pdata = dev_get_plat(dev);\n+\tint i, ret, phy_ok = 0, ret_err = 0;\n+\n+\t/* Set MAC address tables entries for CPU redirection */\n+\tret = sparx5_mac_table_add(priv, mac, PGID_BROADCAST(priv));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tret = sparx5_mac_table_add(priv, pdata->enetaddr, PGID_HOST(priv));\n+\tif (ret)\n+\t\treturn ret;\n+\n+\tfor (i = 0; i < priv->data->num_ports; i++) {\n+\t\tstruct phy_device *phy = priv->ports[i].phy;\n+\n+\t\tif (!priv->ports[i].active || !phy)\n+\t\t\tcontinue;\n+\n+\t\t/* Start up the PHY */\n+\t\tphy_config(phy);\n+\t\tret = phy_startup(phy);\n+\t\tif (ret) {\n+\t\t\tprintf(\"Could not initialize PHY %s (port %d)\\n\",\n+\t\t\t       phy->dev->name, i);\n+\t\t\tret_err = ret;\n+\t\t\tcontinue; /* try all phys */\n+\t\t} else {\n+\t\t\tphy_ok = 1;\n+\t\t\tif (i == priv->data->npi_port)\n+\t\t\t\tprintf(\"NPI Port: \");\n+\t\t\telse\n+\t\t\t\tprintf(\"Port %3d: \", i);\n+\n+\t\t\tprintf(\"%s (internal)\\n\", sparx5_port_has_link(priv, i) ? \"Up\" : \"Down\");\n+\t\t}\n+\n+\t\tsparx5_port_init(priv, i);\n+\t}\n+\n+\treturn phy_ok ? 0 : ret_err;\n+}\n+\n+static void sparx5_stop(struct udevice *dev)\n+{\n+\tstruct sparx5_private *priv = dev_get_priv(dev);\n+\tint i;\n+\n+\tfor (i = 0; i < priv->data->num_ports; i++) {\n+\t\tstruct phy_device *phy = priv->ports[i].phy;\n+\n+\t\tif (phy)\n+\t\t\tphy_shutdown(phy);\n+\t}\n+}\n+\n+static int sparx5_send(struct udevice *dev, void *packet, int length)\n+{\n+\tstruct sparx5_private *priv = dev_get_priv(dev);\n+\n+\treturn mscc_send(priv->regs[TARGET_QS], sparx5_regs_qs,\n+\t\t\t NULL, 0, packet, length);\n+}\n+\n+static int sparx5_recv(struct udevice *dev, int flags, uchar **packetp)\n+{\n+\tstruct sparx5_private *priv = dev_get_priv(dev);\n+\tu32 *rxbuf = (u32 *)net_rx_packets[0];\n+\tint byte_cnt = 0;\n+\n+\tbyte_cnt = mscc_recv(priv->regs[TARGET_QS], sparx5_regs_qs, rxbuf,\n+\t\t\t     priv->data->ifh_len, false);\n+\n+\t*packetp = net_rx_packets[0];\n+\n+\tif (byte_cnt > 0) {\n+\t\tif (byte_cnt >= ETH_FCS_LEN)\n+\t\t\tbyte_cnt -= ETH_FCS_LEN;\n+\t\telse\n+\t\t\tbyte_cnt = 0; /* Runt? */\n+\t}\n+\n+\treturn byte_cnt;\n+}\n+\n+static int sparx5_probe(struct udevice *dev)\n+{\n+\tu32 serdes_args[SERDES_ARG_MAX];\n+\tstruct sparx5_private *priv;\n+\tint i;\n+\tint ret;\n+\tofnode eth_node, node, mdio_node;\n+\tu32 phy_addr;\n+\tstruct udevice *mdio_dev;\n+\tofnode phy_node;\n+\tphy_interface_t mode;\n+\n+\tpriv = dev_get_priv(dev);\n+\tif (!priv)\n+\t\treturn -EINVAL;\n+\n+\tpriv->dev = dev;\n+\n+\tpriv->data = (struct mscc_match_data*)dev_get_driver_data(dev);\n+\tif (!priv->data)\n+\t\treturn -EINVAL;\n+\n+\t/* Allocate the resources dynamically */\n+\tpriv->regs = devm_kzalloc(dev,\n+\t\t\t\t  priv->data->num_regs * sizeof(void __iomem *),\n+\t\t\t\t  GFP_KERNEL);\n+\tif (!priv->regs)\n+\t\treturn -ENOMEM;\n+\n+\tpriv->ports = devm_kzalloc(dev,\n+\t\t\t\t   priv->data->num_ports * sizeof(struct sparx5_phy_port),\n+\t\t\t\t   GFP_KERNEL);\n+\tif (!priv->ports)\n+\t\treturn -ENOMEM;\n+\n+\t/* Get registers and map them to the private structure */\n+\tfor (i = 0; i < priv->data->num_regs; i++) {\n+\t\tpriv->regs[i] = dev_remap_addr_name(dev,\n+\t\t\t\t\t\t    priv->data->reg_names[i]);\n+\t\tif (!priv->regs[i]) {\n+\t\t\tprintf(\"Error can't get regs base addresses for %s\\n\",\n+\t\t\t       priv->data->reg_names[i]);\n+\t\t\treturn -ENOMEM;\n+\t\t}\n+\t}\n+\n+\tpriv->serdes = sparx5_serdes_probe(dev);\n+\tif (IS_ERR(priv->serdes))\n+\t\treturn PTR_ERR(priv->serdes);\n+\n+\t/* iterate all the ports and find out on which bus they are */\n+\ti = 0;\n+\teth_node = dev_read_first_subnode(dev);\n+\tfor (node = ofnode_first_subnode(eth_node);\n+\t     ofnode_valid(node);\n+\t     node = ofnode_next_subnode(node)) {\n+\t\tret = ofnode_read_u32(node, \"reg\", &i);\n+\t\tif (ret)\n+\t\t\treturn ret;\n+\n+\t\tmdio_dev = NULL;\n+\t\tphy_node = ofnode_get_phy_node(node);\n+\n+\t\t/* Do we have a PHY to worry about? */\n+\t\tif (ofnode_valid(phy_node)) {\n+\t\t\t/* Get phy address on mdio bus */\n+\t\t\tret = ofnode_read_u32(phy_node, \"reg\", &phy_addr);\n+\t\t\tif (ret)\n+\t\t\t\treturn ret;\n+\n+\t\t\t/* Get mdio node */\n+\t\t\tmdio_node = ofnode_get_parent(phy_node);\n+\n+\t\t\tret = uclass_get_device_by_ofnode(UCLASS_MDIO, mdio_node, &mdio_dev);\n+\t\t\tif (ret) {\n+\t\t\t\tprintf(\"%s: Cannot get MDIO device: %d\\n\", __FUNCTION__, ret);\n+\t\t\t\treturn ret;\n+\t\t\t}\n+\n+\t\t\tmode = ofnode_read_phy_mode(node);\n+\t\t} else {\n+\t\t\tmdio_dev = NULL;\n+\t\t\tphy_addr = -1;\n+\t\t\tmode = PHY_INTERFACE_MODE_NA;\n+\t\t}\n+\n+\t\tpriv->ports[i].active = true;\n+\t\tpriv->ports[i].phy_addr = phy_addr;\n+\t\tpriv->ports[i].mdio_dev = mdio_dev;\n+\t\tpriv->ports[i].mode = mode;\n+\n+\t\t/* Get serdes info */\n+\t\tret = ofnode_read_u32_array(node, \"phys\", serdes_args, SERDES_ARG_MAX);\n+\t\tif (ret) {\n+\t\t\tret = ofnode_read_u32_array(node, \"phys\", serdes_args, 1);\n+\t\t\tif (ret) {\n+\t\t\t\tprintf(\"%s: Port %d no 'phys' properties?\\n\",\n+\t\t\t\t       __func__, i);\n+\t\t\t\treturn -EINVAL;\n+\t\t\t} else {\n+\t\t\t\tpriv->ports[i].mac_type = serdes_args[SERDES_ARG_MAC_TYPE];\n+\t\t\t}\n+\t\t} else {\n+\t\t\tpriv->ports[i].mac_type = serdes_args[SERDES_ARG_MAC_TYPE];\n+\t\t\tpriv->ports[i].serdes_type = serdes_args[SERDES_ARG_SERDES];\n+\t\t\tpriv->ports[i].serdes_index = serdes_args[SERDES_ARG_SER_IDX];\n+\t\t\tpriv->ports[i].serdes_phy = sparx5_serdes_phy_get(priv->serdes,\n+\t\t\t\t\t\t\t\t\t  priv->ports[i].serdes_type,\n+\t\t\t\t\t\t\t\t\t  priv->ports[i].serdes_index);\n+\t\t}\n+\n+\t\tdebug(\"%s: Add port %d bus %s addr %u serdes %s serdes# %d\\n\",\n+\t\t      __func__, i, priv->ports[i].mdio_dev ? priv->ports[i].mdio_dev->name : \"(none)\", phy_addr,\n+\t\t      priv->ports[i].serdes_type == FA_SERDES_TYPE_6G ? \"6g\" : \"10g\",\n+\t\t      priv->ports[i].serdes_index);\n+\t}\n+\n+\tfor (i = 0; i < priv->data->num_ports; i++) {\n+\t\tstruct phy_device *phy;\n+\n+\t\tif (!priv->ports[i].mdio_dev)\n+\t\t\tcontinue;\n+\n+\t\tphy = dm_mdio_phy_connect(priv->ports[i].mdio_dev,\n+\t\t\t\t  priv->ports[i].phy_addr, dev,\n+\t\t\t\t  priv->ports[i].mode);\n+\t\tif (phy)\n+\t\t\tpriv->ports[i].phy = phy;\n+\t}\n+\n+\tsparx5_initialize(priv);\n+\n+\tdev_priv = priv;\n+\n+\treturn 0;\n+}\n+\n+static int sparx5_remove(struct udevice *dev)\n+{\n+\tstruct sparx5_private *priv = dev_get_priv(dev);\n+\n+\t/* Make sure the core is PROTECTED from reset */\n+\tspx5_rmw(CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE,\n+\t\t CPU_RESET_PROT_STAT_SYS_RST_PROT_VCORE,\n+\t\t priv, CPU_RESET_PROT_STAT);\n+\n+\t/* Reset switch core */\n+\tspx5_wr(GCB_SOFT_RST_SOFT_CHIP_RST_SET(1),\n+\t\tpriv, GCB_SOFT_RST);\n+\n+\tdev_priv = NULL;\n+\n+\treturn 0;\n+}\n+\n+static const struct eth_ops sparx5_ops = {\n+\t.start        = sparx5_start,\n+\t.stop         = sparx5_stop,\n+\t.send         = sparx5_send,\n+\t.recv         = sparx5_recv,\n+};\n+\n+static const struct udevice_id mscc_sparx5_ids[] = {\n+\t{.compatible = \"mscc,vsc7558-switch\", .data = (ulong)&mscc_sparx5_data },\n+\t{.compatible = \"microchip,lan9691-switch\", .data = (ulong)&mscc_lan969x_data },\n+\t{ /* Sentinel */ }\n+};\n+\n+U_BOOT_DRIVER(sparx5) = {\n+\t.name\t\t\t\t= \"sparx5-switch\",\n+\t.id\t\t\t\t= UCLASS_ETH,\n+\t.of_match\t\t\t= mscc_sparx5_ids,\n+\t.probe\t\t\t\t= sparx5_probe,\n+\t.remove\t\t\t\t= sparx5_remove,\n+\t.ops\t\t\t\t= &sparx5_ops,\n+\t.priv_auto\t\t\t= sizeof(struct sparx5_private),\n+\t.plat_auto\t\t\t= sizeof(struct eth_pdata),\n+};\n+\n+static int do_switch(struct cmd_tbl *cmdtp, int flag, int argc,\n+\t\t     char * const argv[])\n+{\n+\tstruct sparx5_private *priv = dev_priv;\n+\tu8 mac[ETH_ALEN];\n+\tint i, addr, cnt = 0;\n+\tu32 cfg0, cfg1, cfg2;\n+\n+\tif (priv) {\n+\t\tmemset(mac, 0, sizeof(mac));\n+\t\tu32 vid = 0;\n+\t\twhile (sparx5_mac_table_getnext(priv, mac, &addr, &vid, &cfg0, &cfg1, &cfg2) == 0) {\n+\t\t\tprintf(\"%4d: %02x:%02x:%02x:%02x:%02x:%02x %d:%d 0x%08x 0x%08x 0x%08x\\n\",\n+\t\t\t       cnt++,\n+\t\t\t       mac[0], mac[1], mac[2],\n+\t\t\t       mac[3], mac[4], mac[5], vid, addr, cfg0, cfg1, cfg2);\n+\t\t}\n+\t\tfor (i = 0; i < priv->data->num_ports; i++)\n+\t\t\tif (priv->ports[i].active) {\n+\t\t\t\tu32 mask, val;\n+\t\t\t\tif (priv->ports[i].mdio_dev) {\n+\t\t\t\t\tval = spx5_rd(priv, DEV2G5_PCS1G_LINK_STATUS(i));\n+\t\t\t\t\tmask = DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS;\n+\t\t\t\t} else {\n+\t\t\t\t\tval = spx5_rd(priv, DEV2G5_PCS1G_ANEG_STATUS(i));\n+\t\t\t\t\tmask = DEV2G5_PCS1G_ANEG_STATUS_ANEG_COMPLETE;\n+\t\t\t\t}\n+\t\t\t\tprintf(\"%2d: Link %s (0x%08x)\\n\", i,\n+\t\t\t\t       val & mask ? \"Up\" : \"--\",\n+\t\t\t\t       val);\n+\t\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_CMD(\n+\tswitch,\t3,\t1,\tdo_switch,\n+\t\"display switch status\",\n+\t\"\"\n+);\ndiff --git a/drivers/net/mscc_eswitch/sparx5_switch.h b/drivers/net/mscc_eswitch/sparx5_switch.h\nnew file mode 100644\nindex 00000000000..ff6a729e484\n--- /dev/null\n+++ b/drivers/net/mscc_eswitch/sparx5_switch.h\n@@ -0,0 +1,69 @@\n+/* SPDX-License-Identifier: GPL-2.0+\n+ * Microchip Sparx5 SerDes driver\n+ *\n+ * Copyright (c) 2020 Microchip Technology Inc.\n+ */\n+\n+#ifndef _SPARX5_SWITCH_H_\n+#define _SPARX5_SWITCH_H_\n+\n+#include \"sparx5_serdes.h\"\n+\n+#include \"mscc_xfer.h\"\n+#include \"mscc_miim.h\"\n+\n+enum {\n+\tSPARX5_TARGET,\n+\tLAN969X_TARGET,\n+};\n+\n+struct sparx5_regs {\n+\tconst unsigned int *reggrp_addr;\n+\tconst unsigned int *reggrp_cnt;\n+\tconst unsigned int *reggrp_size;\n+\tconst unsigned int *reg_addr;\n+\tconst unsigned int *reg_cnt;\n+\tconst unsigned int *regfield_addr;\n+};\n+\n+struct mscc_match_data {\n+\tconst char * const *reg_names;\n+\tstruct sparx5_regs regs;\n+\tu8 num_regs;\n+\tu8 num_ports;\n+\tu8 num_bus;\n+\tu8 cpu_port;\n+\tu8 npi_port;\n+\tu8 ifh_len;\n+\tu8 num_cal_auto;\n+\tu8 target;\n+};\n+\n+struct sparx5_phy_port {\n+\tbool active;\n+\tstruct udevice *mdio_dev;\n+\tu8 phy_addr;\n+\tstruct phy_device *phy;\n+\tphy_interface_t mode;\n+\tu32 mac_type;\n+\tu32 serdes_type;\n+\tu32 serdes_index;\n+\n+\t/* This is the serdes that correspond to the port */\n+\tstruct sparx5_serdes_phy *serdes_phy;\n+};\n+\n+struct sparx5_private {\n+\tstruct mscc_match_data *data;\n+\n+\tvoid __iomem **regs;\n+\tstruct sparx5_phy_port *ports;\n+\tstruct udevice *dev;\n+\n+\t/* This is a container for the entire serdes, which correspond to\n+\t * sparx5_serdes_private\n+\t */\n+\tvoid *serdes;\n+};\n+\n+#endif /* _SPARX5_SWITCH_H_ */\ndiff --git a/include/dt-bindings/mscc/sparx5_data.h b/include/dt-bindings/mscc/sparx5_data.h\nnew file mode 100644\nindex 00000000000..aba0d3c4493\n--- /dev/null\n+++ b/include/dt-bindings/mscc/sparx5_data.h\n@@ -0,0 +1,19 @@\n+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */\n+/*\n+ * Copyright (c) 2019 Microsemi Corporation\n+ */\n+\n+#ifndef _SPARX5_DATA_H_\n+#define _SPARX5_DATA_H_\n+\n+#define FA_SERDES_TYPE_6G  6\n+#define FA_SERDES_TYPE_10G 10\n+#define FA_SERDES_TYPE_25G 25\n+\n+/* similar with phy_interface_t */\n+#define\tIF_SGMII\t1\n+#define\tIF_SGMII_CISCO\t2\n+#define\tIF_QSGMII\t3\n+#define\tIF_RGMII\t4\n+\n+#endif\n",
    "prefixes": [
        "12/14"
    ]
}