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GET /api/patches/2216422/?format=api
{ "id": 2216422, "url": "http://patchwork.ozlabs.org/api/patches/2216422/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/patch/20260326115517.2156-3-dave.patel@riscstar.com/", "project": { "id": 67, "url": "http://patchwork.ozlabs.org/api/projects/67/?format=api", "name": "OpenSBI development", "link_name": "opensbi", "list_id": "opensbi.lists.infradead.org", "list_email": "opensbi@lists.infradead.org", "web_url": "https://github.com/riscv/opensbi", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "https://github.com/riscv/opensbi/commit/{}" }, "msgid": "<20260326115517.2156-3-dave.patel@riscstar.com>", "list_archive_url": null, "date": "2026-03-26T11:55:16", "name": "[v2,2/3] lib: sbi: Add floating-point context save/restore support.", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0166eddbf3e79c5a0ff373396782a1aa5eebd8d4", "submitter": { "id": 92617, "url": "http://patchwork.ozlabs.org/api/people/92617/?format=api", "name": "Dave Patel", "email": "dave.patel@riscstar.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/opensbi/patch/20260326115517.2156-3-dave.patel@riscstar.com/mbox/", "series": [ { "id": 497579, "url": "http://patchwork.ozlabs.org/api/series/497579/?format=api", "web_url": "http://patchwork.ozlabs.org/project/opensbi/list/?series=497579", "date": "2026-03-26T11:55:16", "name": "[v2,1/3] lib: sbi: Add RISC-V vector context save/restore support (eager switching)", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497579/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216422/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216422/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n secure) header.d=lists.infradead.org header.i=@lists.infradead.org\n header.a=rsa-sha256 header.s=bombadil.20210309 header.b=rPr0h2Xd;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=riscstar-com.20230601.gappssmtp.com\n header.i=@riscstar-com.20230601.gappssmtp.com header.a=rsa-sha256\n header.s=20230601 header.b=OX1YL6WR;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=none (no SPF record) smtp.mailfrom=lists.infradead.org\n (client-ip=2607:7c80:54:3::133; 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The original\n message has been attached to this so you can view it or label\n similar future email. If you have any questions, see\n the administrator of that system for details.\n Content preview: From: Dave Patel <dave.patel@riscstar.com> Add support for\n saving and restoring RISC-V floating-point (F/D) extension state in\n OpenSBI.\n This introduces a floating-point context structure and helper routines to\n perform full context save and res [...]\n Content analysis details: (-1.9 points, 5.0 required)\n pts rule name description\n ---- ----------------------\n --------------------------------------------------\n -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at https://www.dnswl.org/, no\n trust\n [2a00:1450:4864:20:0:0:0:435 listed in]\n [list.dnswl.org]\n 0.0 SPF_HELO_NONE SPF: HELO does not publish an SPF Record\n -0.0 SPF_PASS SPF: sender matches SPF record\n -0.1 DKIM_VALID Message has at least one valid DKIM or DK\n signature\n 0.1 DKIM_SIGNED Message has a DKIM or DK signature,\n not necessarily valid\n -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n [score: 0.0000]", "X-BeenThere": "opensbi@lists.infradead.org", "X-Mailman-Version": "2.1.34", "Precedence": "list", "List-Id": "<opensbi.lists.infradead.org>", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/opensbi/>", "List-Post": "<mailto:opensbi@lists.infradead.org>", "List-Help": "<mailto:opensbi-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/opensbi>,\n <mailto:opensbi-request@lists.infradead.org?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Sender": "\"opensbi\" <opensbi-bounces@lists.infradead.org>", "Errors-To": "opensbi-bounces+incoming=patchwork.ozlabs.org@lists.infradead.org" }, "content": "From: Dave Patel <dave.patel@riscstar.com>\n\nAdd support for saving and restoring RISC-V floating-point (F/D) extension\nstate in OpenSBI. This introduces a floating-point context structure and\nhelper routines to perform full context save and restore.\n\nThe floating-point context includes storage for all 32 FPi registers (f0–f31)\nalong with the fcsr control and status register. The register state is saved\nand restored using double-precision load/store instructions (fsd/fld), and\nsingle-precision load/store instructions (fsw/flw) on an RV64 system with\nF and D-extension support.\n\nThe implementation follows an eager context switching model where the entire\nFP state is saved and restored on every context switch. This avoids the need\nfor trap-based lazy management and keeps the design simple and deterministic.\n\nSigned-off-by: Dave Patel <dave.patel@riscstar.com>\"\nSigned-off-by: Dave Patel <dave.patel@riscstar.com>\n---\n include/sbi/sbi_fp.h | 37 +++++++++\n lib/sbi/objects.mk | 3 +\n lib/sbi/sbi_fp.c | 188 +++++++++++++++++++++++++++++++++++++++++++\n 3 files changed, 228 insertions(+)\n create mode 100644 include/sbi/sbi_fp.h\n create mode 100644 lib/sbi/sbi_fp.c\n\n--\n2.43.0", "diff": "diff --git a/include/sbi/sbi_fp.h b/include/sbi/sbi_fp.h\nnew file mode 100644\nindex 00000000..5794b66f\n--- /dev/null\n+++ b/include/sbi/sbi_fp.h\n@@ -0,0 +1,37 @@\n+/* SPDX-License-Identifier: GPL-2.0\n+ *\n+ * Copyright (c) 2026 RISCstar Solutions.\n+ *\n+ * Authors:\n+ * Dave Patel <dave.patel@riscstar.com>\n+ */\n+#ifndef __SBI_FP_H__\n+#define __SBI_FP_H__\n+\n+#include <sbi/riscv_encoding.h>\n+\n+#if defined(__riscv_f) || defined(__riscv_d)\n+\n+#include <stdint.h>\n+\n+struct sbi_fp_context {\n+#if __riscv_xlen == 64 && defined(__riscv_d)\n+ uint64_t f[32];\n+#else\n+ uint32_t f[32];\n+#endif\n+ uint32_t fcsr;\n+} __attribute__((aligned(16)));\n+\n+void sbi_fp_save(struct sbi_fp_context *dst);\n+void sbi_fp_restore(const struct sbi_fp_context *src);\n+\n+#else /* No FP (e.g., Zve32x) */\n+\n+struct sbi_fp_context { };\n+\n+static inline void sbi_fp_save(struct sbi_fp_context *dst) { }\n+static inline void sbi_fp_restore(const struct sbi_fp_context *src) { }\n+\n+#endif //defined(__riscv_f) || defined(__riscv_d)\n+#endif //__SBI_VECTOR_H__\ndiff --git a/lib/sbi/objects.mk b/lib/sbi/objects.mk\nindex 9fd378d0..b99712d3 100644\n--- a/lib/sbi/objects.mk\n+++ b/lib/sbi/objects.mk\n@@ -113,3 +113,6 @@ $(info RESULT = $(findstring v,$(RISCV_EXTS)))\n ifneq ($(findstring v,$(RISCV_EXTS)),)\n libsbi-objs-y += sbi_vector.o\n endif\n+ifneq ($(findstring f,$(RISCV_EXTS))$(findstring d,$(RISCV_EXTS))$(findstring g,$(RISCV_EXTS)),)\n+libsbi-objs-y += sbi_fp.o\n+endif\ndiff --git a/lib/sbi/sbi_fp.c b/lib/sbi/sbi_fp.c\nnew file mode 100644\nindex 00000000..b6651577\n--- /dev/null\n+++ b/lib/sbi/sbi_fp.c\n@@ -0,0 +1,188 @@\n+/* SPDX-License-Identifier: GPL-2.0\n+ *\n+ * Copyright (c) 2026 RISCstar Solutions.\n+ *\n+ * Authors:\n+ * Dave Patel <dave.patel@riscstar.com>\n+ */\n+\n+#include <sbi/riscv_asm.h>\n+#include <sbi/riscv_encoding.h>\n+#include <sbi/sbi_fp.h>\n+\n+#if defined(__riscv_f) || defined(__riscv_d)\n+\n+void sbi_fp_save(struct sbi_fp_context *dst)\n+{\n+\tif (!dst)\n+\t\treturn;\n+\n+#if __riscv_xlen == 64 && defined(__riscv_d)\n+\tasm volatile(\n+\t\t\"fsd f0, 0(%0)\\n\"\n+\t\t\"fsd f1, 8(%0)\\n\"\n+\t\t\"fsd f2, 16(%0)\\n\"\n+\t\t\"fsd f3, 24(%0)\\n\"\n+\t\t\"fsd f4, 32(%0)\\n\"\n+\t\t\"fsd f5, 40(%0)\\n\"\n+\t\t\"fsd f6, 48(%0)\\n\"\n+\t\t\"fsd f7, 56(%0)\\n\"\n+\t\t\"fsd f8, 64(%0)\\n\"\n+\t\t\"fsd f9, 72(%0)\\n\"\n+\t\t\"fsd f10, 80(%0)\\n\"\n+\t\t\"fsd f11, 88(%0)\\n\"\n+\t\t\"fsd f12, 96(%0)\\n\"\n+\t\t\"fsd f13, 104(%0)\\n\"\n+\t\t\"fsd f14, 112(%0)\\n\"\n+\t\t\"fsd f15, 120(%0)\\n\"\n+\t\t\"fsd f16, 128(%0)\\n\"\n+\t\t\"fsd f17, 136(%0)\\n\"\n+\t\t\"fsd f18, 144(%0)\\n\"\n+\t\t\"fsd f19, 152(%0)\\n\"\n+\t\t\"fsd f20, 160(%0)\\n\"\n+\t\t\"fsd f21, 168(%0)\\n\"\n+\t\t\"fsd f22, 176(%0)\\n\"\n+\t\t\"fsd f23, 184(%0)\\n\"\n+\t\t\"fsd f24, 192(%0)\\n\"\n+\t\t\"fsd f25, 200(%0)\\n\"\n+\t\t\"fsd f26, 208(%0)\\n\"\n+\t\t\"fsd f27, 216(%0)\\n\"\n+\t\t\"fsd f28, 224(%0)\\n\"\n+\t\t\"fsd f29, 232(%0)\\n\"\n+\t\t\"fsd f30, 240(%0)\\n\"\n+\t\t\"fsd f31, 248(%0)\\n\"\n+\t\t:\n+\t\t: \"r\"(dst->f)\n+\t\t: \"memory\"\n+\t);\n+#else /* RV32 or F-only */\n+ asm volatile(\n+ \"fsw f0, 0(%0)\\n\"\n+ \"fsw f1, 4(%0)\\n\"\n+ \"fsw f2, 8(%0)\\n\"\n+ \"fsw f3, 12(%0)\\n\"\n+ \"fsw f4, 16(%0)\\n\"\n+ \"fsw f5, 20(%0)\\n\"\n+ \"fsw f6, 24(%0)\\n\"\n+ \"fsw f7, 28(%0)\\n\"\n+ \"fsw f8, 32(%0)\\n\"\n+ \"fsw f9, 36(%0)\\n\"\n+ \"fsw f10, 40(%0)\\n\"\n+ \"fsw f11, 44(%0)\\n\"\n+ \"fsw f12, 48(%0)\\n\"\n+ \"fsw f13, 52(%0)\\n\"\n+ \"fsw f14, 56(%0)\\n\"\n+ \"fsw f15, 60(%0)\\n\"\n+ \"fsw f16, 64(%0)\\n\"\n+ \"fsw f17, 68(%0)\\n\"\n+ \"fsw f18, 72(%0)\\n\"\n+ \"fsw f19, 76(%0)\\n\"\n+ \"fsw f20, 80(%0)\\n\"\n+ \"fsw f21, 84(%0)\\n\"\n+ \"fsw f22, 88(%0)\\n\"\n+ \"fsw f23, 92(%0)\\n\"\n+ \"fsw f24, 96(%0)\\n\"\n+ \"fsw f25, 100(%0)\\n\"\n+ \"fsw f26, 104(%0)\\n\"\n+ \"fsw f27, 108(%0)\\n\"\n+ \"fsw f28, 112(%0)\\n\"\n+ \"fsw f29, 116(%0)\\n\"\n+ \"fsw f30, 120(%0)\\n\"\n+ \"fsw f31, 124(%0)\\n\"\n+ :\n+ : \"r\"(dst->f)\n+ : \"memory\"\n+ );\n+#endif //__riscv_d\n+\n+\tdst->fcsr = csr_read(CSR_FCSR);\n+}\n+\n+void sbi_fp_restore(const struct sbi_fp_context *src)\n+{\n+\tif (!src)\n+ return;\n+\n+#if __riscv_xlen == 64 && defined(__riscv_d)\n+\tasm volatile(\n+\t\t\"fld f0, 0(%0)\\n\"\n+\t\t\"fld f1, 8(%0)\\n\"\n+\t\t\"fld f2, 16(%0)\\n\"\n+\t\t\"fld f3, 24(%0)\\n\"\n+\t\t\"fld f4, 32(%0)\\n\"\n+\t\t\"fld f5, 40(%0)\\n\"\n+\t\t\"fld f6, 48(%0)\\n\"\n+\t\t\"fld f7, 56(%0)\\n\"\n+\t\t\"fld f8, 64(%0)\\n\"\n+\t\t\"fld f9, 72(%0)\\n\"\n+\t\t\"fld f10, 80(%0)\\n\"\n+ \"fld f11, 88(%0)\\n\"\n+\t\t\"fld f12, 96(%0)\\n\"\n+\t\t\"fld f13, 104(%0)\\n\"\n+\t\t\"fld f14, 112(%0)\\n\"\n+\t\t\"fld f15, 120(%0)\\n\"\n+\t\t\"fld f16, 128(%0)\\n\"\n+\t\t\"fld f17, 136(%0)\\n\"\n+\t\t\"fld f18, 144(%0)\\n\"\n+\t\t\"fld f19, 152(%0)\\n\"\n+\t\t\"fld f20, 160(%0)\\n\"\n+\t\t\"fld f21, 168(%0)\\n\"\n+\t\t\"fld f22, 176(%0)\\n\"\n+\t\t\"fld f23, 184(%0)\\n\"\n+\t\t\"fld f24, 192(%0)\\n\"\n+\t\t\"fld f25, 200(%0)\\n\"\n+\t\t\"fld f26, 208(%0)\\n\"\n+\t\t\"fld f27, 216(%0)\\n\"\n+\t\t\"fld f28, 224(%0)\\n\"\n+\t\t\"fld f29, 232(%0)\\n\"\n+\t\t\"fld f30, 240(%0)\\n\"\n+\t\t\"fld f31, 248(%0)\\n\"\n+\t\t:\n+\t\t: \"r\"(src->f)\n+\t\t: \"memory\"\n+\t);\n+#else /* RV32 or F-only */\n+\n+ asm volatile(\n+ \"flw f0, 0(%0)\\n\"\n+ \"flw f1, 4(%0)\\n\"\n+ \"flw f2, 8(%0)\\n\"\n+ \"flw f3, 12(%0)\\n\"\n+ \"flw f4, 16(%0)\\n\"\n+ \"flw f5, 20(%0)\\n\"\n+ \"flw f6, 24(%0)\\n\"\n+ \"flw f7, 28(%0)\\n\"\n+ \"flw f8, 32(%0)\\n\"\n+ \"flw f9, 36(%0)\\n\"\n+ \"flw f10, 40(%0)\\n\"\n+ \"flw f11, 44(%0)\\n\"\n+ \"flw f12, 48(%0)\\n\"\n+ \"flw f13, 52(%0)\\n\"\n+ \"flw f14, 56(%0)\\n\"\n+ \"flw f15, 60(%0)\\n\"\n+ \"flw f16, 64(%0)\\n\"\n+ \"flw f17, 68(%0)\\n\"\n+ \"flw f18, 72(%0)\\n\"\n+ \"flw f19, 76(%0)\\n\"\n+ \"flw f20, 80(%0)\\n\"\n+ \"flw f21, 84(%0)\\n\"\n+ \"flw f22, 88(%0)\\n\"\n+ \"flw f23, 92(%0)\\n\"\n+ \"flw f24, 96(%0)\\n\"\n+ \"flw f25, 100(%0)\\n\"\n+ \"flw f26, 104(%0)\\n\"\n+ \"flw f27, 108(%0)\\n\"\n+ \"flw f28, 112(%0)\\n\"\n+ \"flw f29, 116(%0)\\n\"\n+ \"flw f30, 120(%0)\\n\"\n+ \"flw f31, 124(%0)\\n\"\n+ :\n+ : \"r\"(src->f)\n+ : \"memory\"\n+ );\n+\n+#endif\n+\n+\tcsr_write(CSR_FCSR, src->fcsr);\n+}\n+#endif // FP present\n", "prefixes": [ "v2", "2/3" ] }