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GET /api/patches/2216410/?format=api
{ "id": 2216410, "url": "http://patchwork.ozlabs.org/api/patches/2216410/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-14-robert.marko@sartura.hr/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326112830.313874-14-robert.marko@sartura.hr>", "list_archive_url": null, "date": "2026-03-26T11:26:55", "name": "[14/14] arch: arm: add Microchip LAN969x support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d9dc8a081a055117d83fbca1ed16c083a9daea6f", "submitter": { "id": 78207, "url": "http://patchwork.ozlabs.org/api/people/78207/?format=api", "name": "Robert Marko", "email": "robert.marko@sartura.hr" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-14-robert.marko@sartura.hr/mbox/", "series": [ { "id": 497572, "url": "http://patchwork.ozlabs.org/api/series/497572/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497572", "date": "2026-03-26T11:26:42", "name": "[01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497572/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216410/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216410/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.a=rsa-sha256\n header.s=sartura header.b=XaRib0Eh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.b=\"XaRib0Eh\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=robert.marko@sartura.hr" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhM656mWZz1yGD\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 22:30:53 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id D1E4083EAC;\n\tThu, 26 Mar 2026 12:29:49 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 2370E840CB; Thu, 26 Mar 2026 12:29:49 +0100 (CET)", "from mail-dl1-x1236.google.com (mail-dl1-x1236.google.com\n [IPv6:2607:f8b0:4864:20::1236])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 3D3CB81E18\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 12:29:45 +0100 (CET)", "by mail-dl1-x1236.google.com with SMTP id\n a92af1059eb24-1271257ae53so924874c88.1\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 04:29:45 -0700 (PDT)", "from fedora (cpe-109-60-83-68.zg3.cable.xnet.hr. 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a92af1059eb24-12a96eeb11amr3723510c88.34.1774524581623;\n Thu, 26 Mar 2026 04:29:41 -0700 (PDT)", "From": "Robert Marko <robert.marko@sartura.hr>", "To": "u-boot@lists.denx.de, trini@konsulko.com, lukma@denx.de, hs@nabladev.com,\n peng.fan@nxp.com, jh80.chung@samsung.com, gregory.clement@bootlin.com,\n lars.povlsen@microchip.com, horatiu.vultur@microchip.com,\n jerome.forissier@arm.com, marex@denx.de, daniel.machon@microchip.com", "Cc": "luka.perkov@sartura.hr,\n\tRobert Marko <robert.marko@sartura.hr>", "Subject": "[PATCH 14/14] arch: arm: add Microchip LAN969x support", "Date": "Thu, 26 Mar 2026 12:26:55 +0100", "Message-ID": "<20260326112830.313874-14-robert.marko@sartura.hr>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260326112830.313874-1-robert.marko@sartura.hr>", "References": "<20260326112830.313874-1-robert.marko@sartura.hr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Microchip LAN9696x is a Cortex-A53 based switch SoC.\n\nSince Microchip also has LAN966x and SparX-5 families of switch SoC-s\nlets add a generic architecture so those could be added in future as\nwell under the same architecture.\n\nSupport is included for the SoC and the EV23X71A board.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n arch/arm/Kconfig | 10 +\n arch/arm/Makefile | 1 +\n arch/arm/dts/Makefile | 2 +\n arch/arm/dts/clk-lan9691.h | 24 +\n arch/arm/dts/lan9691.dtsi | 545 +++++++++++++\n arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi | 18 +\n arch/arm/dts/lan9696-ev23x71a.dts | 795 +++++++++++++++++++\n arch/arm/dts/lan969x-u-boot.dtsi | 72 ++\n arch/arm/mach-microchipsw/Kconfig | 31 +\n arch/arm/mach-microchipsw/Makefile | 3 +\n arch/arm/mach-microchipsw/include/mach/soc.h | 29 +\n arch/arm/mach-microchipsw/lan969x/Makefile | 3 +\n arch/arm/mach-microchipsw/lan969x/soc.c | 136 ++++\n board/microchip/lan969x/Makefile | 3 +\n board/microchip/lan969x/lan969x.c | 115 +++\n configs/microchip_ev23x71a_defconfig | 77 ++\n include/configs/lan969x.h | 36 +\n 17 files changed, 1900 insertions(+)\n create mode 100644 arch/arm/dts/clk-lan9691.h\n create mode 100644 arch/arm/dts/lan9691.dtsi\n create mode 100644 arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi\n create mode 100644 arch/arm/dts/lan9696-ev23x71a.dts\n create mode 100644 arch/arm/dts/lan969x-u-boot.dtsi\n create mode 100644 arch/arm/mach-microchipsw/Kconfig\n create mode 100644 arch/arm/mach-microchipsw/Makefile\n create mode 100644 arch/arm/mach-microchipsw/include/mach/soc.h\n create mode 100644 arch/arm/mach-microchipsw/lan969x/Makefile\n create mode 100644 arch/arm/mach-microchipsw/lan969x/soc.c\n create mode 100644 board/microchip/lan969x/Makefile\n create mode 100644 board/microchip/lan969x/lan969x.c\n create mode 100644 configs/microchip_ev23x71a_defconfig\n create mode 100644 include/configs/lan969x.h", "diff": "diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig\nindex cd6a454fd60..ebd9d96452f 100644\n--- a/arch/arm/Kconfig\n+++ b/arch/arm/Kconfig\n@@ -869,6 +869,14 @@ config ARCH_MEDIATEK\n \t Support for the MediaTek SoCs family developed by MediaTek Inc.\n \t Please refer to doc/README.mediatek for more information.\n \n+config ARCH_MICROCHIPSW\n+\tbool \"Microchip switch SoCs\"\n+\tselect DM\n+\tselect OF_CONTROL\n+\timply CMD_DM\n+\thelp\n+\t Support for Microchip switch focused SoC-s.\n+\n config ARCH_MMP\n \tbool \"Marvell MMP\"\n \tselect ARM64\n@@ -2400,6 +2408,8 @@ source \"arch/arm/mach-nexell/Kconfig\"\n \n source \"arch/arm/mach-npcm/Kconfig\"\n \n+source \"arch/arm/mach-microchipsw/Kconfig\"\n+\n source \"board/armltd/total_compute/Kconfig\"\n source \"board/armltd/corstone1000/Kconfig\"\n source \"board/bosch/shc/Kconfig\"\ndiff --git a/arch/arm/Makefile b/arch/arm/Makefile\nindex b36b0742580..2d5e4836b06 100644\n--- a/arch/arm/Makefile\n+++ b/arch/arm/Makefile\n@@ -70,6 +70,7 @@ machine-$(CONFIG_ARCH_KIRKWOOD)\t\t+= kirkwood\n machine-$(CONFIG_ARCH_LPC32XX)\t\t+= lpc32xx\n machine-$(CONFIG_ARCH_MEDIATEK)\t\t+= mediatek\n machine-$(CONFIG_ARCH_MESON)\t\t+= meson\n+machine-$(CONFIG_ARCH_MICROCHIPSW)\t+= microchipsw\n machine-$(CONFIG_ARCH_MMP)\t\t+= mmp\n machine-$(CONFIG_ARCH_MVEBU)\t\t+= mvebu\n machine-$(CONFIG_ARCH_NEXELL)\t\t+= nexell\ndiff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile\nindex 82ad3035308..ec6ba8c5f55 100644\n--- a/arch/arm/dts/Makefile\n+++ b/arch/arm/dts/Makefile\n@@ -1210,6 +1210,8 @@ dtb-$(CONFIG_TARGET_CORSTONE1000) += corstone1000-mps3.dtb \\\n \n dtb-$(CONFIG_TARGET_COREPRIMEVELTE) += pxa1908-samsung-coreprimevelte.dtb\n \n+dtb-$(CONFIG_ARCH_MICROCHIPSW) += lan9696-ev23x71a.dtb\n+\n include $(srctree)/scripts/Makefile.dts\n \n # Add any required device tree compiler flags here\ndiff --git a/arch/arm/dts/clk-lan9691.h b/arch/arm/dts/clk-lan9691.h\nnew file mode 100644\nindex 00000000000..0f2d7a0f881\n--- /dev/null\n+++ b/arch/arm/dts/clk-lan9691.h\n@@ -0,0 +1,24 @@\n+/* SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) */\n+\n+#ifndef _DTS_CLK_LAN9691_H\n+#define _DTS_CLK_LAN9691_H\n+\n+#define GCK_ID_QSPI0\t\t0\n+#define GCK_ID_QSPI2\t\t1\n+#define GCK_ID_SDMMC0\t\t2\n+#define GCK_ID_SDMMC1\t\t3\n+#define GCK_ID_MCAN0\t\t4\n+#define GCK_ID_MCAN1\t\t5\n+#define GCK_ID_FLEXCOM0\t\t6\n+#define GCK_ID_FLEXCOM1\t\t7\n+#define GCK_ID_FLEXCOM2\t\t8\n+#define GCK_ID_FLEXCOM3\t\t9\n+#define GCK_ID_TIMER\t\t10\n+#define GCK_ID_USB_REFCLK\t11\n+\n+/* Gate clocks */\n+#define GCK_GATE_USB_DRD\t12\n+#define GCK_GATE_MCRAMC\t\t13\n+#define GCK_GATE_HMATRIX\t14\n+\n+#endif\ndiff --git a/arch/arm/dts/lan9691.dtsi b/arch/arm/dts/lan9691.dtsi\nnew file mode 100644\nindex 00000000000..b79923fba00\n--- /dev/null\n+++ b/arch/arm/dts/lan9691.dtsi\n@@ -0,0 +1,545 @@\n+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n+/*\n+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.\n+ */\n+\n+#include <dt-bindings/dma/at91.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/mfd/at91-usart.h>\n+#include <dt-bindings/mfd/atmel-flexcom.h>\n+\n+#include \"clk-lan9691.h\"\n+\n+/ {\n+\t#address-cells = <1>;\n+\t#size-cells = <1>;\n+\n+\tmodel = \"Microchip LAN969x\";\n+\tcompatible = \"microchip,lan9691\";\n+\tinterrupt-parent = <&gic>;\n+\n+\tclocks {\n+\t\tfx100_clk: fx100-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <320000000>;\n+\t\t};\n+\n+\t\tcpu_clk: cpu-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <1000000000>;\n+\t\t};\n+\n+\t\tddr_clk: ddr-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <600000000>;\n+\t\t};\n+\n+\t\tfabric_clk: fabric-clk {\n+\t\t\tcompatible = \"fixed-clock\";\n+\t\t\t#clock-cells = <0>;\n+\t\t\tclock-frequency = <250000000>;\n+\t\t};\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0: cpu@0 {\n+\t\t\tcompatible = \"arm,cortex-a53\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x0 0x0>;\n+\t\t\tnext-level-cache = <&l2_0>;\n+\t\t};\n+\n+\t\tl2_0: l2-cache {\n+\t\t\tcompatible = \"cache\";\n+\t\t\tcache-level = <2>;\n+\t\t\tcache-unified;\n+\t\t};\n+\t};\n+\n+\tpsci {\n+\t\tcompatible = \"arm,psci-1.0\";\n+\t\tmethod = \"smc\";\n+\t};\n+\n+\tpmu {\n+\t\tcompatible = \"arm,cortex-a53-pmu\";\n+\t\tinterrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, /* Secure Phys IRQ */\n+\t\t\t <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, /* Non-secure Phys IRQ */\n+\t\t\t <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, /* Virt IRQ */\n+\t\t\t <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; /* Hyp IRQ */\n+\t};\n+\n+\taxi: axi {\n+\t\tcompatible = \"simple-bus\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tranges;\n+\n+\t\tusb: usb@300000 {\n+\t\t\tcompatible = \"microchip,lan9691-dwc3\", \"snps,dwc3\";\n+\t\t\treg = <0x300000 0x80000>;\n+\t\t\tinterrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&clks GCK_GATE_USB_DRD>,\n+\t\t\t\t <&clks GCK_ID_USB_REFCLK>;\n+\t\t\tclock-names = \"bus_early\", \"ref\";\n+\t\t\tassigned-clocks = <&clks GCK_ID_USB_REFCLK>;\n+\t\t\tassigned-clock-rates = <60000000>;\n+\t\t\tmaximum-speed = \"high-speed\";\n+\t\t\tdr_mode = \"host\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\totp: otp@e0021000 {\n+\t\t\tcompatible = \"microchip,lan9691-otpc\";\n+\t\t\treg = <0xe0021000 0x1000>;\n+\t\t};\n+\n+\t\tflx0: flexcom@e0040000 {\n+\t\t\tcompatible = \"microchip,lan9691-flexcom\", \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe0040000 0x100>;\n+\t\t\tranges = <0x0 0xe0040000 0x800>;\n+\t\t\tclocks = <&clks GCK_ID_FLEXCOM0>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tusart0: serial@200 {\n+\t\t\t\tcompatible = \"microchip,lan9691-usart\", \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(3)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tatmel,usart-mode = <AT91_USART_MODE_SERIAL>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tspi0: spi@400 {\n+\t\t\t\tcompatible = \"microchip,lan9691-spi\", \"atmel,at91rm9200-spi\";\n+\t\t\t\treg = <0x400 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(3)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"spi_clk\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c0: i2c@600 {\n+\t\t\t\tcompatible = \"microchip,lan9691-i2c\", \"microchip,sam9x60-i2c\";\n+\t\t\t\treg = <0x600 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(3)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tflx1: flexcom@e0044000 {\n+\t\t\tcompatible = \"microchip,lan9691-flexcom\", \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe0044000 0x100>;\n+\t\t\tranges = <0x0 0xe0044000 0x800>;\n+\t\t\tclocks = <&clks GCK_ID_FLEXCOM1>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tusart1: serial@200 {\n+\t\t\t\tcompatible = \"microchip,lan9691-usart\", \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(3)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tatmel,usart-mode = <AT91_USART_MODE_SERIAL>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tspi1: spi@400 {\n+\t\t\t\tcompatible = \"microchip,lan9691-spi\", \"atmel,at91rm9200-spi\";\n+\t\t\t\treg = <0x400 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(3)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"spi_clk\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c1: i2c@600 {\n+\t\t\t\tcompatible = \"microchip,lan9691-i2c\", \"microchip,sam9x60-i2c\";\n+\t\t\t\treg = <0x600 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(3)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(2)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\ttrng: rng@e0048000 {\n+\t\t\tcompatible = \"microchip,lan9691-trng\", \"atmel,at91sam9g45-trng\";\n+\t\t\treg = <0xe0048000 0x100>;\n+\t\t\tclocks = <&fabric_clk>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\taes: crypto@e004c000 {\n+\t\t\tcompatible = \"microchip,lan9691-aes\", \"atmel,at91sam9g46-aes\";\n+\t\t\treg = <0xe004c000 0x100>;\n+\t\t\tinterrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(12)>,\n+\t\t\t <&dma AT91_XDMAC_DT_PERID(13)>;\n+\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\tclocks = <&fabric_clk>;\n+\t\t\tclock-names = \"aes_clk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tflx2: flexcom@e0060000 {\n+\t\t\tcompatible = \"microchip,lan9691-flexcom\", \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe0060000 0x100>;\n+\t\t\tranges = <0x0 0xe0060000 0x800>;\n+\t\t\tclocks = <&clks GCK_ID_FLEXCOM2>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tusart2: serial@200 {\n+\t\t\t\tcompatible = \"microchip,lan9691-usart\", \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(7)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(6)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tatmel,usart-mode = <AT91_USART_MODE_SERIAL>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tspi2: spi@400 {\n+\t\t\t\tcompatible = \"microchip,lan9691-spi\", \"atmel,at91rm9200-spi\";\n+\t\t\t\treg = <0x400 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(7)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(6)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"spi_clk\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c2: i2c@600 {\n+\t\t\t\tcompatible = \"microchip,lan9691-i2c\", \"microchip,sam9x60-i2c\";\n+\t\t\t\treg = <0x600 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(7)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(6)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tflx3: flexcom@e0064000 {\n+\t\t\tcompatible = \"microchip,lan9691-flexcom\", \"atmel,sama5d2-flexcom\";\n+\t\t\treg = <0xe0064000 0x100>;\n+\t\t\tranges = <0x0 0xe0064000 0x800>;\n+\t\t\tclocks = <&clks GCK_ID_FLEXCOM3>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tusart3: serial@200 {\n+\t\t\t\tcompatible = \"microchip,lan9691-usart\", \"atmel,at91sam9260-usart\";\n+\t\t\t\treg = <0x200 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(9)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(8)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"usart\";\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tatmel,usart-mode = <AT91_USART_MODE_SERIAL>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\tspi3: spi@400 {\n+\t\t\t\tcompatible = \"microchip,lan9691-spi\", \"atmel,at91rm9200-spi\";\n+\t\t\t\treg = <0x400 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(9)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(8)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\tclock-names = \"spi_clk\";\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tatmel,fifo-size = <32>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\n+\t\t\ti2c3: i2c@600 {\n+\t\t\t\tcompatible = \"microchip,lan9691-i2c\", \"microchip,sam9x60-i2c\";\n+\t\t\t\treg = <0x600 0x200>;\n+\t\t\t\tinterrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(9)>,\n+\t\t\t\t <&dma AT91_XDMAC_DT_PERID(8)>;\n+\t\t\t\tdma-names = \"tx\", \"rx\";\n+\t\t\t\tclocks = <&fabric_clk>;\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tstatus = \"disabled\";\n+\t\t\t};\n+\t\t};\n+\n+\t\tdma: dma-controller@e0068000 {\n+\t\t\tcompatible = \"microchip,lan9691-dma\", \"microchip,sama7g5-dma\";\n+\t\t\treg = <0xe0068000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdma-channels = <16>;\n+\t\t\t#dma-cells = <1>;\n+\t\t\tclocks = <&fabric_clk>;\n+\t\t\tclock-names = \"dma_clk\";\n+\t\t};\n+\n+\t\tsha: crypto@e006c000 {\n+\t\t\tcompatible = \"microchip,lan9691-sha\", \"atmel,at91sam9g46-sha\";\n+\t\t\treg = <0xe006c000 0xec>;\n+\t\t\tinterrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tdmas = <&dma AT91_XDMAC_DT_PERID(14)>;\n+\t\t\tdma-names = \"tx\";\n+\t\t\tclocks = <&fabric_clk>;\n+\t\t\tclock-names = \"sha_clk\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\ttimer: timer@e008c000 {\n+\t\t\tcompatible = \"snps,dw-apb-timer\";\n+\t\t\treg = <0xe008c000 0x400>;\n+\t\t\tclocks = <&fabric_clk>;\n+\t\t\tclock-names = \"timer\";\n+\t\t\tinterrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\twatchdog: watchdog@e0090000 {\n+\t\t\tcompatible = \"snps,dw-wdt\";\n+\t\t\treg = <0xe0090000 0x1000>;\n+\t\t\tinterrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&fabric_clk>;\n+\t\t};\n+\n+\t\tcpu_ctrl: syscon@e00c0000 {\n+\t\t\tcompatible = \"microchip,lan966x-cpu-syscon\", \"syscon\";\n+\t\t\treg = <0xe00c0000 0x350>;\n+\t\t};\n+\n+\t\tswitch: switch@e00c0000 {\n+\t\t\tcompatible = \"microchip,lan9691-switch\";\n+\t\t\treg = <0xe00c0000 0x0010000>,\n+\t\t\t <0xe2010000 0x1410000>;\n+\t\t\treg-names = \"cpu\", \"devices\";\n+\t\t\tinterrupt-names = \"xtr\", \"fdma\", \"ptp\";\n+\t\t\tinterrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tresets = <&reset 0>;\n+\t\t\treset-names = \"switch\";\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tclks: clock-controller@e00c00b4 {\n+\t\t\tcompatible = \"microchip,lan9691-gck\";\n+\t\t\treg = <0xe00c00b4 0x30>, <0xe00c0308 0x4>;\n+\t\t\t#clock-cells = <1>;\n+\t\t\tclocks = <&cpu_clk>, <&ddr_clk>, <&fx100_clk>;\n+\t\t\tclock-names = \"cpu\", \"ddr\", \"sys\";\n+\t\t};\n+\n+\t\tqspi0: spi@e0804000 {\n+\t\t\tcompatible = \"microchip,lan9691-qspi\";\n+\t\t\treg = <0xe0804000 0x00000100>,\n+\t\t\t <0x20000000 0x08000000>;\n+\t\t\treg-names = \"qspi_base\", \"qspi_mmap\";\n+\t\t\tinterrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&fabric_clk>, <&clks GCK_ID_QSPI0>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t\tassigned-clocks = <&clks GCK_ID_QSPI0>;\n+\t\t\tassigned-clock-rates = <100000000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsdmmc0: mmc@e0830000 {\n+\t\t\tcompatible = \"microchip,lan9691-sdhci\";\n+\t\t\treg = <0xe0830000 0x00000300>;\n+\t\t\tinterrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&clks GCK_ID_SDMMC0>, <&clks GCK_ID_SDMMC0>;\n+\t\t\tclock-names = \"hclock\", \"multclk\";\n+\t\t\tassigned-clocks = <&clks GCK_ID_SDMMC0>;\n+\t\t\tassigned-clock-rates = <100000000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsdmmc1: mmc@e0838000 {\n+\t\t\tcompatible = \"microchip,lan9691-sdhci\";\n+\t\t\treg = <0xe0838000 0x00000300>;\n+\t\t\tinterrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&clks GCK_ID_SDMMC1>, <&clks GCK_ID_SDMMC1>;\n+\t\t\tclock-names = \"hclock\", \"multclk\";\n+\t\t\tassigned-clocks = <&clks GCK_ID_SDMMC1>;\n+\t\t\tassigned-clock-rates = <45000000>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tqspi2: spi@e0834000 {\n+\t\t\tcompatible = \"microchip,lan9691-qspi\";\n+\t\t\treg = <0xe0834000 0x00000100>,\n+\t\t\t <0x30000000 0x04000000>;\n+\t\t\treg-names = \"qspi_base\", \"qspi_mmap\";\n+\t\t\tinterrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&fabric_clk>, <&clks GCK_ID_QSPI2>;\n+\t\t\tclock-names = \"pclk\", \"gclk\";\n+\t\t\tassigned-clocks = <&clks GCK_ID_QSPI2>;\n+\t\t\tassigned-clock-rates = <100000000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\treset: reset-controller@e201000c {\n+\t\t\tcompatible = \"microchip,lan9691-switch-reset\",\n+\t\t\t\t \"microchip,lan966x-switch-reset\";\n+\t\t\treg = <0xe201000c 0x4>;\n+\t\t\treg-names = \"gcb\";\n+\t\t\t#reset-cells = <1>;\n+\t\t\tcpu-syscon = <&cpu_ctrl>;\n+\t\t};\n+\n+\t\tgpio: pinctrl@e20100d4 {\n+\t\t\tcompatible = \"microchip,lan9691-pinctrl\";\n+\t\t\treg = <0xe20100d4 0xd4>,\n+\t\t\t <0xe2010370 0xa8>;\n+\t\t\tgpio-controller;\n+\t\t\t#gpio-cells = <2>;\n+\t\t\tgpio-ranges = <&gpio 0 0 66>;\n+\t\t\tinterrupt-controller;\n+\t\t\tinterrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t#interrupt-cells = <2>;\n+\t\t};\n+\n+\t\tmdio0: mdio@e20101a8 {\n+\t\t\tcompatible = \"microchip,lan9691-miim\", \"mscc,ocelot-miim\";\n+\t\t\treg = <0xe20101a8 0x24>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tclocks = <&fx100_clk>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tmdio1: mdio@e20101cc {\n+\t\t\tcompatible = \"microchip,lan9691-miim\", \"mscc,ocelot-miim\";\n+\t\t\treg = <0xe20101cc 0x24>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tclocks = <&fx100_clk>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tsgpio: gpio@e2010230 {\n+\t\t\tcompatible = \"microchip,lan9691-sgpio\", \"microchip,sparx5-sgpio\";\n+\t\t\treg = <0xe2010230 0x118>;\n+\t\t\tclocks = <&fx100_clk>;\n+\t\t\tresets = <&reset 0>;\n+\t\t\treset-names = \"switch\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t\tstatus = \"disabled\";\n+\n+\t\t\tsgpio_in: gpio@0 {\n+\t\t\t\tcompatible = \"microchip,lan9691-sgpio-bank\",\n+\t\t\t\t\t \"microchip,sparx5-sgpio-bank\";\n+\t\t\t\treg = <0>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <3>;\n+\t\t\t\tinterrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\t\tinterrupt-controller;\n+\t\t\t\t#interrupt-cells = <3>;\n+\t\t\t};\n+\n+\t\t\tsgpio_out: gpio@1 {\n+\t\t\t\tcompatible = \"microchip,lan9691-sgpio-bank\",\n+\t\t\t\t\t \"microchip,sparx5-sgpio-bank\";\n+\t\t\t\treg = <1>;\n+\t\t\t\tgpio-controller;\n+\t\t\t\t#gpio-cells = <3>;\n+\t\t\t};\n+\t\t};\n+\n+\t\ttmon: hwmon@e2020100 {\n+\t\t\tcompatible = \"microchip,lan9691-temp\", \"microchip,sparx5-temp\";\n+\t\t\treg = <0xe2020100 0xc>;\n+\t\t\tclocks = <&fx100_clk>;\n+\t\t\t#thermal-sensor-cells = <0>;\n+\t\t};\n+\n+\t\tserdes: serdes@e3410000 {\n+\t\t\tcompatible = \"microchip,lan9691-serdes\";\n+\t\t\treg = <0xe3410000 0x150000>;\n+\t\t\t#phy-cells = <1>;\n+\t\t\tclocks = <&fabric_clk>;\n+\t\t};\n+\n+\t\tgic: interrupt-controller@e8c11000 {\n+\t\t\tcompatible = \"arm,gic-400\";\n+\t\t\treg = <0xe8c11000 0x1000>, /* Distributor GICD_ */\n+\t\t\t <0xe8c12000 0x2000>, /* CPU interface GICC_ */\n+\t\t\t <0xe8c14000 0x2000>, /* Virt interface control */\n+\t\t\t <0xe8c16000 0x2000>; /* Virt CPU interface */\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\tinterrupt-controller;\n+\t\t\tinterrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi b/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi\nnew file mode 100644\nindex 00000000000..bbbb578cc57\n--- /dev/null\n+++ b/arch/arm/dts/lan9696-ev23x71a-u-boot.dtsi\n@@ -0,0 +1,18 @@\n+\n+#include <dt-bindings/mscc/sparx5_data.h>\n+\n+&switch {\n+\t/delete-node/ ethernet-ports;\n+\n+\tethernet-ports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport29: port@29 {\n+\t\t\treg = <29>;\n+\t\t\tphy-handle = <&phy3>;\n+\t\t\tphy-mode = \"rgmii-rxid\";\n+\t\t\tphys = <IF_RGMII>;\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm/dts/lan9696-ev23x71a.dts b/arch/arm/dts/lan9696-ev23x71a.dts\nnew file mode 100644\nindex 00000000000..4935b6d7b14\n--- /dev/null\n+++ b/arch/arm/dts/lan9696-ev23x71a.dts\n@@ -0,0 +1,795 @@\n+// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT)\n+/*\n+ * Copyright (c) 2025 Microchip Technology Inc. and its subsidiaries.\n+ */\n+\n+/dts-v1/;\n+\n+#include <dt-bindings/gpio/gpio.h>\n+#include <dt-bindings/leds/common.h>\n+#include \"lan9691.dtsi\"\n+\n+/ {\n+\tmodel = \"Microchip EV23X71A\";\n+\tcompatible = \"microchip,ev23x71a\", \"microchip,lan9696\", \"microchip,lan9691\";\n+\n+\taliases {\n+\t\tserial0 = &usart0;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"serial0:115200n8\";\n+\t};\n+\n+\tgpio-restart {\n+\t\tcompatible = \"gpio-restart\";\n+\t\tgpios = <&gpio 60 GPIO_ACTIVE_LOW>;\n+\t\topen-source;\n+\t\tpriority = <200>;\n+\t};\n+\n+\ti2c-mux {\n+\t\tcompatible = \"i2c-mux-gpio\";\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\t\ti2c-parent = <&i2c3>;\n+\t\tidle-state = <0x8>;\n+\t\tmux-gpios = <&sgpio_out 0 1 GPIO_ACTIVE_HIGH>,\n+\t\t\t <&sgpio_out 0 2 GPIO_ACTIVE_HIGH>,\n+\t\t\t <&sgpio_out 0 3 GPIO_ACTIVE_HIGH>;\n+\t\tsettle-time-us = <100>;\n+\n+\t\ti2c_sfp0: i2c@0 {\n+\t\t\treg = <0x0>;\n+\t\t};\n+\n+\t\ti2c_sfp1: i2c@1 {\n+\t\t\treg = <0x1>;\n+\t\t};\n+\n+\t\ti2c_sfp2: i2c@2 {\n+\t\t\treg = <0x2>;\n+\t\t};\n+\n+\t\ti2c_sfp3: i2c@3 {\n+\t\t\treg = <0x3>;\n+\t\t};\n+\n+\t\ti2c_poe: i2c@7 {\n+\t\t\treg = <0x7>;\n+\t\t};\n+\t};\n+\n+\tleds {\n+\t\tcompatible = \"gpio-leds\";\n+\n+\t\tled-status {\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tfunction = LED_FUNCTION_STATUS;\n+\t\t\tgpios = <&gpio 61 GPIO_ACTIVE_LOW>;\n+\t\t};\n+\n+\t\tled-sfp1-green {\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <0>;\n+\t\t\tgpios = <&sgpio_out 6 0 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-sfp1-yellow {\n+\t\t\tcolor = <LED_COLOR_ID_YELLOW>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <0>;\n+\t\t\tgpios = <&sgpio_out 6 1 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-sfp2-green {\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <1>;\n+\t\t\tgpios = <&sgpio_out 7 0 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-sfp2-yellow {\n+\t\t\tcolor = <LED_COLOR_ID_YELLOW>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <1>;\n+\t\t\tgpios = <&sgpio_out 7 1 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-sfp3-green {\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <2>;\n+\t\t\tgpios = <&sgpio_out 8 0 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-sfp3-yellow {\n+\t\t\tcolor = <LED_COLOR_ID_YELLOW>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <2>;\n+\t\t\tgpios = <&sgpio_out 8 1 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-sfp4-green {\n+\t\t\tcolor = <LED_COLOR_ID_GREEN>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <3>;\n+\t\t\tgpios = <&sgpio_out 9 0 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\n+\t\tled-sfp4-yellow {\n+\t\t\tcolor = <LED_COLOR_ID_YELLOW>;\n+\t\t\tfunction = LED_FUNCTION_LAN;\n+\t\t\tfunction-enumerator = <3>;\n+\t\t\tgpios = <&sgpio_out 9 1 GPIO_ACTIVE_LOW>;\n+\t\t\tdefault-state = \"off\";\n+\t\t};\n+\t};\n+\n+\tmux-controller {\n+\t\tcompatible = \"gpio-mux\";\n+\t\t#mux-control-cells = <0>;\n+\t\tmux-gpios = <&sgpio_out 1 2 GPIO_ACTIVE_LOW>,\n+\t\t\t <&sgpio_out 1 3 GPIO_ACTIVE_LOW>;\n+\t};\n+\n+\tsfp0: sfp0 {\n+\t\tcompatible = \"sff,sfp\";\n+\t\ti2c-bus = <&i2c_sfp0>;\n+\t\ttx-disable-gpios = <&sgpio_out 6 2 GPIO_ACTIVE_HIGH>;\n+\t\tlos-gpios = <&sgpio_in 6 0 GPIO_ACTIVE_HIGH>;\n+\t\tmod-def0-gpios = <&sgpio_in 6 1 GPIO_ACTIVE_LOW>;\n+\t\ttx-fault-gpios = <&sgpio_in 6 2 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tsfp1: sfp1 {\n+\t\tcompatible = \"sff,sfp\";\n+\t\ti2c-bus = <&i2c_sfp1>;\n+\t\ttx-disable-gpios = <&sgpio_out 7 2 GPIO_ACTIVE_HIGH>;\n+\t\tlos-gpios = <&sgpio_in 7 0 GPIO_ACTIVE_HIGH>;\n+\t\tmod-def0-gpios = <&sgpio_in 7 1 GPIO_ACTIVE_LOW>;\n+\t\ttx-fault-gpios = <&sgpio_in 7 2 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tsfp2: sfp2 {\n+\t\tcompatible = \"sff,sfp\";\n+\t\ti2c-bus = <&i2c_sfp2>;\n+\t\ttx-disable-gpios = <&sgpio_out 8 2 GPIO_ACTIVE_HIGH>;\n+\t\tlos-gpios = <&sgpio_in 8 0 GPIO_ACTIVE_HIGH>;\n+\t\tmod-def0-gpios = <&sgpio_in 8 1 GPIO_ACTIVE_LOW>;\n+\t\ttx-fault-gpios = <&sgpio_in 8 2 GPIO_ACTIVE_HIGH>;\n+\t};\n+\n+\tsfp3: sfp3 {\n+\t\tcompatible = \"sff,sfp\";\n+\t\ti2c-bus = <&i2c_sfp3>;\n+\t\ttx-disable-gpios = <&sgpio_out 9 2 GPIO_ACTIVE_HIGH>;\n+\t\tlos-gpios = <&sgpio_in 9 0 GPIO_ACTIVE_HIGH>;\n+\t\tmod-def0-gpios = <&sgpio_in 9 1 GPIO_ACTIVE_LOW>;\n+\t\ttx-fault-gpios = <&sgpio_in 9 2 GPIO_ACTIVE_HIGH>;\n+\t};\n+};\n+\n+&gpio {\n+\temmc_sd_pins: emmc-sd-pins {\n+\t\t/* eMMC_SD - CMD, CLK, D0, D1, D2, D3, D4, D5, D6, D7, RSTN */\n+\t\tpins = \"GPIO_14\", \"GPIO_15\", \"GPIO_16\", \"GPIO_17\",\n+\t\t \"GPIO_18\", \"GPIO_19\", \"GPIO_20\", \"GPIO_21\",\n+\t\t \"GPIO_22\", \"GPIO_23\", \"GPIO_24\";\n+\t\tfunction = \"emmc_sd\";\n+\t};\n+\n+\tfan_pins: fan-pins {\n+\t\tpins = \"GPIO_25\", \"GPIO_26\";\n+\t\tfunction = \"fan\";\n+\t};\n+\n+\tfc0_pins: fc0-pins {\n+\t\tpins = \"GPIO_3\", \"GPIO_4\";\n+\t\tfunction = \"fc\";\n+\t};\n+\n+\tfc2_pins: fc2-pins {\n+\t\tpins = \"GPIO_64\", \"GPIO_65\", \"GPIO_66\";\n+\t\tfunction = \"fc\";\n+\t};\n+\n+\tfc3_pins: fc3-pins {\n+\t\tpins = \"GPIO_55\", \"GPIO_56\";\n+\t\tfunction = \"fc\";\n+\t};\n+\n+\tmdio_irq_pins: mdio-irq-pins {\n+\t\tpins = \"GPIO_11\";\n+\t\tfunction = \"miim_irq\";\n+\t};\n+\n+\tmdio_pins: mdio-pins {\n+\t\tpins = \"GPIO_9\", \"GPIO_10\";\n+\t\tfunction = \"miim\";\n+\t};\n+\n+\tptp_ext_pins: ptp-ext-pins {\n+\t\tpins = \"GPIO_59\";\n+\t\tfunction = \"ptpsync_5\";\n+\t};\n+\n+\tptp_out_pins: ptp-out-pins {\n+\t\tpins = \"GPIO_58\";\n+\t\tfunction = \"ptpsync_4\";\n+\t};\n+\n+\tsgpio_pins: sgpio-pins {\n+\t\t/* SCK, D0, D1, LD */\n+\t\tpins = \"GPIO_5\", \"GPIO_6\", \"GPIO_7\", \"GPIO_8\";\n+\t\tfunction = \"sgpio_a\";\n+\t};\n+\n+\tusb_over_pins: usb-over-pins {\n+\t\tpins = \"GPIO_13\";\n+\t\tfunction = \"usb_over_detect\";\n+\t};\n+\n+\tusb_power_pins: usb-power-pins {\n+\t\tpins = \"GPIO_1\";\n+\t\tfunction = \"usb_power\";\n+\t};\n+\n+\tusb_rst_pins: usb-rst-pins {\n+\t\tpins = \"GPIO_12\";\n+\t\tfunction = \"usb2phy_rst\";\n+\t};\n+\n+\tusb_ulpi_pins: usb-ulpi-pins {\n+\t\tpins = \"GPIO_30\", \"GPIO_31\", \"GPIO_32\", \"GPIO_33\",\n+\t\t \"GPIO_34\", \"GPIO_35\", \"GPIO_36\", \"GPIO_37\",\n+\t\t \"GPIO_38\", \"GPIO_39\", \"GPIO_40\", \"GPIO_41\";\n+\t\tfunction = \"usb_ulpi\";\n+\t};\n+};\n+\n+&flx0 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;\n+\tstatus = \"okay\";\n+};\n+\n+&flx2 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_SPI>;\n+\tstatus = \"okay\";\n+};\n+\n+&flx3 {\n+\tatmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_TWI>;\n+\tstatus = \"okay\";\n+};\n+\n+&i2c3 {\n+\tpinctrl-0 = <&fc3_pins>;\n+\tpinctrl-names = \"default\";\n+\ti2c-analog-filter;\n+\ti2c-digital-filter;\n+\ti2c-digital-filter-width-ns = <35>;\n+\ti2c-sda-hold-time-ns = <1500>;\n+\tstatus = \"okay\";\n+};\n+\n+&mdio0 {\n+\tpinctrl-0 = <&mdio_pins>, <&mdio_irq_pins>;\n+\tpinctrl-names = \"default\";\n+\treset-gpios = <&gpio 62 GPIO_ACTIVE_LOW>;\n+\tstatus = \"okay\";\n+\n+\tphy3: phy@3 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <3>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy4: phy@4 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <4>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy5: phy@5 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <5>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy6: phy@6 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <6>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy7: phy@7 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <7>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy8: phy@8 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <8>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy9: phy@9 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <9>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy10: phy@10 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <10>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy11: phy@11 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <11>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy12: phy@12 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <12>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy13: phy@13 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <13>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy14: phy@14 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <14>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy15: phy@15 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <15>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy16: phy@16 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <16>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy17: phy@17 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <17>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy18: phy@18 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <18>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy19: phy@19 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <19>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy20: phy@20 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <20>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy21: phy@21 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <21>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy22: phy@22 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <22>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy23: phy@23 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <23>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy24: phy@24 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <24>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy25: phy@25 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <25>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy26: phy@26 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <26>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+\n+\tphy27: phy@27 {\n+\t\tcompatible = \"ethernet-phy-ieee802.3-c22\";\n+\t\treg = <27>;\n+\t\tinterrupts = <11 IRQ_TYPE_LEVEL_LOW>;\n+\t\tinterrupt-parent = <&gpio>;\n+\t};\n+};\n+\n+&otp {\n+\tnvmem-layout {\n+\t\tcompatible = \"microchip,otp-layout\";\n+\n+\t\tbase_mac_address: base-mac-address {\n+\t\t\t#nvmem-cell-cells = <1>;\n+\t\t};\n+\t};\n+};\n+\n+&qspi0 {\n+\tstatus = \"okay\";\n+\n+\tflash@0 {\n+\t\tcompatible = \"jedec,spi-nor\";\n+\t\treg = <0>;\n+\t\tspi-max-frequency = <100000000>;\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <1>;\n+\t\tspi-tx-bus-width = <1>;\n+\t\tspi-rx-bus-width = <4>;\n+\t\tm25p,fast-read;\n+\t};\n+};\n+\n+&sdmmc0 {\n+\tpinctrl-0 = <&emmc_sd_pins>;\n+\tpinctrl-names = \"default\";\n+\tmax-frequency = <100000000>;\n+\tbus-width = <8>;\n+\tmmc-ddr-1_8v;\n+\tmmc-hs200-1_8v;\n+\tnon-removable;\n+\tdisable-wp;\n+\tstatus = \"okay\";\n+};\n+\n+&serdes {\n+\tstatus = \"okay\";\n+};\n+\n+&sgpio {\n+\tpinctrl-0 = <&sgpio_pins>;\n+\tpinctrl-names = \"default\";\n+\tmicrochip,sgpio-port-ranges = <0 1>, <6 9>;\n+\tstatus = \"okay\";\n+\n+\tgpio@0 {\n+\t\tngpios = <128>;\n+\t};\n+\tgpio@1 {\n+\t\tngpios = <128>;\n+\t};\n+};\n+\n+&spi2 {\n+\tpinctrl-0 = <&fc2_pins>;\n+\tpinctrl-names = \"default\";\n+\tcs-gpios = <&gpio 63 GPIO_ACTIVE_LOW>;\n+\tstatus = \"okay\";\n+};\n+\n+&switch {\n+\tpinctrl-0 = <&ptp_out_pins>, <&ptp_ext_pins>;\n+\tpinctrl-names = \"default\";\n+\tnvmem-cells = <&base_mac_address 0>;\n+\tnvmem-cell-names = \"mac-address\";\n+\tstatus = \"okay\";\n+\n+\tethernet-ports {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tport0: port@0 {\n+\t\t\treg = <0>;\n+\t\t\tphy-handle = <&phy4>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 0>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport1: port@1 {\n+\t\t\treg = <1>;\n+\t\t\tphy-handle = <&phy5>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 0>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport2: port@2 {\n+\t\t\treg = <2>;\n+\t\t\tphy-handle = <&phy6>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 0>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport3: port@3 {\n+\t\t\treg = <3>;\n+\t\t\tphy-handle = <&phy7>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 0>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport4: port@4 {\n+\t\t\treg = <4>;\n+\t\t\tphy-handle = <&phy8>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 1>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport5: port@5 {\n+\t\t\treg = <5>;\n+\t\t\tphy-handle = <&phy9>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 1>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport6: port@6 {\n+\t\t\treg = <6>;\n+\t\t\tphy-handle = <&phy10>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 1>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport7: port@7 {\n+\t\t\treg = <7>;\n+\t\t\tphy-handle = <&phy11>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 1>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport8: port@8 {\n+\t\t\treg = <8>;\n+\t\t\tphy-handle = <&phy12>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 2>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport9: port@9 {\n+\t\t\treg = <9>;\n+\t\t\tphy-handle = <&phy13>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 2>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport10: port@10 {\n+\t\t\treg = <10>;\n+\t\t\tphy-handle = <&phy14>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 2>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport11: port@11 {\n+\t\t\treg = <11>;\n+\t\t\tphy-handle = <&phy15>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 2>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport12: port@12 {\n+\t\t\treg = <12>;\n+\t\t\tphy-handle = <&phy16>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 3>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport13: port@13 {\n+\t\t\treg = <13>;\n+\t\t\tphy-handle = <&phy17>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 3>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport14: port@14 {\n+\t\t\treg = <14>;\n+\t\t\tphy-handle = <&phy18>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 3>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport15: port@15 {\n+\t\t\treg = <15>;\n+\t\t\tphy-handle = <&phy19>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 3>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport16: port@16 {\n+\t\t\treg = <16>;\n+\t\t\tphy-handle = <&phy20>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 4>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport17: port@17 {\n+\t\t\treg = <17>;\n+\t\t\tphy-handle = <&phy21>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 4>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport18: port@18 {\n+\t\t\treg = <18>;\n+\t\t\tphy-handle = <&phy22>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 4>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport19: port@19 {\n+\t\t\treg = <19>;\n+\t\t\tphy-handle = <&phy23>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 4>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport20: port@20 {\n+\t\t\treg = <20>;\n+\t\t\tphy-handle = <&phy24>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 5>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport21: port@21 {\n+\t\t\treg = <21>;\n+\t\t\tphy-handle = <&phy25>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 5>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport22: port@22 {\n+\t\t\treg = <22>;\n+\t\t\tphy-handle = <&phy26>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 5>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport23: port@23 {\n+\t\t\treg = <23>;\n+\t\t\tphy-handle = <&phy27>;\n+\t\t\tphy-mode = \"qsgmii\";\n+\t\t\tphys = <&serdes 5>;\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\n+\t\tport24: port@24 {\n+\t\t\treg = <24>;\n+\t\t\tphys = <&serdes 6>;\n+\t\t\tphy-mode = \"10gbase-r\";\n+\t\t\tsfp = <&sfp0>;\n+\t\t\tmanaged = \"in-band-status\";\n+\t\t\tmicrochip,bandwidth = <10000>;\n+\t\t\tmicrochip,sd-sgpio = <24>;\n+\t\t};\n+\n+\t\tport25: port@25 {\n+\t\t\treg = <25>;\n+\t\t\tphys = <&serdes 7>;\n+\t\t\tphy-mode = \"10gbase-r\";\n+\t\t\tsfp = <&sfp1>;\n+\t\t\tmanaged = \"in-band-status\";\n+\t\t\tmicrochip,bandwidth = <10000>;\n+\t\t\tmicrochip,sd-sgpio = <28>;\n+\t\t};\n+\n+\t\tport26: port@26 {\n+\t\t\treg = <26>;\n+\t\t\tphys = <&serdes 8>;\n+\t\t\tphy-mode = \"10gbase-r\";\n+\t\t\tsfp = <&sfp2>;\n+\t\t\tmanaged = \"in-band-status\";\n+\t\t\tmicrochip,bandwidth = <10000>;\n+\t\t\tmicrochip,sd-sgpio = <32>;\n+\t\t};\n+\n+\t\tport27: port@27 {\n+\t\t\treg = <27>;\n+\t\t\tphys = <&serdes 9>;\n+\t\t\tphy-mode = \"10gbase-r\";\n+\t\t\tsfp = <&sfp3>;\n+\t\t\tmanaged = \"in-band-status\";\n+\t\t\tmicrochip,bandwidth = <10000>;\n+\t\t\tmicrochip,sd-sgpio = <36>;\n+\t\t};\n+\n+\t\tport29: port@29 {\n+\t\t\treg = <29>;\n+\t\t\tphy-handle = <&phy3>;\n+\t\t\tphy-mode = \"rgmii-id\";\n+\t\t\tmicrochip,bandwidth = <1000>;\n+\t\t};\n+\t};\n+};\n+\n+&tmon {\n+\tpinctrl-0 = <&fan_pins>;\n+\tpinctrl-names = \"default\";\n+};\n+\n+&usart0 {\n+\tpinctrl-0 = <&fc0_pins>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\n+\n+&usb {\n+\tpinctrl-0 = <&usb_ulpi_pins>, <&usb_rst_pins>, <&usb_over_pins>, <&usb_power_pins>;\n+\tpinctrl-names = \"default\";\n+\tstatus = \"okay\";\n+};\ndiff --git a/arch/arm/dts/lan969x-u-boot.dtsi b/arch/arm/dts/lan969x-u-boot.dtsi\nnew file mode 100644\nindex 00000000000..066e0697d77\n--- /dev/null\n+++ b/arch/arm/dts/lan969x-u-boot.dtsi\n@@ -0,0 +1,72 @@\n+\n+&switch {\n+\t/delete-property/ reg;\n+\t/delete-property/ reg-names;\n+\n+\treg = <0xe2900000 0x100000>, // ANA_AC\n+\t <0xe2400000 0x100000>, // ANA_CL\n+\t <0xe2800000 0x100000>, // ANA_L2\n+\t <0xe2480000 0x100000>, // ANA_L3\n+\t <0xe3200000 0x10000>, // ASM\n+\t <0xe2060000 0x10000>, // LRN\n+\t <0xe20b0000 0x10000>, // QFWD\n+\t <0xe2030000 0x20000>, // DEVCPU_QS\n+\t <0xe20a0000 0x10000>, // QSYS\n+\t <0xe2600000 0x80000>, // REW\n+\t <0xe2a00000 0x80000>, // VOP\n+\t <0xe30ec000 0x80000>, // DSM\n+\t <0xe22c0000 0x80000>, // EACL\n+\t <0xe2080000 0x80000>, // VCAP_SUPER\n+\t <0xe2580000 0x80000>, // HSCH\n+\t <0xe30f0000 0x10000>, // PORT_CONF\n+\t <0xe20c0000 0x10000>, // XQS\n+\t <0xe3408000 0x10000>, // HSIO\n+\t <0xe2010000 0x10000>, // GCB\n+\t <0xe00c0000 0x10000>, // CPU\n+\t <0xe2040000 0x10000>, // PTP\n+\t <0xe3004000 0x4000>, // DEV2G5_0\n+\t <0xe3010000 0x4000>, // DEV2G5_1\n+\t <0xe3014000 0x4000>, // DEV2G5_2\n+\t <0xe3018000 0x4000>, // DEV2G5_3\n+\t <0xe301c000 0x4000>, // DEV2G5_4\n+\t <0xe3028000 0x4000>, // DEV2G5_5\n+\t <0xe302c000 0x4000>, // DEV2G5_6\n+\t <0xe3030000 0x4000>, // DEV2G5_7\n+\t <0xe3034000 0x4000>, // DEV2G5_8\n+\t <0xe3040000 0x4000>, // DEV2G5_9\n+\t <0xe304c000 0x4000>, // DEV2G5_10\n+\t <0xe3050000 0x4000>, // DEV2G5_11\n+\t <0xe3054000 0x4000>, // DEV2G5_12\n+\t <0xe3060000 0x4000>, // DEV2G5_13\n+\t <0xe306c000 0x4000>, // DEV2G5_14\n+\t <0xe3070000 0x4000>, // DEV2G5_15\n+\t <0xe3074000 0x4000>, // DEV2G5_16\n+\t <0xe3080000 0x4000>, // DEV2G5_17\n+\t <0xe308c000 0x4000>, // DEV2G5_18\n+\t <0xe3090000 0x4000>, // DEV2G5_19\n+\t <0xe3094000 0x4000>, // DEV2G5_20\n+\t <0xe30a0000 0x4000>, // DEV2G5_21\n+\t <0xe30ac000 0x4000>, // DEV2G5_22\n+\t <0xe30b0000 0x4000>, // DEV2G5_23\n+\t <0xe30b4000 0x4000>, // DEV2G5_24\n+\t <0xe30c0000 0x4000>, // DEV2G5_25\n+\t <0xe30cc000 0x4000>, // DEV2G5_26\n+\t <0xe30d8000 0x4000>, // DEV2G5_27\n+\t <0xe30e4000 0x4000>, // DEV2G5_28 (RGMII)\n+\t <0xe30e8000 0x4000>, // DEV2G5_29 (RGMII)\n+\t <0xe3410000 0x150000>; // SERDES\n+\treg-names =\n+\t \"ana_ac\", \"ana_cl\", \"ana_l2\", \"ana_l3\",\n+\t \"asm\", \"lrn\", \"qfwd\", \"qs\",\n+\t \"qsys\", \"rew\", \"vop\", \"dsm\",\n+\t \"eacl\", \"vcap_super\", \"hsch\", \"port_conf\", \"xqs\",\n+\t \"hsio\", \"gcb\", \"cpu\", \"ptp\",\n+\t \"port0\", \"port1\", \"port2\", \"port3\",\n+\t \"port4\", \"port5\", \"port6\", \"port7\", \"port8\",\n+\t \"port9\", \"port10\", \"port11\", \"port12\", \"port13\",\n+\t \"port14\", \"port15\", \"port16\", \"port17\", \"port18\",\n+\t \"port19\", \"port20\", \"port21\", \"port22\", \"port23\",\n+\t \"port24\", \"port25\", \"port26\", \"port27\", \"port28\",\n+\t \"port29\";\n+\tclocks = <&fabric_clk>;\n+};\ndiff --git a/arch/arm/mach-microchipsw/Kconfig b/arch/arm/mach-microchipsw/Kconfig\nnew file mode 100644\nindex 00000000000..aadd6beb00d\n--- /dev/null\n+++ b/arch/arm/mach-microchipsw/Kconfig\n@@ -0,0 +1,31 @@\n+if ARCH_MICROCHIPSW\n+\n+config SYS_SOC\n+\tdefault \"microchipsw\"\n+\n+config SYS_VENDOR\n+\tdefault \"microchip\"\n+\n+choice\n+\tprompt \"Microchip switch SoC select\"\n+\n+config TARGET_LAN969X\n+\tbool \"Microchip LAN969x SoC\"\n+\tselect ARM64\n+\tselect ARCH_SUPPORT_TFABOOT\n+\tselect DM_SERIAL\n+\tselect DM_GPIO\n+\thelp\n+\t Support for Microchip LAN969X reference board platform.\n+\n+endchoice\n+\n+config SYS_BOARD\n+\tstring \"Board name\"\n+\tdefault \"lan969x\" if TARGET_LAN969X\n+\tdefault \"\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"lan969x\" if TARGET_LAN969X\n+\n+endif\ndiff --git a/arch/arm/mach-microchipsw/Makefile b/arch/arm/mach-microchipsw/Makefile\nnew file mode 100644\nindex 00000000000..39eca321705\n--- /dev/null\n+++ b/arch/arm/mach-microchipsw/Makefile\n@@ -0,0 +1,3 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+\n+obj-$(CONFIG_TARGET_LAN969X) += lan969x/\ndiff --git a/arch/arm/mach-microchipsw/include/mach/soc.h b/arch/arm/mach-microchipsw/include/mach/soc.h\nnew file mode 100644\nindex 00000000000..cd1d61ff121\n--- /dev/null\n+++ b/arch/arm/mach-microchipsw/include/mach/soc.h\n@@ -0,0 +1,29 @@\n+/*\n+ * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: BSD-3-Clause\n+ */\n+\n+#ifndef _MICROCHIPSW_SOC_H_\n+#define _MICROCHIPSW_SOC_H_\n+\n+#if defined(CONFIG_TARGET_LAN969X)\n+#include <asm/types.h>\n+\n+typedef enum {\n+\tBOOT_SOURCE_EMMC = 0,\n+\tBOOT_SOURCE_QSPI,\n+\tBOOT_SOURCE_SDMMC,\n+\tBOOT_SOURCE_NONE\n+} boot_source_type_t;\n+\n+phys_size_t tfa_get_dram_size(void);\n+\n+boot_source_type_t tfa_get_boot_source(void);\n+\n+int tfa_get_board_number(void);\n+\n+phys_size_t tfa_get_sram_info(int ix, phys_addr_t *start);\n+\n+#endif /* CONFIG_TARGET_LAN969X */\n+#endif /* _LAN969X_SOC_H_ */\ndiff --git a/arch/arm/mach-microchipsw/lan969x/Makefile b/arch/arm/mach-microchipsw/lan969x/Makefile\nnew file mode 100644\nindex 00000000000..efa5153a3b7\n--- /dev/null\n+++ b/arch/arm/mach-microchipsw/lan969x/Makefile\n@@ -0,0 +1,3 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+\n+obj-y = soc.o\ndiff --git a/arch/arm/mach-microchipsw/lan969x/soc.c b/arch/arm/mach-microchipsw/lan969x/soc.c\nnew file mode 100644\nindex 00000000000..d094b52f888\n--- /dev/null\n+++ b/arch/arm/mach-microchipsw/lan969x/soc.c\n@@ -0,0 +1,136 @@\n+#include <asm/io.h>\n+#include <dm/uclass.h>\n+#include <linux/arm-smccc.h>\n+#include <linux/bitfield.h>\n+\n+#include <asm/arch/soc.h>\n+\n+#define CPU_RESET_PROT_STAT\t0xe00c0088\n+#define SYS_RST_PROT_VCORE_M\tBIT(5)\n+\n+#define GCB_CHIP_ID\t\t0xe2010000\n+#define PART_ID_M\t\tGENMASK(27, 12)\n+\n+#define GCB_SOFT_RST\t\t0xe201000c\n+#define CHIP_SOFT_RST_M\t\tBIT(0)\n+\n+#define SIP_SVC_UID\t\t0x8200ff01\n+#define SIP_SVC_VERSION\t\t0x8200ff02\n+#define SIP_SVC_GET_BOOTSRC\t0x8200ff09\n+#define SIP_SVC_GET_DDR_SIZE\t0x8200ff0a\n+#define SIP_SVC_GET_BOARD_NO\t0x8200ff0b\n+#define SIP_SVC_SRAM_INFO\t0x8200ff0d\n+\n+enum lan969x_part_id {\n+\tLAN9691VAO = 0x9691, /* lan969x-40-VAO */\n+\tLAN9692VAO = 0x9692, /* lan969x-65-VAO */\n+\tLAN9693VAO = 0x9693, /* lan969x-100-VAO */\n+\tLAN9694\t = 0x9694, /* lan969x-40 */\n+\tLAN9694TSN = 0x9695, /* lan969x-40-TSN */\n+\tLAN9694RED = 0x969A, /* lan969x-40-RED */\n+\tLAN9696 = 0x9696, /* lan969x-60 */\n+\tLAN9696TSN = 0x9697, /* lan969x-60-TSN */\n+\tLAN9696RED = 0x969B, /* lan969x-60-RED */\n+\tLAN9698 = 0x9698, /* lan969x-100 */\n+\tLAN9698TSN = 0x9699, /* lan969x-100-TSN */\n+\tLAN9698RED = 0x969C, /* lan969x-100-RED */\n+};\n+\n+boot_source_type_t tfa_get_boot_source(void)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(SIP_SVC_GET_BOOTSRC, -1, 0, 0, 0, 0, 0, 0, &res);\n+\tif (res.a0)\n+\t\treturn BOOT_SOURCE_NONE;\n+\n+\treturn (boot_source_type_t) res.a1;\n+}\n+\n+phys_size_t tfa_get_dram_size(void)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(SIP_SVC_GET_DDR_SIZE, -1, 0, 0, 0, 0, 0, 0, &res);\n+\tif (res.a0)\n+\t\treturn 0;\n+\n+\treturn res.a1;\n+}\n+\n+int tfa_get_board_number(void)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(SIP_SVC_GET_BOARD_NO, -1, 0, 0, 0, 0, 0, 0, &res);\n+\tif (res.a0)\n+\t\treturn 0;\n+\n+\treturn res.a1;\n+}\n+\n+phys_size_t tfa_get_sram_info(int ix, phys_addr_t *start)\n+{\n+\tstruct arm_smccc_res res;\n+\n+\tarm_smccc_smc(SIP_SVC_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);\n+\tif (res.a0 == 0 && res.a1 <= 1) {\n+\t\t/* SRAM info supported > 0.1 */\n+\t\treturn 0;\n+\t}\n+\n+\tarm_smccc_smc(SIP_SVC_SRAM_INFO, ix, 0, 0, 0, 0, 0, 0, &res);\n+\tif (res.a0) {\n+\t\t/* No SRAM segment 'ix' */\n+\t\treturn 0;\n+\t}\n+\n+\t/* Have SRAM segment */\n+\t*start = res.a1;\n+\treturn res.a2;\n+}\n+\n+__weak void reset_cpu(void)\n+{\n+\tclrbits_le32(CPU_RESET_PROT_STAT, SYS_RST_PROT_VCORE_M);\n+\tsetbits_le32(GCB_SOFT_RST, CHIP_SOFT_RST_M);\n+}\n+\n+static char *part_id_string(u32 chip_id_reg)\n+{\n+\tswitch (FIELD_GET(PART_ID_M, chip_id_reg)) {\n+\tcase LAN9691VAO:\n+\t\treturn \"LAN9691VAO\";\n+\tcase LAN9692VAO:\n+\t\treturn \"LAN9692VAO\";\n+\tcase LAN9693VAO:\n+\t\treturn \"LAN9693VAO\";\n+\tcase LAN9694:\n+\t\treturn \"LAN9694\";\n+\tcase LAN9694TSN:\n+\t\treturn \"LAN9694TSN\";\n+\tcase LAN9694RED:\n+\t\treturn \"LAN9694RED\";\n+\tcase LAN9696:\n+\t\treturn \"LAN9696\";\n+\tcase LAN9696TSN:\n+\t\treturn \"LAN9696TSN\";\n+\tcase LAN9696RED:\n+\t\treturn \"LAN9696RED\";\n+\tcase LAN9698:\n+\t\treturn \"LAN9698\";\n+\tcase LAN9698TSN:\n+\t\treturn \"LAN9698TSN\";\n+\tcase LAN9698RED:\n+\t\treturn \"LAN9698RED\";\n+\tdefault:\n+\t\treturn \"Unknown ID\";\n+\t}\n+}\n+\n+int print_cpuinfo(void)\n+{\n+\tprintf(\"CPU: %s\\n\", part_id_string(readl(GCB_CHIP_ID)));\n+\n+\treturn 0;\n+}\ndiff --git a/board/microchip/lan969x/Makefile b/board/microchip/lan969x/Makefile\nnew file mode 100644\nindex 00000000000..97e3de097b4\n--- /dev/null\n+++ b/board/microchip/lan969x/Makefile\n@@ -0,0 +1,3 @@\n+# SPDX-License-Identifier: GPL-2.0+\n+\n+obj-y\t:= lan969x.o\ndiff --git a/board/microchip/lan969x/lan969x.c b/board/microchip/lan969x/lan969x.c\nnew file mode 100644\nindex 00000000000..47083a95999\n--- /dev/null\n+++ b/board/microchip/lan969x/lan969x.c\n@@ -0,0 +1,115 @@\n+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)\n+/*\n+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.\n+ */\n+\n+#include <asm/io.h>\n+#include <asm/armv8/cpu.h>\n+#include <asm/armv8/mmu.h>\n+#include <dm/uclass.h>\n+#include <dm/uclass-internal.h>\n+#include <linux/sizes.h>\n+#include <asm/global_data.h>\n+#include <env.h>\n+#include <env_internal.h>\n+\n+#include <asm/arch/soc.h>\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+static struct mm_region fa_mem_map[] = {\n+\t{\n+\t\t.virt = PHYS_SDRAM_1,\n+\t\t.phys = PHYS_SDRAM_1,\n+\t\t.size = PHYS_SDRAM_1_SIZE,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t PTE_BLOCK_INNER_SHARE\n+\t}, {\n+\t\t.virt = LAN969X_SRAM_BASE,\n+\t\t.phys = LAN969X_SRAM_BASE,\n+\t\t.size = LAN969X_SRAM_SIZE,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |\n+\t\t\t PTE_BLOCK_INNER_SHARE\n+\t}, {\n+\t\t.virt = LAN969X_QSPI0_MMAP,\n+\t\t.phys = LAN969X_QSPI0_MMAP,\n+\t\t.size = LAN969X_QSPI0_RANGE,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t PTE_BLOCK_NON_SHARE |\n+\t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+\t}, {\n+\t\t.virt = LAN969X_DEV_BASE,\n+\t\t.phys = LAN969X_DEV_BASE,\n+\t\t.size = LAN969X_DEV_SIZE,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t PTE_BLOCK_NON_SHARE |\n+\t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+\t}, {\n+\t\t.virt = LAN969X_USB_BASE,\n+\t\t.phys = LAN969X_USB_BASE,\n+\t\t.size = LAN969X_USB_SIZE,\n+\t\t.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |\n+\t\t\t PTE_BLOCK_NON_SHARE |\n+\t\t\t PTE_BLOCK_PXN | PTE_BLOCK_UXN\n+\t}, {\n+\t\t/* List terminator */\n+\t\t0,\n+\t}\n+};\n+struct mm_region *mem_map = fa_mem_map;\n+\n+int dram_init(void)\n+{\n+\tgd->ram_size = tfa_get_dram_size();\n+\n+\t/* Fall-back to compile-time default */\n+\tif (!gd->ram_size)\n+\t\tgd->ram_size = LAN969X_DDR_SIZE_DEF;\n+\n+\treturn 0;\n+}\n+\n+static void add_memory_bank(int bankno, phys_addr_t start, phys_size_t size)\n+{\n+\tgd->bd->bi_dram[bankno].start = start;\n+\tgd->bd->bi_dram[bankno].size = size;\n+}\n+\n+int dram_init_banksize(void)\n+{\n+\tint bankno = 0;\n+\tphys_addr_t start;\n+\tphys_size_t size;\n+\n+\t/* Add DDR */\n+\tadd_memory_bank(bankno++, PHYS_SDRAM_1, gd->ram_size);\n+\n+\t/* First the lower half of SRAM */\n+\tsize = tfa_get_sram_info(0, &start);\n+\tif (size) {\n+\t\tadd_memory_bank(bankno++, start, size);\n+\t}\n+\n+\t/* Upper half of SRAM has 1st 128K reserved for BL31 */\n+\tsize = tfa_get_sram_info(1, &start);\n+\tif (size) {\n+\t\tadd_memory_bank(bankno++, start, size);\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int arch_cpu_init(void)\n+{\n+\treturn 0;\n+}\n+\n+int mach_cpu_init(void)\n+{\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\treturn 0;\n+}\ndiff --git a/configs/microchip_ev23x71a_defconfig b/configs/microchip_ev23x71a_defconfig\nnew file mode 100644\nindex 00000000000..2717f6e9adf\n--- /dev/null\n+++ b/configs/microchip_ev23x71a_defconfig\n@@ -0,0 +1,77 @@\n+CONFIG_ARM=y\n+CONFIG_POSITION_INDEPENDENT=y\n+# CONFIG_ARM64_SUPPORT_AARCH32 is not set\n+CONFIG_ARCH_MICROCHIPSW=y\n+CONFIG_TFABOOT=y\n+CONFIG_NR_DRAM_BANKS=3\n+CONFIG_ENV_OFFSET=0x0\n+CONFIG_DEFAULT_DEVICE_TREE=\"lan9696-ev23x71a\"\n+CONFIG_SYS_BOOTM_LEN=0x4000000\n+CONFIG_SYS_LOAD_ADDR=0x64000000\n+CONFIG_DEBUG_UART_BASE=0xe0040200\n+CONFIG_DEBUG_UART_CLOCK=250000000\n+CONFIG_DEBUG_UART=y\n+# CONFIG_EFI_LOADER is not set\n+CONFIG_FIT=y\n+CONFIG_FIT_VERBOSE=y\n+# CONFIG_LEGACY_IMAGE_FORMAT is not set\n+CONFIG_HUSH_PARSER=y\n+# CONFIG_HUSH_OLD_PARSER is not set\n+CONFIG_HUSH_MODERN_PARSER=y\n+CONFIG_CMD_CLK=y\n+CONFIG_CMD_GPIO=y\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_MTD=y\n+CONFIG_CMD_PART=y\n+CONFIG_CMD_USB=y\n+CONFIG_CMD_WDT=y\n+CONFIG_CMD_DHCP=y\n+CONFIG_CMD_DNS=y\n+CONFIG_CMD_MII=y\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_WGET=y\n+CONFIG_EFI_PARTITION=y\n+CONFIG_DEVICE_TREE_INCLUDES=\"lan969x-u-boot.dtsi\"\n+CONFIG_ENV_IS_IN_MMC=y\n+CONFIG_ENV_MMC_USE_SW_PARTITION=y\n+CONFIG_ENV_MMC_SW_PARTITION=\"Env\"\n+CONFIG_PROT_TCP_SACK=y\n+CONFIG_NET_RANDOM_ETHADDR=y\n+CONFIG_CLK=y\n+CONFIG_CLK_LAN966X=y\n+# CONFIG_I2C is not set\n+# CONFIG_INPUT is not set\n+CONFIG_LED=y\n+CONFIG_LED_GPIO=y\n+CONFIG_MISC=y\n+CONFIG_MICROCHIP_FLEXCOM=y\n+CONFIG_MMC_SDHCI=y\n+CONFIG_MMC_SDHCI_ATMEL=y\n+CONFIG_MTD=y\n+CONFIG_DM_MTD=y\n+CONFIG_DM_SPI_FLASH=y\n+CONFIG_SPI_FLASH_SFDP_SUPPORT=y\n+CONFIG_SPI_FLASH_SST=y\n+CONFIG_SPI_FLASH_MTD=y\n+CONFIG_PHY_MICROCHIP=y\n+CONFIG_DM_MDIO=y\n+CONFIG_PHY_GIGE=y\n+CONFIG_MSCC_LAN969X_SWITCH=y\n+CONFIG_MDIO_MSCC_MIIM=y\n+CONFIG_PINCTRL=y\n+CONFIG_PINCTRL_LAN969X=y\n+CONFIG_SERIAL_SEARCH_ALL=y\n+CONFIG_DEBUG_UART_ANNOUNCE=y\n+CONFIG_DEBUG_UART_SKIP_INIT=y\n+CONFIG_ATMEL_USART=y\n+CONFIG_SPI=y\n+CONFIG_DM_SPI=y\n+CONFIG_ATMEL_QSPI=y\n+CONFIG_SYSRESET=y\n+CONFIG_SYSRESET_GPIO=y\n+CONFIG_USB=y\n+CONFIG_USB_XHCI_HCD=y\n+CONFIG_USB_DWC3=y\n+CONFIG_USB_DWC3_GENERIC=y\n+CONFIG_DESIGNWARE_WATCHDOG=y\n+CONFIG_WDT=y\ndiff --git a/include/configs/lan969x.h b/include/configs/lan969x.h\nnew file mode 100644\nindex 00000000000..3164b1b3da2\n--- /dev/null\n+++ b/include/configs/lan969x.h\n@@ -0,0 +1,36 @@\n+/*\n+ * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries.\n+ *\n+ * SPDX-License-Identifier: BSD-3-Clause\n+ */\n+\n+#ifndef __LAN969X_CONFIG_H\n+#define __LAN969X_CONFIG_H\n+\n+#include <linux/sizes.h>\n+\n+/* LAN969X defines */\n+#define LAN969X_QSPI0_MMAP UL(0x20000000)\n+#define LAN969X_QSPI0_RANGE SZ_256M\n+#define LAN969X_SRAM_BASE UL(0x00100000)\n+#define LAN969X_SRAM_SIZE SZ_2M\n+#define LAN969X_DDR_BASE UL(0x60000000)\n+#define LAN969X_DDR_SIZE_DEF (SZ_1G - (SZ_1G / 8)) /* ECC enabled cost 1/8th capacity */\n+#define LAN969X_DDR_SIZE_MAX SZ_2G\n+\n+#define LAN969X_DEV_BASE\tUL(0xE0000000)\n+#define LAN969X_DEV_SIZE\tUL(0x10000000)\n+\n+#define LAN969X_USB_BASE\t0x300000\n+#define LAN969X_USB_SIZE\t0x80000\n+\n+#define PHYS_SDRAM_1\t\tLAN969X_DDR_BASE\n+#define PHYS_SDRAM_1_SIZE\tLAN969X_DDR_SIZE_MAX /* Used for MMU table - only */\n+\n+#define CFG_SYS_SDRAM_BASE LAN969X_DDR_BASE\n+#define CFG_SYS_INIT_RAM_ADDR\t(LAN969X_DDR_BASE + SZ_64M)\n+#define CFG_SYS_INIT_RAM_SIZE\tSZ_32K\n+\n+#define CFG_SYS_BOOTMAPSZ\tSZ_64M\t/* Initial map for Linux*/\n+\n+#endif\t/* __LAN969X_CONFIG_H */\n", "prefixes": [ "14/14" ] }