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GET /api/patches/2216409/?format=api
{ "id": 2216409, "url": "http://patchwork.ozlabs.org/api/patches/2216409/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-13-robert.marko@sartura.hr/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326112830.313874-13-robert.marko@sartura.hr>", "list_archive_url": null, "date": "2026-03-26T11:26:54", "name": "[13/14] net: phy: add Microchip LAN8841 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "f8e34d739b4c4bb143ada2fa3c11c06f6d1887d1", "submitter": { "id": 78207, "url": "http://patchwork.ozlabs.org/api/people/78207/?format=api", "name": "Robert Marko", "email": "robert.marko@sartura.hr" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-13-robert.marko@sartura.hr/mbox/", "series": [ { "id": 497572, "url": "http://patchwork.ozlabs.org/api/series/497572/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497572", "date": "2026-03-26T11:26:42", "name": "[01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497572/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216409/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216409/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.a=rsa-sha256\n header.s=sartura header.b=HnbCPo4Z;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.b=\"HnbCPo4Z\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=robert.marko@sartura.hr" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhM5w561Bz1yGD\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 22:30:44 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 5334A83FA3;\n\tThu, 26 Mar 2026 12:29:42 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id EA01D840B5; Thu, 26 Mar 2026 12:29:40 +0100 (CET)", "from mail-dl1-x122c.google.com (mail-dl1-x122c.google.com\n [IPv6:2607:f8b0:4864:20::122c])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 8CAD481E18\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 12:29:38 +0100 (CET)", "by mail-dl1-x122c.google.com with SMTP id\n a92af1059eb24-126ea4e9694so2002375c88.1\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 04:29:38 -0700 (PDT)", "from fedora (cpe-109-60-83-68.zg3.cable.xnet.hr. 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a92af1059eb24-12a96eeaf79mr3631130c88.34.1774524575864;\n Thu, 26 Mar 2026 04:29:35 -0700 (PDT)", "From": "Robert Marko <robert.marko@sartura.hr>", "To": "u-boot@lists.denx.de, trini@konsulko.com, lukma@denx.de, hs@nabladev.com,\n peng.fan@nxp.com, jh80.chung@samsung.com, gregory.clement@bootlin.com,\n lars.povlsen@microchip.com, horatiu.vultur@microchip.com,\n jerome.forissier@arm.com, marex@denx.de, daniel.machon@microchip.com", "Cc": "luka.perkov@sartura.hr,\n\tRobert Marko <robert.marko@sartura.hr>", "Subject": "[PATCH 13/14] net: phy: add Microchip LAN8841 support", "Date": "Thu, 26 Mar 2026 12:26:54 +0100", "Message-ID": "<20260326112830.313874-13-robert.marko@sartura.hr>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260326112830.313874-1-robert.marko@sartura.hr>", "References": "<20260326112830.313874-1-robert.marko@sartura.hr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Add driver for the Microchip LAN8841 PHY.\n\nIt provides fixes for erratas, as well as support for enabling the required\nRGMII delays based on the PHY mode.\n\nIt is based on the upstream Linux driver.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/net/phy/Kconfig | 3 +\n drivers/net/phy/Makefile | 1 +\n drivers/net/phy/microchip.c | 185 ++++++++++++++++++++++++++++++++++++\n 3 files changed, 189 insertions(+)\n create mode 100644 drivers/net/phy/microchip.c", "diff": "diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig\nindex 709f1c91eb2..3eaf9d7495f 100644\n--- a/drivers/net/phy/Kconfig\n+++ b/drivers/net/phy/Kconfig\n@@ -231,6 +231,9 @@ config PHY_MICREL_KSZ8XXX\n \n endif # PHY_MICREL\n \n+config PHY_MICROCHIP\n+\tbool \"Microchip Ethernet PHYs support\"\n+\n config PHY_MOTORCOMM\n \ttristate \"Motorcomm PHYs\"\n \thelp\ndiff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile\nindex 83520de7f1f..04e9d61a3c2 100644\n--- a/drivers/net/phy/Makefile\n+++ b/drivers/net/phy/Makefile\n@@ -25,6 +25,7 @@ obj-y += mediatek/\n obj-y += airoha/\n obj-$(CONFIG_PHY_MICREL_KSZ8XXX) += micrel_ksz8xxx.o\n obj-$(CONFIG_PHY_MICREL_KSZ90X1) += micrel_ksz90x1.o\n+obj-$(CONFIG_PHY_MICROCHIP) += microchip.o\n obj-$(CONFIG_PHY_MESON_GXL) += meson-gxl.o\n obj-$(CONFIG_PHY_MOTORCOMM) += motorcomm.o\n obj-$(CONFIG_PHY_NATSEMI) += natsemi.o\ndiff --git a/drivers/net/phy/microchip.c b/drivers/net/phy/microchip.c\nnew file mode 100644\nindex 00000000000..bc54311ab72\n--- /dev/null\n+++ b/drivers/net/phy/microchip.c\n@@ -0,0 +1,185 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+\n+#include <phy.h>\n+#include <linux/bitops.h>\n+\n+#define PHY_ID_MATCH_MODEL_MASK \tGENMASK(31, 4)\n+#define PHY_ID_LAN8841\t\t\t0x00221650\n+\n+#define LAN8841_MMD_COMMON_CTRL_REG\t2\n+#define LAN8841_RXC_DLL_CTRL\t\t76\n+#define LAN8841_TXC_DLL_CTRL\t\t77\n+#define LAN8841_DLL_ENABLE_DELAY\t0\n+\n+#define LAN8841_MMD_TIMER_REG\t\t\t0\n+#define LAN8841_MMD0_REGISTER_17\t\t17\n+#define LAN8841_MMD0_REGISTER_17_DROP_OPT(x)\t((x) & 0x3)\n+#define LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS\tBIT(3)\n+#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG\t2\n+#define LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK\tBIT(14)\n+#define LAN8841_MMD_ANALOG_REG\t\t\t28\n+#define LAN8841_ANALOG_CONTROL_1\t\t1\n+#define LAN8841_ANALOG_CONTROL_1_PLL_TRIM(x)\t(((x) & 0x3) << 5)\n+#define LAN8841_ANALOG_CONTROL_10\t\t13\n+#define LAN8841_ANALOG_CONTROL_10_PLL_DIV(x)\t((x) & 0x3)\n+#define LAN8841_ANALOG_CONTROL_11\t\t14\n+#define LAN8841_ANALOG_CONTROL_11_LDO_REF(x)\t(((x) & 0x7) << 12)\n+#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT\t69\n+#define LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL 0xbffc\n+#define LAN8841_BTRX_POWER_DOWN\t\t\t70\n+#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A\tBIT(0)\n+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_A\tBIT(1)\n+#define LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B\tBIT(2)\n+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_B\tBIT(3)\n+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_C\tBIT(5)\n+#define LAN8841_BTRX_POWER_DOWN_BTRX_CH_D\tBIT(7)\n+#define LAN8841_ADC_CHANNEL_MASK\t\t198\n+#define LAN8841_PTP_RX_PARSE_L2_ADDR_EN\t\t370\n+#define LAN8841_PTP_RX_PARSE_IP_ADDR_EN\t\t371\n+#define LAN8841_PTP_RX_VERSION\t\t\t374\n+#define LAN8841_PTP_TX_PARSE_L2_ADDR_EN\t\t434\n+#define LAN8841_PTP_TX_PARSE_IP_ADDR_EN\t\t435\n+#define LAN8841_PTP_TX_VERSION\t\t\t438\n+#define LAN8841_PTP_CMD_CTL\t\t\t256\n+#define LAN8841_PTP_CMD_CTL_PTP_ENABLE\t\tBIT(2)\n+#define LAN8841_PTP_CMD_CTL_PTP_DISABLE\t\tBIT(1)\n+#define LAN8841_PTP_CMD_CTL_PTP_RESET\t\tBIT(0)\n+#define LAN8841_PTP_RX_PARSE_CONFIG\t\t368\n+#define LAN8841_PTP_TX_PARSE_CONFIG\t\t432\n+#define LAN8841_PTP_RX_MODE\t\t\t381\n+#define LAN8841_PTP_INSERT_TS_EN\t\tBIT(0)\n+#define LAN8841_PTP_INSERT_TS_32BIT\t\tBIT(1)\n+\n+static int lan8841_config_rgmii_delay(struct phy_device *phydev)\n+{\n+\tu16 rxcdll_val, txcdll_val;\n+\tint ret;\n+\n+\tswitch (phydev->interface) {\n+\tcase PHY_INTERFACE_MODE_RGMII:\n+\t\trxcdll_val = BIT(14);\n+\t\ttxcdll_val = BIT(14);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RGMII_ID:\n+\t\trxcdll_val = LAN8841_DLL_ENABLE_DELAY;\n+\t\ttxcdll_val = LAN8841_DLL_ENABLE_DELAY;\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RGMII_RXID:\n+\t\trxcdll_val = LAN8841_DLL_ENABLE_DELAY;\n+\t\ttxcdll_val = BIT(14);\n+\t\tbreak;\n+\tcase PHY_INTERFACE_MODE_RGMII_TXID:\n+\t\trxcdll_val = BIT(14);\n+\t\ttxcdll_val = LAN8841_DLL_ENABLE_DELAY;\n+\t\tbreak;\n+\tdefault:\n+\t\treturn 0;\n+\t}\n+\n+\tret = phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t\t LAN8841_RXC_DLL_CTRL, BIT_MASK(14),\n+\t\t\t rxcdll_val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn phy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t\t LAN8841_TXC_DLL_CTRL, BIT_MASK(14),\n+\t\t\t txcdll_val);\n+}\n+\n+static int lan8841_config_init(struct phy_device *phydev)\n+{\n+\tint ret;\n+\n+\tif (phy_interface_is_rgmii(phydev)) {\n+\t\tret = lan8841_config_rgmii_delay(phydev);\n+\t\tif (ret < 0)\n+\t\t\treturn ret;\n+\t}\n+\n+\t/* Initialize the HW by resetting everything */\n+\tphy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_CMD_CTL,\n+\t\t LAN8841_PTP_CMD_CTL_PTP_RESET,\n+\t\t LAN8841_PTP_CMD_CTL_PTP_RESET);\n+\n+\tphy_modify_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_CMD_CTL,\n+\t\t LAN8841_PTP_CMD_CTL_PTP_ENABLE,\n+\t\t LAN8841_PTP_CMD_CTL_PTP_ENABLE);\n+\n+\t/* Don't process any frames */\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_RX_PARSE_CONFIG, 0);\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_TX_PARSE_CONFIG, 0);\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_TX_PARSE_L2_ADDR_EN, 0);\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_RX_PARSE_L2_ADDR_EN, 0);\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_TX_PARSE_IP_ADDR_EN, 0);\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_RX_PARSE_IP_ADDR_EN, 0);\n+\n+\t/* Disable checking for minorVersionPTP field */\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_RX_VERSION, 0xff00);\n+\tphy_write_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t LAN8841_PTP_TX_VERSION, 0xff00);\n+\n+\t/* 100BT Clause 40 improvement errata */\n+\tphy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,\n+\t\t LAN8841_ANALOG_CONTROL_1,\n+\t\t LAN8841_ANALOG_CONTROL_1_PLL_TRIM(0x2));\n+\tphy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,\n+\t\t LAN8841_ANALOG_CONTROL_10,\n+\t\t LAN8841_ANALOG_CONTROL_10_PLL_DIV(0x1));\n+\n+\t/* 10M/100M Ethernet Signal Tuning Errata for Shorted-Center Tap\n+\t * Magnetics\n+\t */\n+\tret = phy_read_mmd(phydev, LAN8841_MMD_COMMON_CTRL_REG,\n+\t\t\t LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG);\n+\tif (ret & LAN8841_OPERATION_MODE_STRAP_OVERRIDE_LOW_REG_MAGJACK) {\n+\t\tphy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,\n+\t\t\t LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT,\n+\t\t\t LAN8841_TX_LOW_I_CH_C_D_POWER_MANAGMENT_VAL);\n+\t\tphy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,\n+\t\t\t LAN8841_BTRX_POWER_DOWN,\n+\t\t\t LAN8841_BTRX_POWER_DOWN_QBIAS_CH_A |\n+\t\t\t LAN8841_BTRX_POWER_DOWN_BTRX_CH_A |\n+\t\t\t LAN8841_BTRX_POWER_DOWN_QBIAS_CH_B |\n+\t\t\t LAN8841_BTRX_POWER_DOWN_BTRX_CH_B |\n+\t\t\t LAN8841_BTRX_POWER_DOWN_BTRX_CH_C |\n+\t\t\t LAN8841_BTRX_POWER_DOWN_BTRX_CH_D);\n+\t}\n+\n+\t/* LDO Adjustment errata */\n+\tphy_write_mmd(phydev, LAN8841_MMD_ANALOG_REG,\n+\t\t LAN8841_ANALOG_CONTROL_11,\n+\t\t LAN8841_ANALOG_CONTROL_11_LDO_REF(1));\n+\n+\t/* 100BT RGMII latency tuning errata */\n+\tphy_write_mmd(phydev, MDIO_MMD_PMAPMD,\n+\t\t LAN8841_ADC_CHANNEL_MASK, 0x0);\n+\tphy_write_mmd(phydev, LAN8841_MMD_TIMER_REG,\n+\t\t LAN8841_MMD0_REGISTER_17,\n+\t\t LAN8841_MMD0_REGISTER_17_DROP_OPT(2) |\n+\t\t LAN8841_MMD0_REGISTER_17_XMIT_TOG_TX_DIS);\n+\n+\t/* Disable Power Down */\n+\tphy_modify(phydev, MDIO_DEVAD_NONE, MII_BMCR, BMCR_PDOWN, 0);\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_PHY_DRIVER(lan8841) = {\n+\t.name = \"Microchip LAN8841\",\n+\t.uid = PHY_ID_LAN8841,\n+\t.mask = PHY_ID_MATCH_MODEL_MASK,\n+\t.features = PHY_GBIT_FEATURES,\n+\t.config = &lan8841_config_init,\n+\t.startup = &genphy_startup,\n+\t.shutdown = &genphy_shutdown,\n+};\n", "prefixes": [ "13/14" ] }