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GET /api/patches/2216398/?format=api
{ "id": 2216398, "url": "http://patchwork.ozlabs.org/api/patches/2216398/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-3-robert.marko@sartura.hr/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326112830.313874-3-robert.marko@sartura.hr>", "list_archive_url": null, "date": "2026-03-26T11:26:44", "name": "[03/14] clk: add Microchip LAN966x and LAN969x support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "59740bfcdf03553e8329b22d1778933462f8219c", "submitter": { "id": 78207, "url": "http://patchwork.ozlabs.org/api/people/78207/?format=api", "name": "Robert Marko", "email": "robert.marko@sartura.hr" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-3-robert.marko@sartura.hr/mbox/", "series": [ { "id": 497572, "url": "http://patchwork.ozlabs.org/api/series/497572/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497572", "date": "2026-03-26T11:26:42", "name": "[01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497572/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216398/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216398/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.a=rsa-sha256\n header.s=sartura header.b=zj/vzwfL;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.b=\"zj/vzwfL\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=robert.marko@sartura.hr" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhM49192nz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 22:29:13 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id C7D2783FA3;\n\tThu, 26 Mar 2026 12:28:59 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 7A50C83FA3; Thu, 26 Mar 2026 12:28:58 +0100 (CET)", "from mail-dl1-x122d.google.com (mail-dl1-x122d.google.com\n [IPv6:2607:f8b0:4864:20::122d])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 1DBE881E18\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 12:28:56 +0100 (CET)", "by mail-dl1-x122d.google.com with SMTP id\n a92af1059eb24-1273349c56bso1061700c88.0\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 04:28:56 -0700 (PDT)", "from fedora (cpe-109-60-83-68.zg3.cable.xnet.hr. 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a92af1059eb24-12a96f0944emr3395503c88.34.1774524533877;\n Thu, 26 Mar 2026 04:28:53 -0700 (PDT)", "From": "Robert Marko <robert.marko@sartura.hr>", "To": "u-boot@lists.denx.de, trini@konsulko.com, lukma@denx.de, hs@nabladev.com,\n peng.fan@nxp.com, jh80.chung@samsung.com, gregory.clement@bootlin.com,\n lars.povlsen@microchip.com, horatiu.vultur@microchip.com,\n jerome.forissier@arm.com, marex@denx.de, daniel.machon@microchip.com", "Cc": "luka.perkov@sartura.hr,\n\tRobert Marko <robert.marko@sartura.hr>", "Subject": "[PATCH 03/14] clk: add Microchip LAN966x and LAN969x support", "Date": "Thu, 26 Mar 2026 12:26:44 +0100", "Message-ID": "<20260326112830.313874-3-robert.marko@sartura.hr>", "X-Mailer": "git-send-email 2.53.0", "In-Reply-To": "<20260326112830.313874-1-robert.marko@sartura.hr>", "References": "<20260326112830.313874-1-robert.marko@sartura.hr>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "Import clock driver for Microchip LAN966x and LAN969x SoC-s from the vendor\nU-Boot as it is based on the upstream Linux driver.\n\nSigned-off-by: Robert Marko <robert.marko@sartura.hr>\n---\n drivers/clk/Makefile | 2 +-\n drivers/clk/microchip/Kconfig | 7 +\n drivers/clk/microchip/Makefile | 3 +-\n drivers/clk/microchip/clk-lan966x.c | 198 ++++++++++++++++++++++++++++\n 4 files changed, 208 insertions(+), 2 deletions(-)\n create mode 100644 drivers/clk/microchip/clk-lan966x.c", "diff": "diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile\nindex 5f0c0d8a5c2..88b76652378 100644\n--- a/drivers/clk/Makefile\n+++ b/drivers/clk/Makefile\n@@ -39,7 +39,7 @@ obj-$(CONFIG_CLK_EXYNOS) += exynos/\n obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o\n obj-$(CONFIG_CLK_K210) += clk_k210.o\n obj-$(CONFIG_CLK_MPC83XX) += mpc83xx_clk.o\n-obj-$(CONFIG_CLK_MPFS) += microchip/\n+obj-y += microchip/\n obj-$(CONFIG_CLK_MVEBU) += mvebu/\n obj-$(CONFIG_CLK_OCTEON) += clk_octeon.o\n obj-$(CONFIG_CLK_OWL) += owl/\ndiff --git a/drivers/clk/microchip/Kconfig b/drivers/clk/microchip/Kconfig\nindex 62072e100b1..275cd849fec 100644\n--- a/drivers/clk/microchip/Kconfig\n+++ b/drivers/clk/microchip/Kconfig\n@@ -1,3 +1,10 @@\n+config CLK_LAN966X\n+\tbool \"Microchip LAN966X and LAN969X clock support\"\n+\tdepends on ARCH_MICROCHIPSW\n+\tdepends on CLK\n+\thelp\n+\t Clock driver for Microchip LAN969X platforms.\n+\n config CLK_MPFS\n \tbool \"Clock support for Microchip PolarFire SoC\"\n \tdepends on CLK && CLK_CCF\ndiff --git a/drivers/clk/microchip/Makefile b/drivers/clk/microchip/Makefile\nindex 329b2c0c93f..bce4cbebd69 100644\n--- a/drivers/clk/microchip/Makefile\n+++ b/drivers/clk/microchip/Makefile\n@@ -1 +1,2 @@\n-obj-y += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o mpfs_clk_msspll.o\n+obj-$(CONFIG_CLK_LAN966X) += clk-lan966x.o\n+obj-$(CONFIG_CLK_MPFS) += += mpfs_clk.o mpfs_clk_cfg.o mpfs_clk_periph.o mpfs_clk_msspll.o\ndiff --git a/drivers/clk/microchip/clk-lan966x.c b/drivers/clk/microchip/clk-lan966x.c\nnew file mode 100644\nindex 00000000000..1d704af006c\n--- /dev/null\n+++ b/drivers/clk/microchip/clk-lan966x.c\n@@ -0,0 +1,198 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+\n+#include <asm/io.h>\n+#include <clk-uclass.h>\n+#include <div64.h>\n+#include <dm.h>\n+#include <regmap.h>\n+#include <syscon.h>\n+#include <linux/bitfield.h>\n+\n+#define GCK_ENA BIT(0)\n+#define GCK_SRC_SEL GENMASK(9, 8)\n+#define GCK_PRESCALER GENMASK(23, 16)\n+\n+struct lan966x_soc_clk_gate_desc {\n+\tconst char *name;\n+\tint bit_idx;\n+};\n+\n+static const struct lan966x_soc_clk_gate_desc lan966x_clk_gate_desc[] = {\n+\t{ \"uhphs\", 11 },\n+\t{ \"udphs\", 10 },\n+\t{ \"mcramc\", 9 },\n+\t{ \"hmatrix\", 8 },\n+\t{ }\n+};\n+\n+static const struct lan966x_soc_clk_gate_desc lan969x_clk_gate_desc[] = {\n+\t{ \"usb_drd\", 10 },\n+\t{ \"mcramc\", 9 },\n+\t{ \"hmatrix\", 8 },\n+\t{ }\n+};\n+\n+struct lan966x_clk {\n+\tvoid *base;\n+\tvoid *gate;\n+\tint clk_cnt;\n+\tint clk_gate_cnt;\n+\tconst struct lan966x_soc_clk_gate_desc *clk_gate_desc;\n+\tulong parent_rate;\n+};\n+\n+struct lan966x_driver_data {\n+\tint clk_cnt;\n+\tint clk_gate_cnt;\n+\tconst struct lan966x_soc_clk_gate_desc *clk_gate_desc;\n+\tulong parent_rate;\n+};\n+\n+static struct lan966x_driver_data lan966x_data = {\n+\t.clk_cnt = 14,\n+\t.clk_gate_cnt = 4,\n+\t.clk_gate_desc = lan966x_clk_gate_desc,\n+\t.parent_rate = 600000000,\n+};\n+\n+static struct lan966x_driver_data lan969x_data = {\n+\t.clk_cnt = 12,\n+\t.clk_gate_cnt = 3,\n+\t.clk_gate_desc = lan969x_clk_gate_desc,\n+\t.parent_rate = 1000000000,\n+};\n+\n+static void* lan966x_clk_ctlreg(struct lan966x_clk *gck, u8 id)\n+{\n+\treturn gck->base + (id * sizeof(u32));\n+}\n+\n+static ulong lan966x_clk_set_rate(struct clk *clk, ulong rate)\n+{\n+\tstruct lan966x_clk *gck = dev_get_priv(clk->dev);\n+\tunsigned long parent_rate = gck->parent_rate;\n+\tu32 div;\n+\n+\tif (clk->id >= gck->clk_cnt)\n+\t\treturn -ENODEV;\n+\n+\tif (rate == 0)\n+\t\treturn -EINVAL;\n+\n+\t/* Calc divisor */\n+\tdiv = DIV_ROUND_CLOSEST(parent_rate, rate);\n+\n+\t/* Set src, prescaler */\n+\tclrsetbits_le32(lan966x_clk_ctlreg(gck, clk->id),\n+\t\t\tGCK_SRC_SEL | GCK_PRESCALER,\n+\t\t\t/* Select CPU_CLK as source always */\n+\t\t\tFIELD_PREP(GCK_SRC_SEL, 0x0) |\n+\t\t\t/* Divisor - 1 */\n+\t\t\tFIELD_PREP(GCK_PRESCALER, (div - 1)));\n+\n+\treturn 0;\n+}\n+\n+static ulong lan966x_clk_get_rate(struct clk *clk)\n+{\n+\tstruct lan966x_clk *gck = dev_get_priv(clk->dev);\n+\tunsigned long parent_rate = gck->parent_rate;\n+\tu32 div, val;\n+\n+\tif (clk->id >= gck->clk_cnt)\n+\t\treturn -ENODEV;\n+\n+\tval = readl(lan966x_clk_ctlreg(gck, clk->id));\n+\n+\tdiv = 1 + FIELD_GET(GCK_PRESCALER, val);\n+\n+\treturn parent_rate / div;\n+}\n+\n+static int lan966x_clk_enable(struct clk *clk)\n+{\n+\tstruct lan966x_clk *gck = dev_get_priv(clk->dev);\n+\n+\tif (clk->id >= gck->clk_cnt) {\n+\t\t/* If there are no gate clock then this is not allowed */\n+\t\tif (gck->gate == NULL)\n+\t\t\treturn -ENODEV;\n+\n+\t\tif (clk->id >= gck->clk_cnt + gck->clk_gate_cnt)\n+\t\t\treturn -ENODEV;\n+\n+\t\tsetbits_le32(gck->gate,\n+\t\t\t BIT(gck->clk_gate_desc[clk->id - gck->clk_cnt].bit_idx));\n+\n+\t\treturn 0;\n+\t}\n+\n+\tsetbits_le32(lan966x_clk_ctlreg(gck, clk->id), GCK_ENA);\n+\n+\treturn 0;\n+}\n+\n+static int lan966x_clk_disable(struct clk *clk)\n+{\n+\tstruct lan966x_clk *gck = dev_get_priv(clk->dev);\n+\n+\tif (clk->id >= gck->clk_cnt) {\n+\t\t/* If there are no gate clock then this is not allowed */\n+\t\tif (gck->gate == NULL)\n+\t\t\treturn -ENODEV;\n+\n+\t\tif (clk->id >= gck->clk_cnt + gck->clk_gate_cnt)\n+\t\t\treturn -ENODEV;\n+\n+\t\tclrbits_le32(gck->gate, BIT(gck->clk_gate_desc[clk->id - gck->clk_cnt].bit_idx));\n+\n+\t\treturn 0;\n+\t}\n+\n+\tclrbits_le32(lan966x_clk_ctlreg(gck, clk->id), GCK_ENA);\n+\n+\treturn 0;\n+}\n+\n+static int lan966x_clk_probe(struct udevice *dev)\n+{\n+\tstruct lan966x_clk *priv = dev_get_priv(dev);\n+\tstruct lan966x_driver_data *data;\n+\n+\tpriv->base = dev_remap_addr(dev);\n+\tif (IS_ERR(priv->base))\n+\t\treturn PTR_ERR(priv->base);\n+\n+\tpriv->gate = dev_remap_addr_index(dev, 1);\n+\n+\t/* Get clock count for target device */\n+\tdata = (struct lan966x_driver_data*)dev_get_driver_data(dev);\n+\tpriv->clk_cnt = data->clk_cnt;\n+\tpriv->clk_gate_cnt = data->clk_gate_cnt;\n+\tpriv->clk_gate_desc = data->clk_gate_desc;\n+\tpriv->parent_rate = data->parent_rate;\n+\n+\treturn 0;\n+}\n+\n+static struct clk_ops lan966x_clk_ops = {\n+\t.disable\t= lan966x_clk_disable,\n+\t.enable\t\t= lan966x_clk_enable,\n+\t.get_rate\t= lan966x_clk_get_rate,\n+\t.set_rate\t= lan966x_clk_set_rate,\n+};\n+\n+static const struct udevice_id lan966x_clk_ids[] = {\n+\t{ .compatible = \"microchip,lan966x-gck\", .data = (unsigned long)&lan966x_data },\n+\t{ .compatible = \"microchip,lan9691-gck\", .data = (unsigned long)&lan969x_data },\n+\t{ }\n+};\n+\n+U_BOOT_DRIVER(lan966x_clk) = {\n+\t.name\t\t= \"lan966x_clk\",\n+\t.id\t\t= UCLASS_CLK,\n+\t.of_match\t= lan966x_clk_ids,\n+\t.priv_auto\t= sizeof(struct lan966x_clk),\n+\t.ops\t\t= &lan966x_clk_ops,\n+\t.probe\t\t= lan966x_clk_probe,\n+};\n", "prefixes": [ "03/14" ] }