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GET /api/patches/2216397/?format=api
{ "id": 2216397, "url": "http://patchwork.ozlabs.org/api/patches/2216397/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-2-robert.marko@sartura.hr/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326112830.313874-2-robert.marko@sartura.hr>", "list_archive_url": null, "date": "2026-03-26T11:26:43", "name": "[02/14] pinctrl: add Microchip LAN969x driver", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5ab32a14d4d7b324b4889e5255f96a5ff486ae4f", "submitter": { "id": 78207, "url": "http://patchwork.ozlabs.org/api/people/78207/?format=api", "name": "Robert Marko", "email": "robert.marko@sartura.hr" }, "delegate": { "id": 3651, "url": "http://patchwork.ozlabs.org/api/users/3651/?format=api", "username": "trini", "first_name": "Tom", "last_name": "Rini", "email": "trini@ti.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260326112830.313874-2-robert.marko@sartura.hr/mbox/", "series": [ { "id": 497572, "url": "http://patchwork.ozlabs.org/api/series/497572/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497572", "date": "2026-03-26T11:26:42", "name": "[01/14] serial: atmel-usart: allow selecting from ARCH_MICROCHIPSW", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497572/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216397/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216397/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.a=rsa-sha256\n header.s=sartura header.b=jk8yawMd;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=2a01:238:438b:c500:173d:9f52:ddab:ee01; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sartura.hr header.i=@sartura.hr header.b=\"jk8yawMd\";\n\tdkim-atps=neutral", "phobos.denx.de;\n dmarc=pass (p=reject dis=none) header.from=sartura.hr", "phobos.denx.de;\n spf=pass smtp.mailfrom=robert.marko@sartura.hr" ], "Received": [ "from phobos.denx.de (phobos.denx.de\n [IPv6:2a01:238:438b:c500:173d:9f52:ddab:ee01])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhM4416Mjz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 22:29:08 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 7DFD583EB3;\n\tThu, 26 Mar 2026 12:28:56 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id 5002683F00; Thu, 26 Mar 2026 12:28:55 +0100 (CET)", "from mail-dl1-x122f.google.com (mail-dl1-x122f.google.com\n [IPv6:2607:f8b0:4864:20::122f])\n (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id 74A3983EAC\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 12:28:52 +0100 (CET)", "by mail-dl1-x122f.google.com with SMTP id\n a92af1059eb24-1274204434bso1494587c88.1\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 04:28:52 -0700 (PDT)", "from fedora (cpe-109-60-83-68.zg3.cable.xnet.hr. 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The driver supports setting\n \t pins on start-up and changing the GPIO attributes.\n \n+config PINCTRL_LAN969X\n+\tbool \"Microchip LAN969X pinctrl driver\"\n+\tdepends on DM && TARGET_LAN969X\n+\tselect PINCONF\n+\tselect REGMAP\n+\thelp\n+\t This option is to enable the LAN969X pinctrl driver.\n+\n config PINCTRL_PIC32\n \tbool \"Microchip PIC32 pin-control and pin-mux driver\"\n \tdepends on DM && MACH_PIC32\ndiff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile\nindex 33ff7b95ef2..d0c46268673 100644\n--- a/drivers/pinctrl/Makefile\n+++ b/drivers/pinctrl/Makefile\n@@ -12,6 +12,7 @@ obj-$(CONFIG_$(PHASE_)PINCTRL_ROCKCHIP)\t+= rockchip/\n obj-$(CONFIG_ARCH_ASPEED) += aspeed/\n obj-$(CONFIG_ARCH_ATH79) += ath79/\n obj-$(CONFIG_PINCTRL_INTEL) += intel/\n+obj-$(CONFIG_PINCTRL_LAN969X) += pinctrl-lan969x.o\n obj-$(CONFIG_ARCH_MTMIPS) += mtmips/\n obj-$(CONFIG_ARCH_NPCM) += nuvoton/\n obj-$(CONFIG_PINCTRL_QCOM) += qcom/\ndiff --git a/drivers/pinctrl/pinctrl-lan969x.c b/drivers/pinctrl/pinctrl-lan969x.c\nnew file mode 100644\nindex 00000000000..70e66193ddd\n--- /dev/null\n+++ b/drivers/pinctrl/pinctrl-lan969x.c\n@@ -0,0 +1,582 @@\n+// SPDX-License-Identifier: (GPL-2.0 OR MIT)\n+\n+#include <asm/gpio.h>\n+#include <config.h>\n+#include <dm.h>\n+#include <dm/devres.h>\n+#include <dm/device-internal.h>\n+#include <dm/pinctrl.h>\n+#include <errno.h>\n+#include <fdtdec.h>\n+#include <linux/bitfield.h>\n+#include <linux/io.h>\n+#include <linux/types.h>\n+#include <regmap.h>\n+\n+/* GPIO standard registers */\n+#define LAN969X_FUNC_PER_PIN\t8\n+\n+/* GPIO standard registers */\n+#define LAN969X_GPIO_OUT_SET\t0x0\n+#define LAN969X_GPIO_OUT_CLR\t0x4\n+#define LAN969X_GPIO_OUT\t0x8\n+#define LAN969X_GPIO_IN\t\t0xc\n+#define LAN969X_GPIO_OE\t\t0x10\n+#define LAN969X_GPIO_INTR\t0x14\n+#define LAN969X_GPIO_INTR_ENA\t0x18\n+#define LAN969X_GPIO_INTR_IDENT\t0x1c\n+#define LAN969X_GPIO_ALT0\t0x20\n+#define LAN969X_GPIO_ALT1\t0x24\n+#define LAN969X_GPIO_ALT2\t0x28\n+#define LAN969X_GPIO_SD_MAP\t0x2c\n+\n+enum {\n+\tFUNC_CAN0_a,\n+\tFUNC_CAN0_b,\n+\tFUNC_CAN1,\n+\tFUNC_CLKMON,\n+\tFUNC_NONE,\n+\tFUNC_FAN,\n+\tFUNC_FC,\n+\tFUNC_FC_SHRD,\n+\tFUNC_FUSA,\n+\tFUNC_GPIO,\n+\tFUNC_IRQ0,\n+\tFUNC_IRQ1,\n+\tFUNC_IRQ3,\n+\tFUNC_IRQ4,\n+\tFUNC_MIIM,\n+\tFUNC_MIIM_Sa,\n+\tFUNC_MIIM_IRQ,\n+\tFUNC_PCIE_PERST,\n+\tFUNC_PTPSYNC_0,\n+\tFUNC_PTPSYNC_1,\n+\tFUNC_PTPSYNC_2,\n+\tFUNC_PTPSYNC_3,\n+\tFUNC_PTPSYNC_4,\n+\tFUNC_PTPSYNC_5,\n+\tFUNC_PTPSYNC_6,\n+\tFUNC_PTPSYNC_7,\n+\tFUNC_QSPI1,\n+\tFUNC_R,\n+\tFUNC_SD,\n+\tFUNC_SFP_SD,\n+\tFUNC_SGPIO_a,\n+\tFUNC_SYNCE,\n+\tFUNC_TWI,\n+\tFUNC_USB_POWER,\n+\tFUNC_USB2PHY_RST,\n+\tFUNC_USB_OVER_DETECT,\n+\tFUNC_USB_ULPI,\n+\tFUNC_EMMC_SD,\n+\tFUNC_MAX\n+};\n+\n+static const char *const lan969x_function_names[FUNC_MAX] = {\n+\t[FUNC_CAN0_a]\t\t= \"can0_a\",\n+\t[FUNC_CAN0_b]\t\t= \"can0_b\",\n+\t[FUNC_CAN1]\t\t= \"can1\",\n+\t[FUNC_CLKMON]\t\t= \"clkmon\",\n+\t[FUNC_NONE]\t\t= \"none\",\n+\t[FUNC_FAN]\t\t= \"fan\",\n+\t[FUNC_FC]\t\t= \"fc\",\n+\t[FUNC_FC_SHRD]\t\t= \"fc_shrd\",\n+\t[FUNC_FUSA]\t\t= \"fusa\",\n+\t[FUNC_GPIO]\t\t= \"gpio\",\n+\t[FUNC_IRQ0]\t\t= \"irq0\",\n+\t[FUNC_IRQ1]\t\t= \"irq1\",\n+\t[FUNC_IRQ3]\t\t= \"irq3\",\n+\t[FUNC_IRQ4]\t\t= \"irq4\",\n+\t[FUNC_MIIM]\t\t= \"miim\",\n+\t[FUNC_MIIM_Sa]\t\t= \"miim_slave_a\",\n+\t[FUNC_MIIM_IRQ]\t\t= \"miim_irq\",\n+\t[FUNC_PCIE_PERST]\t= \"pcie_perst\",\n+\t[FUNC_PTPSYNC_0]\t= \"ptpsync_0\",\n+\t[FUNC_PTPSYNC_1]\t= \"ptpsync_1\",\n+\t[FUNC_PTPSYNC_2]\t= \"ptpsync_2\",\n+\t[FUNC_PTPSYNC_3]\t= \"ptpsync_3\",\n+\t[FUNC_PTPSYNC_4]\t= \"ptpsync_4\",\n+\t[FUNC_PTPSYNC_5]\t= \"ptpsync_5\",\n+\t[FUNC_PTPSYNC_6]\t= \"ptpsync_6\",\n+\t[FUNC_PTPSYNC_7]\t= \"ptpsync_7\",\n+\t[FUNC_QSPI1]\t\t= \"qspi1\",\n+\t[FUNC_R]\t\t= \"reserved\",\n+\t[FUNC_SD]\t\t= \"sd\",\n+\t[FUNC_SFP_SD]\t\t= \"sfp_sd\",\n+\t[FUNC_SGPIO_a]\t\t= \"sgpio_a\",\n+\t[FUNC_SYNCE]\t\t= \"synce\",\n+\t[FUNC_TWI]\t\t= \"twi\",\n+\t[FUNC_USB_POWER]\t= \"usb_power\",\n+\t[FUNC_USB2PHY_RST]\t= \"usb2phy_rst\",\n+\t[FUNC_USB_OVER_DETECT]\t= \"usb_over_detect\",\n+\t[FUNC_USB_ULPI]\t\t= \"usb_ulpi\",\n+\t[FUNC_EMMC_SD]\t\t= \"emmc_sd\",\n+};\n+\n+struct lan969x_pin_caps {\n+\tunsigned int pin;\n+\tunsigned char functions[LAN969X_FUNC_PER_PIN];\n+};\n+\n+struct lan969x_pin_data {\n+\tconst char *name;\n+\tstruct lan969x_pin_caps *drv_data;\n+};\n+\n+#define LAN969X_P(p, f0, f1, f2, f3, f4, f5, f6, f7) \\\n+static struct lan969x_pin_caps lan969x_pin_##p = { \\\n+\t.pin = p, \\\n+\t.functions = { \\\n+\t\tFUNC_##f0, FUNC_##f1, FUNC_##f2, \\\n+\t\tFUNC_##f3, FUNC_##f4, FUNC_##f5, \\\n+\t\tFUNC_##f6, FUNC_##f7 \\\n+\t}, \\\n+}\n+\n+#define REG(r, info, p) ((r) * (info)->stride + (4 * ((p) / 32)))\n+\n+struct lan969x_pmx_func {\n+\tconst char **groups;\n+\tunsigned int ngroups;\n+};\n+\n+struct lan969x_pinctrl {\n+\tstruct udevice *dev;\n+\tstruct pinctrl_dev *pctl;\n+\tstruct regmap *map;\n+\tvoid __iomem *pincfg;\n+\tstruct lan969x_pmx_func *func;\n+\tint num_func;\n+\tconst struct lan969x_pin_data *lan969x_pins;\n+\tint num_pins;\n+\tconst char * const *function_names;\n+\tconst unsigned long *lan969x_gpios;\n+\tu8 stride;\n+};\n+\n+/* Pinmuxing table taken from data sheet */\n+/* Pin FUNC0 FUNC1 FUNC2 FUNC3 FUNC4 FUNC5 FUNC6 FUNC7 */\n+LAN969X_P(0, GPIO, IRQ0, FC_SHRD, PCIE_PERST, NONE, NONE, NONE, R);\n+LAN969X_P(1, GPIO, IRQ1, FC_SHRD, USB_POWER, NONE, NONE, NONE, R);\n+LAN969X_P(2, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(3, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(4, GPIO, FC, NONE, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(5, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);\n+LAN969X_P(6, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);\n+LAN969X_P(7, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);\n+LAN969X_P(8, GPIO, SGPIO_a, NONE, CLKMON, NONE, NONE, NONE, R);\n+LAN969X_P(9, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);\n+LAN969X_P(10, GPIO, MIIM, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);\n+LAN969X_P(11, GPIO, MIIM_IRQ, MIIM_Sa, CLKMON, NONE, NONE, NONE, R);\n+LAN969X_P(12, GPIO, IRQ3, FC_SHRD, USB2PHY_RST, NONE, NONE, NONE, R);\n+LAN969X_P(13, GPIO, IRQ4, FC_SHRD, USB_OVER_DETECT, NONE, NONE, NONE, R);\n+LAN969X_P(14, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);\n+LAN969X_P(15, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);\n+LAN969X_P(16, GPIO, EMMC_SD, QSPI1, FC, NONE, NONE, NONE, R);\n+LAN969X_P(17, GPIO, EMMC_SD, QSPI1, PTPSYNC_0, USB_POWER, NONE, NONE, R);\n+LAN969X_P(18, GPIO, EMMC_SD, QSPI1, PTPSYNC_1, USB2PHY_RST, NONE, NONE, R);\n+LAN969X_P(19, GPIO, EMMC_SD, QSPI1, PTPSYNC_2, USB_OVER_DETECT, NONE, NONE, R);\n+LAN969X_P(20, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);\n+LAN969X_P(21, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);\n+LAN969X_P(22, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);\n+LAN969X_P(23, GPIO, EMMC_SD, NONE, FC_SHRD, NONE, NONE, NONE, R);\n+LAN969X_P(24, GPIO, EMMC_SD, NONE, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(25, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R);\n+LAN969X_P(26, GPIO, FAN, FUSA, CAN0_a, QSPI1, NONE, NONE, R);\n+LAN969X_P(27, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R);\n+LAN969X_P(28, GPIO, SYNCE, FC, MIIM, QSPI1, NONE, NONE, R);\n+LAN969X_P(29, GPIO, SYNCE, FC, MIIM_IRQ, QSPI1, NONE, NONE, R);\n+LAN969X_P(30, GPIO, PTPSYNC_0, USB_ULPI, FC_SHRD, QSPI1, NONE, NONE, R);\n+LAN969X_P(31, GPIO, PTPSYNC_1, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);\n+LAN969X_P(32, GPIO, PTPSYNC_2, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);\n+LAN969X_P(33, GPIO, SD, USB_ULPI, FC_SHRD, NONE, NONE, NONE, R);\n+LAN969X_P(34, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R);\n+LAN969X_P(35, GPIO, SD, USB_ULPI, CAN1, FC_SHRD, NONE, NONE, R);\n+LAN969X_P(36, GPIO, SD, USB_ULPI, PCIE_PERST, FC_SHRD, NONE, NONE, R);\n+LAN969X_P(37, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R);\n+LAN969X_P(38, GPIO, SD, USB_ULPI, CAN0_b, NONE, NONE, NONE, R);\n+LAN969X_P(39, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R);\n+LAN969X_P(40, GPIO, SD, USB_ULPI, MIIM, NONE, NONE, NONE, R);\n+LAN969X_P(41, GPIO, SD, USB_ULPI, MIIM_IRQ, NONE, NONE, NONE, R);\n+LAN969X_P(42, GPIO, PTPSYNC_3, CAN1, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(43, GPIO, PTPSYNC_4, CAN1, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(44, GPIO, PTPSYNC_5, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(45, GPIO, PTPSYNC_6, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(46, GPIO, PTPSYNC_7, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(47, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(48, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(49, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(50, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(51, GPIO, NONE, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(52, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(53, GPIO, FAN, SFP_SD, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(54, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(55, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(56, GPIO, SYNCE, FC, NONE, NONE, NONE, NONE, R);\n+LAN969X_P(57, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_3, NONE, NONE, R);\n+LAN969X_P(58, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_4, NONE, NONE, R);\n+LAN969X_P(59, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_5, NONE, NONE, R);\n+LAN969X_P(60, GPIO, SFP_SD, FC_SHRD, TWI, PTPSYNC_6, NONE, NONE, R);\n+LAN969X_P(61, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R);\n+LAN969X_P(62, GPIO, MIIM, FC_SHRD, TWI, NONE, NONE, NONE, R);\n+LAN969X_P(63, GPIO, MIIM_IRQ, FC_SHRD, TWI, NONE, NONE, NONE, R);\n+LAN969X_P(64, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);\n+LAN969X_P(65, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);\n+LAN969X_P(66, GPIO, FC, FC_SHRD, TWI, NONE, NONE, NONE, R);\n+\n+#define LAN969X_PIN(n) { \\\n+\t.name = \"GPIO_\"#n, \\\n+\t.drv_data = &lan969x_pin_##n \\\n+}\n+\n+static const struct lan969x_pin_data lan969x_pins[] = {\n+\tLAN969X_PIN(0),\n+\tLAN969X_PIN(1),\n+\tLAN969X_PIN(2),\n+\tLAN969X_PIN(3),\n+\tLAN969X_PIN(4),\n+\tLAN969X_PIN(5),\n+\tLAN969X_PIN(6),\n+\tLAN969X_PIN(7),\n+\tLAN969X_PIN(8),\n+\tLAN969X_PIN(9),\n+\tLAN969X_PIN(10),\n+\tLAN969X_PIN(11),\n+\tLAN969X_PIN(12),\n+\tLAN969X_PIN(13),\n+\tLAN969X_PIN(14),\n+\tLAN969X_PIN(15),\n+\tLAN969X_PIN(16),\n+\tLAN969X_PIN(17),\n+\tLAN969X_PIN(18),\n+\tLAN969X_PIN(19),\n+\tLAN969X_PIN(20),\n+\tLAN969X_PIN(21),\n+\tLAN969X_PIN(22),\n+\tLAN969X_PIN(23),\n+\tLAN969X_PIN(24),\n+\tLAN969X_PIN(25),\n+\tLAN969X_PIN(26),\n+\tLAN969X_PIN(27),\n+\tLAN969X_PIN(28),\n+\tLAN969X_PIN(29),\n+\tLAN969X_PIN(30),\n+\tLAN969X_PIN(31),\n+\tLAN969X_PIN(32),\n+\tLAN969X_PIN(33),\n+\tLAN969X_PIN(34),\n+\tLAN969X_PIN(35),\n+\tLAN969X_PIN(36),\n+\tLAN969X_PIN(37),\n+\tLAN969X_PIN(38),\n+\tLAN969X_PIN(39),\n+\tLAN969X_PIN(40),\n+\tLAN969X_PIN(41),\n+\tLAN969X_PIN(42),\n+\tLAN969X_PIN(43),\n+\tLAN969X_PIN(44),\n+\tLAN969X_PIN(45),\n+\tLAN969X_PIN(46),\n+\tLAN969X_PIN(47),\n+\tLAN969X_PIN(48),\n+\tLAN969X_PIN(49),\n+\tLAN969X_PIN(50),\n+\tLAN969X_PIN(51),\n+\tLAN969X_PIN(52),\n+\tLAN969X_PIN(53),\n+\tLAN969X_PIN(54),\n+\tLAN969X_PIN(55),\n+\tLAN969X_PIN(56),\n+\tLAN969X_PIN(57),\n+\tLAN969X_PIN(58),\n+\tLAN969X_PIN(59),\n+\tLAN969X_PIN(60),\n+\tLAN969X_PIN(61),\n+\tLAN969X_PIN(62),\n+\tLAN969X_PIN(63),\n+\tLAN969X_PIN(64),\n+\tLAN969X_PIN(65),\n+\tLAN969X_PIN(66),\n+};\n+\n+static int lan969x_gpio_probe(struct udevice *dev)\n+{\n+\tstruct gpio_dev_priv *uc_priv;\n+\n+\tuc_priv = dev_get_uclass_priv(dev);\n+\tuc_priv->bank_name = \"lan969x-gpio\";\n+\tuc_priv->gpio_count = ARRAY_SIZE(lan969x_pins);\n+\n+\treturn 0;\n+}\n+\n+static int lan969x_gpio_get(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev->parent);\n+\tunsigned int val;\n+\n+\tregmap_read(info->map, REG(LAN969X_GPIO_IN, info, offset), &val);\n+\n+\treturn !!(val & BIT(offset % 32));\n+}\n+\n+static int lan969x_gpio_set(struct udevice *dev, unsigned int offset, int value)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev->parent);\n+\n+\tif (value)\n+\t\tregmap_write(info->map, REG(LAN969X_GPIO_OUT_SET, info, offset),\n+\t\t\t BIT(offset % 32));\n+\telse\n+\t\tregmap_write(info->map, REG(LAN969X_GPIO_OUT_CLR, info, offset),\n+\t\t\t BIT(offset % 32));\n+\n+\treturn 0;\n+}\n+\n+static int lan969x_gpio_get_direction(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev->parent);\n+\tunsigned int val;\n+\n+\tregmap_read(info->map, REG(LAN969X_GPIO_OE, info, offset), &val);\n+\n+\tif (val & BIT(offset % 32))\n+\t\treturn GPIOF_OUTPUT;\n+\n+\treturn GPIOF_INPUT;\n+}\n+\n+static int lan969x_gpio_direction_input(struct udevice *dev, unsigned int offset)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev->parent);\n+\n+\tregmap_write(info->map, REG(LAN969X_GPIO_OE, info, offset),\n+\t\t ~BIT(offset % 32));\n+\n+\treturn 0;\n+}\n+\n+static int lan969x_gpio_direction_output(struct udevice *dev,\n+\t\t\t\t\t unsigned int offset, int value)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev->parent);\n+\n+\tregmap_write(info->map, REG(LAN969X_GPIO_OE, info, offset),\n+\t\t BIT(offset % 32));\n+\n+\treturn lan969x_gpio_set(dev, offset, value);\n+}\n+\n+const struct dm_gpio_ops lan969x_gpio_ops = {\n+\t.set_value = lan969x_gpio_set,\n+\t.get_value = lan969x_gpio_get,\n+\t.get_function = lan969x_gpio_get_direction,\n+\t.direction_input = lan969x_gpio_direction_input,\n+\t.direction_output = lan969x_gpio_direction_output,\n+};\n+\n+static int lan969x_pctl_get_groups_count(struct udevice *dev)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev);\n+\n+\treturn info->num_pins;\n+}\n+\n+static const char *lan969x_pctl_get_group_name(struct udevice *dev,\n+\t\t\t\t\t unsigned int group)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev);\n+\n+\treturn info->lan969x_pins[group].name;\n+}\n+\n+static int lan969x_get_functions_count(struct udevice *dev)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev);\n+\n+\treturn info->num_func;\n+}\n+\n+static const char *lan969x_get_function_name(struct udevice *dev,\n+\t\t\t\t\t unsigned int function)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev);\n+\n+\treturn info->function_names[function];\n+}\n+\n+static int lan969x_pin_function_idx(unsigned int pin, unsigned int function,\n+\t\t\t\t const struct lan969x_pin_data *lan969x_pins)\n+{\n+\tstruct lan969x_pin_caps *p = lan969x_pins[pin].drv_data;\n+\tint i;\n+\n+\tfor (i = 0; i < LAN969X_FUNC_PER_PIN; i++) {\n+\t\tif (function == p->functions[i])\n+\t\t\treturn i;\n+\t}\n+\n+\treturn -1;\n+}\n+\n+#define REG_ALT(msb, info, p) (LAN969X_GPIO_ALT0 * (info)->stride + 4 * ((msb) + ((info)->stride * ((p) / 32))))\n+\n+static int lan969x_pinmux_set_mux(struct udevice *dev,\n+\t\t\t\t unsigned int pin_selector, unsigned int selector)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev);\n+\tstruct lan969x_pin_caps *pin = info->lan969x_pins[pin_selector].drv_data;\n+\tunsigned int p = pin->pin % 32;\n+\tint f;\n+\n+\tf = lan969x_pin_function_idx(pin_selector, selector, info->lan969x_pins);\n+\tif (f < 0)\n+\t\treturn -EINVAL;\n+\n+\t/*\n+\t * f is encoded on two bits.\n+\t * bit 0 of f goes in BIT(pin) of ALT[0], bit 1 of f goes in BIT(pin) of\n+\t * ALT[1], bit 2 of f goes in BIT(pin) of ALT[2]\n+\t * This is racy because both registers can't be updated at the same time\n+\t * but it doesn't matter much for now.\n+\t * Note: ALT0/ALT1/ALT2 are organized specially for 78 gpio targets\n+\t */\n+\tregmap_update_bits(info->map, REG_ALT(0, info, pin->pin),\n+\t\t\t BIT(p), f << p);\n+\tregmap_update_bits(info->map, REG_ALT(1, info, pin->pin),\n+\t\t\t BIT(p), (f >> 1) << p);\n+\tregmap_update_bits(info->map, REG_ALT(2, info, pin->pin),\n+\t\t\t BIT(p), (f >> 2) << p);\n+\n+\treturn 0;\n+}\n+\n+/* Non-constant mask variant of FIELD_GET */\n+#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask) - 1))\n+\n+static int lan969x_get_pin_muxing(struct udevice *dev, unsigned int selector,\n+\t\t\t\t char *buf, int size)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev);\n+\tstruct lan969x_pin_caps *pin = info->lan969x_pins[selector].drv_data;\n+\tunsigned int alt0, alt1, alt2, function = 0;\n+\n+\tregmap_read(info->map, REG_ALT(0, info, pin->pin), &alt0);\n+\tregmap_read(info->map, REG_ALT(1, info, pin->pin), &alt1);\n+\tregmap_read(info->map, REG_ALT(2, info, pin->pin), &alt2);\n+\n+\tfunction |= FIELD_PREP(BIT(0), field_get(BIT(pin->pin), alt0));\n+\tfunction |= FIELD_PREP(BIT(1), field_get(BIT(pin->pin), alt1));\n+\tfunction |= FIELD_PREP(BIT(2), field_get(BIT(pin->pin), alt2));\n+\n+\tsnprintf(buf, size, \"%s\", lan969x_get_function_name(dev, pin->functions[function]));\n+\treturn 0;\n+}\n+\n+#if CONFIG_IS_ENABLED(PINCONF)\n+static const struct pinconf_param lan969x_pinconf_params[] = {\n+\t{ \"bias-disable\", PIN_CONFIG_BIAS_DISABLE, 0 },\n+\t{ \"bias-pull-up\", PIN_CONFIG_BIAS_PULL_UP, 1 },\n+\t{ \"bias-pull-down\", PIN_CONFIG_BIAS_PULL_DOWN, 0 },\n+\t{ \"drive-strength\", PIN_CONFIG_DRIVE_STRENGTH, 0 },\n+};\n+\n+static int lan969x_pinconf_set(struct udevice *dev, unsigned int pin,\n+\t\t\t unsigned int param, unsigned int arg)\n+{\n+\tstruct lan969x_pinctrl *info = dev_get_priv(dev);\n+\tunsigned int val;\n+\tint err = 0;\n+\n+\tif (info->pincfg == NULL)\n+\t\treturn err;\n+\n+\tswitch (param) {\n+\tcase PIN_CONFIG_BIAS_DISABLE:\n+\tcase PIN_CONFIG_BIAS_PULL_UP:\n+\tcase PIN_CONFIG_BIAS_PULL_DOWN:\n+\t\tval = readl(info->pincfg + (pin * 4));\n+\t\tval &= ~(BIT(3) | BIT(2));\n+\t\tval |= (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :\n+\t\t (param == PIN_CONFIG_BIAS_PULL_UP) ? BIT(3) : BIT(2);\n+\t\twritel(val, info->pincfg + (pin * 4));\n+\t\tbreak;\n+\tcase PIN_CONFIG_DRIVE_STRENGTH:\n+\t\tif (arg <= 3) {\n+\t\t\tval = readl(info->pincfg + (pin * 4));\n+\t\t\tval &= ~GENMASK(1, 0);\n+\t\t\tval |= arg;\n+\t\t\twritel(val, info->pincfg + (pin * 4));\n+\t\t} else {\n+\t\t\terr = -EINVAL;\n+\t\t}\n+\t\tbreak;\n+\tdefault:\n+\t\terr = -ENOTSUPP;\n+\t}\n+\n+\treturn err;\n+}\n+#endif\n+\n+const struct pinctrl_ops lan969x_pinctrl_ops = {\n+\t.get_pins_count = lan969x_pctl_get_groups_count,\n+\t.get_pin_name = lan969x_pctl_get_group_name,\n+\t.get_pin_muxing = lan969x_get_pin_muxing,\n+\t.get_functions_count = lan969x_get_functions_count,\n+\t.get_function_name = lan969x_get_function_name,\n+\t.pinmux_set = lan969x_pinmux_set_mux,\n+\t.set_state = pinctrl_generic_set_state,\n+#if CONFIG_IS_ENABLED(PINCONF)\n+\t.pinconf_num_params = ARRAY_SIZE(lan969x_pinconf_params),\n+\t.pinconf_params = lan969x_pinconf_params,\n+\t.pinconf_set = lan969x_pinconf_set,\n+#endif\n+};\n+\n+static struct driver lan969x_gpio_driver = {\n+\t.name\t= \"lan969x-gpio\",\n+\t.id\t= UCLASS_GPIO,\n+\t.probe\t= lan969x_gpio_probe,\n+\t.ops\t= &lan969x_gpio_ops,\n+};\n+\n+int lan969x_pinctrl_probe(struct udevice *dev)\n+{\n+\tstruct lan969x_pinctrl *priv = dev_get_priv(dev);\n+\tint ret;\n+\n+\tret = regmap_init_mem(dev_ofnode(dev), &priv->map);\n+\tif (ret)\n+\t\treturn -EINVAL;\n+\n+\tpriv->pincfg = dev_remap_addr_index(dev, 1);\n+\n+\tpriv->func = devm_kzalloc(dev, FUNC_MAX * sizeof(struct lan969x_pmx_func), GFP_KERNEL);\n+\tpriv->num_func = FUNC_MAX;\n+\tpriv->function_names = lan969x_function_names;\n+\n+\tpriv->lan969x_pins = lan969x_pins;\n+\tpriv->num_pins = ARRAY_SIZE(lan969x_pins);\n+\tpriv->stride = 1 + (priv->num_pins - 1) / 32;\n+\n+\tret = device_bind(dev, &lan969x_gpio_driver, \"lan969x-gpio\", NULL,\n+\t\t\t dev_ofnode(dev), NULL);\n+\n+\treturn ret;\n+}\n+\n+static const struct udevice_id lan969x_pinctrl_of_match[] = {\n+\t{.compatible = \"microchip,lan9691-pinctrl\"},\n+\t{},\n+};\n+\n+U_BOOT_DRIVER(lan969x_pinctrl) = {\n+\t.name = \"lan969x-pinctrl\",\n+\t.id = UCLASS_PINCTRL,\n+\t.of_match = of_match_ptr(lan969x_pinctrl_of_match),\n+\t.probe = lan969x_pinctrl_probe,\n+\t.priv_auto = sizeof(struct lan969x_pinctrl),\n+\t.ops = &lan969x_pinctrl_ops,\n+};\n", "prefixes": [ "02/14" ] }