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GET /api/patches/2216383/?format=api
{ "id": 2216383, "url": "http://patchwork.ozlabs.org/api/patches/2216383/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260326110948.68908-5-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326110948.68908-5-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-26T11:09:41", "name": "[v4,04/10] dmaengine: tegra: Make reset control optional", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "47cd0af4b6a4c1b8bbcc43813a962dff5dbceca4", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260326110948.68908-5-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 497568, "url": "http://patchwork.ozlabs.org/api/series/497568/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497568", "date": "2026-03-26T11:09:37", "name": "Add GPCDMA support in Tegra264", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497568/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216383/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216383/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13287-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=oQf5XJJG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>, Frank Li <Frank.Li@nxp.com>", "Subject": "[PATCH v4 04/10] dmaengine: tegra: Make reset control optional", "Date": "Thu, 26 Mar 2026 16:39:41 +0530", "Message-ID": "<20260326110948.68908-5-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260326110948.68908-1-akhilrajeev@nvidia.com>", "References": "<20260326110948.68908-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF000397AF:EE_|IA1PR12MB8287:EE_", "X-MS-Office365-Filtering-Correlation-Id": "721ba7b3-8329-4461-3323-08de8b285e12", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|82310400026|1800799024|36860700016|7416014|376014|921020|18002099003|56012099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\tKUBJc71OxIP6fSRqrFffGWxQCN/QVVdH6dLqGdcvzDiMXBXTzQV9Xv1WHuNt7p2YlOHNrHBe1eMxyWi3+Qmmd6gwjTJdTgsCgJzsm8pzKHMDSNG7TC4verUhzBHG4714Gz5KIpnF8KY76XiV5uF/b512JyOHRIXX8kwvJF6Z8Q/qnGE325F2RhsdR70Lfq3FAGIAz2RmiV4ELSXxhky8+tWm7zfIZqs4IcjG5VfX1bjknkonwgI8e7Ov1ByVmSdwOQBW8jyoWo+imbA7jIn/5sFnyUZqITRfbYez9q7isEwJRgaUDzd/xfADklpMJvl3HKto0qWnw0/eKbjowi60HekC0D3a1qZscbZfq2HFn0IGGbbt4F4fdyhRVV9wLvfGnh4ZHms5IIy8RPivwnYu2S0KTKHUwnT3O7LHlVgImVWbdJy/aDs2EbxyMz+505M9ma5JrDlLbUadeHAE23gy7YHro972wMiB839qcEhghPDyi3raqznUQvrZyXp4FaSv926f/wrX5VvcpfzoyRKs4EXWsOckNilQVZ2DXzF6zpwRiuhW/5QHMk27J1l561NX1VTIyb96Yt9Cr2USFKr6NbbnLiDoN8+BEjOTBjJ1qGYrpyn9jfHe65sU/P4G43lDLH6QmvbRa42OTkF+330QvC8OqjlgsVVFHmqtBeE6g6LNFcFpC24rNavdP4qipIoOLYt0A/heXa0E7ZqaMf2pD+oQyXgZyJ1SitD1V3InbIBZX5i09GKX+azOmP5qhwV/IxnhO0+uYFsc+MEc15UH9lt8r/JdPqVEtlwLiyM/XEBVJW4owKjIqySeJwzhU4q3", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(36860700016)(7416014)(376014)(921020)(18002099003)(56012099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tizi/2MYoKGw67dG+Q8/YLqwVveMk6rA+amG8TanDYwYMY82blM7dPK4Ho7f3LygVXVkyrHXvUZCrDSqwFayzS3LFmAF8z+wN+JMpTvTHrWuyiUBqD52mrJx/YVIQVVets5GvB8XcgvqgRMadPwnBETMAPZYlGbNLmdSgQfnLOPJ3Nx8K79Z5coyW7pf2ZFWKYGhD4Br/smbhzf3JixVE1/HRytCXuM+lPwp72n8967VAiJm0KeyBurNr6C33r4B7ofNSmc8mAl5jvyIu3KlBrMNwZtYo3iZqEC324lgsCE9ppX6lBUfwYYeTUVphySoCqMzaioGeoVH146HQlOx1LnCjwtCnVPKVupvmFQVdLrG1hAJubS1rAf6OHv1d5Qlt4amLCyhtTzfsrxWi2ehegKeWVZZVklWITBNHw1F8iKLEFkmtXQf+JkflhiE9GneX", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Mar 2026 11:11:02.4725\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 721ba7b3-8329-4461-3323-08de8b285e12", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSN1PEPF000397AF.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB8287" }, "content": "On Tegra264, reset is not available for the driver to control as\nthis is handled by the boot firmware. Hence make the reset control\noptional and update the error message to reflect the correct error.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\nReviewed-by: Frank Li <Frank.Li@nxp.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 4 ++--\n 1 file changed, 2 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex 5948fbf32c21..a0522a992ebc 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -1381,10 +1381,10 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \tif (IS_ERR(tdma->base_addr))\n \t\treturn PTR_ERR(tdma->base_addr);\n \n-\ttdma->rst = devm_reset_control_get_exclusive(&pdev->dev, \"gpcdma\");\n+\ttdma->rst = devm_reset_control_get_optional_exclusive(&pdev->dev, \"gpcdma\");\n \tif (IS_ERR(tdma->rst)) {\n \t\treturn dev_err_probe(&pdev->dev, PTR_ERR(tdma->rst),\n-\t\t\t \"Missing controller reset\\n\");\n+\t\t\t \"Failed to get controller reset\\n\");\n \t}\n \treset_control_reset(tdma->rst);\n \n", "prefixes": [ "v4", "04/10" ] }