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GET /api/patches/2216377/?format=api
{ "id": 2216377, "url": "http://patchwork.ozlabs.org/api/patches/2216377/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260326110948.68908-7-akhilrajeev@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326110948.68908-7-akhilrajeev@nvidia.com>", "list_archive_url": null, "date": "2026-03-26T11:09:43", "name": "[v4,06/10] dmaengine: tegra: Support address width > 39 bits", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "0fd70e309aa40752f48cb44566bbfc2a7922d8db", "submitter": { "id": 81965, "url": "http://patchwork.ozlabs.org/api/people/81965/?format=api", "name": "Akhil R", "email": "akhilrajeev@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260326110948.68908-7-akhilrajeev@nvidia.com/mbox/", "series": [ { "id": 497568, "url": "http://patchwork.ozlabs.org/api/series/497568/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497568", "date": "2026-03-26T11:09:37", "name": "Add GPCDMA support in Tegra264", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/497568/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216377/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216377/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13288-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=clilHE5B;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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pr=C", "From": "Akhil R <akhilrajeev@nvidia.com>", "To": "Vinod Koul <vkoul@kernel.org>, Frank Li <Frank.Li@kernel.org>, Rob Herring\n\t<robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley\n\t<conor+dt@kernel.org>, Thierry Reding <thierry.reding@gmail.com>, \"Jonathan\n Hunter\" <jonathanh@nvidia.com>, Laxman Dewangan <ldewangan@nvidia.com>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>, <dmaengine@vger.kernel.org>,\n\t<devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>,\n\t<linux-kernel@vger.kernel.org>", "CC": "Akhil R <akhilrajeev@nvidia.com>, Frank Li <Frank.Li@nxp.com>", "Subject": "[PATCH v4 06/10] dmaengine: tegra: Support address width > 39 bits", "Date": "Thu, 26 Mar 2026 16:39:43 +0530", "Message-ID": "<20260326110948.68908-7-akhilrajeev@nvidia.com>", "X-Mailer": "git-send-email 2.50.1", "In-Reply-To": "<20260326110948.68908-1-akhilrajeev@nvidia.com>", "References": "<20260326110948.68908-1-akhilrajeev@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "SN1PEPF000397AF:EE_|MW4PR12MB7263:EE_", "X-MS-Office365-Filtering-Correlation-Id": "b3ed7cef-e4bc-40fa-8e51-08de8b2866d4", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|7416014|82310400026|376014|36860700016|921020|22082099003|18002099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\tzI8j1QZoceGWo1FjWKqpMiUFm0fTQQhaI3BUjmBAuNSVnmw12UR7hajQV33QUyxQ7thvQWNdIwerKy+RR4sgBpiAcYnnbVTMh5QCkc16Ntx4lu0DPVuCuCxOkHFDh/Lf5fW9gxyxUu7UO0ykFhptzGW8+wW7cXrfOuG8MdmZNe4j+WHEELJnjRgFMVwSPKu4b6lxn+e5e6RhNVI/Ci0TEZKS9ZTreoLj4HG+vt3aVC0pmSlUZRoTFgL+qREP3z6WkqckoLdJfFiXzz1xtaS9MQQNzhQBWl/4eP48UinR3bILAXBIxRBkBA8B9Nte9fjrUkyZ3L4rKCnZCRa1NmC9EFk0Ta32gihqEOw/aFDEr7rott9jVwWS4yMZgH8N/4qiC/EsMqG+QDRjk5V4inUIlQWboiUDgxotve6/ilrzG+4uhCHgC1dP90a67hgN2QPsuFGafvfLuTZ3d68ONDCSoObogJbk6oZDoqi7Gp59FjKne5d9653ziSZVFPNZJHTcoXepoZfbHo7/zkPdRqtsAMcXEHAwknyMQpqqtGPVmo+TjNj+JYN7vPnNqn0ppRDzM0DRM2Rx6a1xJqOGYGOWh8AoRsjT2j3f0tQTl0uId+n6FKS2GA3znCDn/h/KK2SDR8kAw1QtPWdn89fad6hfFAwPwAsUSEtGL242G10uRzyEQ53qclsjLiONUpsNl9T9hyKtZzvuNHOwBaoIa06TPnBXUL5SBqaHiwMfzqXbEizg3HD+q+8AnnS0IziWuuwHo3Ku72n1Jlwl0hPAhLOePC5tGXoCvH5fxwmsB5rgxzCHSjLPlFL67/Lcovh757YU", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.233;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge2.nvidia.com;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(82310400026)(376014)(36860700016)(921020)(22082099003)(18002099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\twRLKPuP63zv7MIqzSeKbXF0jspFPaX+5KSZ2PPZZfHngac2+mTCoEwDmcws9JTO58kMdO5dtHTieyNty+Y2srjjOt4NKLhy4v9gTKvxgkBOxVnmXHKL3w+N+/pvVz7JSohv5rarjxjgbP1XGeeHveeTZcjZHSgIfgi+HeCBzoInQRMSi8sdY1tq2vNHAu/zUdFJk26jEXA5mGS1GhczhgTyJH4HDj657q63qBijZ2O95LOdpWgRrnr4/k40WLruhDyLWX29amXgE5gXohQVbqAuMM05UD3ew4VDYDOTjS4y/GkY7WWrLIiio63i+fJJ5Hc1ssyLAE2FWPKfORfClyp+dPR/W0MaLdw5e7pvdagXMkbccJ9coLhL9mnDs+s6Vvtbc+WcNSx89SYrE9W8ws2TIAoRpKekNscMpbvAAVDyaIXeAs+107yqLr7fJywUn", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "26 Mar 2026 11:11:17.1898\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b3ed7cef-e4bc-40fa-8e51-08de8b2866d4", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tSN1PEPF000397AF.namprd05.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW4PR12MB7263" }, "content": "Tegra264 supports address width of 41 bits. Unlike older SoCs which use\na common high_addr register for upper address bits, Tegra264 has separate\nsrc_high and dst_high registers to accommodate this wider address space.\n\nAdd an addr_bits property to the device data structure to specify the\nnumber of address bits supported on each device and use that to program\nthe appropriate registers.\n\nUpdate the sg_req struct to remove the high_addr field and use\ndma_addr_t for src and dst to store the complete addresses. Extract\nthe high address bits only when programming the registers.\n\nSigned-off-by: Akhil R <akhilrajeev@nvidia.com>\nReviewed-by: Frank Li <Frank.Li@nxp.com>\n---\n drivers/dma/tegra186-gpc-dma.c | 83 +++++++++++++++++++++-------------\n 1 file changed, 52 insertions(+), 31 deletions(-)", "diff": "diff --git a/drivers/dma/tegra186-gpc-dma.c b/drivers/dma/tegra186-gpc-dma.c\nindex b213c4ae07d2..3ac43ad19ed6 100644\n--- a/drivers/dma/tegra186-gpc-dma.c\n+++ b/drivers/dma/tegra186-gpc-dma.c\n@@ -146,6 +146,7 @@ struct tegra_dma_channel;\n */\n struct tegra_dma_chip_data {\n \tbool hw_support_pause;\n+\tunsigned int addr_bits;\n \tunsigned int nr_channels;\n \tunsigned int channel_reg_size;\n \tunsigned int max_dma_count;\n@@ -161,6 +162,8 @@ struct tegra_dma_channel_regs {\n \tu32 src;\n \tu32 dst;\n \tu32 high_addr;\n+\tu32 src_high;\n+\tu32 dst_high;\n \tu32 mc_seq;\n \tu32 mmio_seq;\n \tu32 wcount;\n@@ -179,10 +182,9 @@ struct tegra_dma_channel_regs {\n */\n struct tegra_dma_sg_req {\n \tunsigned int len;\n+\tdma_addr_t src;\n+\tdma_addr_t dst;\n \tu32 csr;\n-\tu32 src;\n-\tu32 dst;\n-\tu32 high_addr;\n \tu32 mc_seq;\n \tu32 mmio_seq;\n \tu32 wcount;\n@@ -266,6 +268,25 @@ static inline struct device *tdc2dev(struct tegra_dma_channel *tdc)\n \treturn tdc->vc.chan.device->dev;\n }\n \n+static void tegra_dma_program_addr(struct tegra_dma_channel *tdc,\n+\t\t\t\t struct tegra_dma_sg_req *sg_req)\n+{\n+\ttdc_write(tdc, tdc->regs->src, lower_32_bits(sg_req->src));\n+\ttdc_write(tdc, tdc->regs->dst, lower_32_bits(sg_req->dst));\n+\n+\tif (tdc->tdma->chip_data->addr_bits > 39) {\n+\t\ttdc_write(tdc, tdc->regs->src_high, upper_32_bits(sg_req->src));\n+\t\ttdc_write(tdc, tdc->regs->dst_high, upper_32_bits(sg_req->dst));\n+\t} else {\n+\t\tu32 src_high = FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR,\n+\t\t\t\t\t upper_32_bits(sg_req->src));\n+\t\tu32 dst_high = FIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR,\n+\t\t\t\t\t upper_32_bits(sg_req->dst));\n+\n+\t\ttdc_write(tdc, tdc->regs->high_addr, src_high | dst_high);\n+\t}\n+}\n+\n static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)\n {\n \tdev_dbg(tdc2dev(tdc), \"DMA Channel %d name %s register dump:\\n\",\n@@ -274,10 +295,20 @@ static void tegra_dma_dump_chan_regs(struct tegra_dma_channel *tdc)\n \t\ttdc_read(tdc, tdc->regs->csr),\n \t\ttdc_read(tdc, tdc->regs->status),\n \t\ttdc_read(tdc, tdc->regs->csre));\n-\tdev_dbg(tdc2dev(tdc), \"SRC %x DST %x HI ADDR %x\\n\",\n-\t\ttdc_read(tdc, tdc->regs->src),\n-\t\ttdc_read(tdc, tdc->regs->dst),\n-\t\ttdc_read(tdc, tdc->regs->high_addr));\n+\n+\tif (tdc->tdma->chip_data->addr_bits > 39) {\n+\t\tdev_dbg(tdc2dev(tdc), \"SRC %x SRC HI %x DST %x DST HI %x\\n\",\n+\t\t\ttdc_read(tdc, tdc->regs->src),\n+\t\t\ttdc_read(tdc, tdc->regs->src_high),\n+\t\t\ttdc_read(tdc, tdc->regs->dst),\n+\t\t\ttdc_read(tdc, tdc->regs->dst_high));\n+\t} else {\n+\t\tdev_dbg(tdc2dev(tdc), \"SRC %x DST %x HI ADDR %x\\n\",\n+\t\t\ttdc_read(tdc, tdc->regs->src),\n+\t\t\ttdc_read(tdc, tdc->regs->dst),\n+\t\t\ttdc_read(tdc, tdc->regs->high_addr));\n+\t}\n+\n \tdev_dbg(tdc2dev(tdc), \"MCSEQ %x IOSEQ %x WCNT %x XFER %x WSTA %x\\n\",\n \t\ttdc_read(tdc, tdc->regs->mc_seq),\n \t\ttdc_read(tdc, tdc->regs->mmio_seq),\n@@ -480,9 +511,7 @@ static void tegra_dma_configure_next_sg(struct tegra_dma_channel *tdc)\n \tsg_req = &dma_desc->sg_req[dma_desc->sg_idx];\n \n \ttdc_write(tdc, tdc->regs->wcount, sg_req->wcount);\n-\ttdc_write(tdc, tdc->regs->src, sg_req->src);\n-\ttdc_write(tdc, tdc->regs->dst, sg_req->dst);\n-\ttdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);\n+\ttegra_dma_program_addr(tdc, sg_req);\n \n \t/* Start DMA */\n \ttdc_write(tdc, tdc->regs->csr,\n@@ -510,11 +539,9 @@ static void tegra_dma_start(struct tegra_dma_channel *tdc)\n \n \tsg_req = &dma_desc->sg_req[dma_desc->sg_idx];\n \n+\ttegra_dma_program_addr(tdc, sg_req);\n \ttdc_write(tdc, tdc->regs->wcount, sg_req->wcount);\n \ttdc_write(tdc, tdc->regs->csr, 0);\n-\ttdc_write(tdc, tdc->regs->src, sg_req->src);\n-\ttdc_write(tdc, tdc->regs->dst, sg_req->dst);\n-\ttdc_write(tdc, tdc->regs->high_addr, sg_req->high_addr);\n \ttdc_write(tdc, tdc->regs->fixed_pattern, sg_req->fixed_pattern);\n \ttdc_write(tdc, tdc->regs->mmio_seq, sg_req->mmio_seq);\n \ttdc_write(tdc, tdc->regs->mc_seq, sg_req->mc_seq);\n@@ -819,7 +846,7 @@ static unsigned int get_burst_size(struct tegra_dma_channel *tdc,\n \n static int get_transfer_param(struct tegra_dma_channel *tdc,\n \t\t\t enum dma_transfer_direction direction,\n-\t\t\t u32 *apb_addr,\n+\t\t\t dma_addr_t *apb_addr,\n \t\t\t u32 *mmio_seq,\n \t\t\t u32 *csr,\n \t\t\t unsigned int *burst_size,\n@@ -897,11 +924,9 @@ tegra_dma_prep_dma_memset(struct dma_chan *dc, dma_addr_t dest, int value,\n \tdma_desc->bytes_req = len;\n \tdma_desc->sg_count = 1;\n \tsg_req = dma_desc->sg_req;\n-\n \tsg_req[0].src = 0;\n \tsg_req[0].dst = dest;\n-\tsg_req[0].high_addr =\n-\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));\n+\n \tsg_req[0].fixed_pattern = value;\n \t/* Word count reg takes value as (N +1) words */\n \tsg_req[0].wcount = ((len - 4) >> 2);\n@@ -969,10 +994,7 @@ tegra_dma_prep_dma_memcpy(struct dma_chan *dc, dma_addr_t dest,\n \n \tsg_req[0].src = src;\n \tsg_req[0].dst = dest;\n-\tsg_req[0].high_addr =\n-\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (src >> 32));\n-\tsg_req[0].high_addr |=\n-\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (dest >> 32));\n+\n \t/* Word count reg takes value as (N +1) words */\n \tsg_req[0].wcount = ((len - 4) >> 2);\n \tsg_req[0].csr = csr;\n@@ -992,7 +1014,8 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,\n \tstruct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);\n \tunsigned int max_dma_count = tdc->tdma->chip_data->max_dma_count;\n \tenum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;\n-\tu32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0;\n+\tu32 csr, mc_seq, mmio_seq = 0;\n+\tdma_addr_t apb_ptr = 0;\n \tstruct tegra_dma_sg_req *sg_req;\n \tstruct tegra_dma_desc *dma_desc;\n \tstruct scatterlist *sg;\n@@ -1080,13 +1103,9 @@ tegra_dma_prep_slave_sg(struct dma_chan *dc, struct scatterlist *sgl,\n \t\tif (direction == DMA_MEM_TO_DEV) {\n \t\t\tsg_req[i].src = mem;\n \t\t\tsg_req[i].dst = apb_ptr;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));\n \t\t} else if (direction == DMA_DEV_TO_MEM) {\n \t\t\tsg_req[i].src = apb_ptr;\n \t\t\tsg_req[i].dst = mem;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));\n \t\t}\n \n \t\t/*\n@@ -1110,7 +1129,8 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l\n \t\t\t unsigned long flags)\n {\n \tenum dma_slave_buswidth slave_bw = DMA_SLAVE_BUSWIDTH_UNDEFINED;\n-\tu32 csr, mc_seq, apb_ptr = 0, mmio_seq = 0, burst_size;\n+\tu32 csr, mc_seq, mmio_seq = 0, burst_size;\n+\tdma_addr_t apb_ptr = 0;\n \tunsigned int max_dma_count, len, period_count, i;\n \tstruct tegra_dma_channel *tdc = to_tegra_dma_chan(dc);\n \tstruct tegra_dma_desc *dma_desc;\n@@ -1201,13 +1221,9 @@ tegra_dma_prep_dma_cyclic(struct dma_chan *dc, dma_addr_t buf_addr, size_t buf_l\n \t\tif (direction == DMA_MEM_TO_DEV) {\n \t\t\tsg_req[i].src = mem;\n \t\t\tsg_req[i].dst = apb_ptr;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_SRC_PTR, (mem >> 32));\n \t\t} else if (direction == DMA_DEV_TO_MEM) {\n \t\t\tsg_req[i].src = apb_ptr;\n \t\t\tsg_req[i].dst = mem;\n-\t\t\tsg_req[i].high_addr =\n-\t\t\t\tFIELD_PREP(TEGRA_GPCDMA_HIGH_ADDR_DST_PTR, (mem >> 32));\n \t\t}\n \t\t/*\n \t\t * Word count register takes input in words. Writing a value\n@@ -1304,6 +1320,7 @@ static const struct tegra_dma_channel_regs tegra186_reg_offsets = {\n \n static const struct tegra_dma_chip_data tegra186_dma_chip_data = {\n \t.nr_channels = 32,\n+\t.addr_bits = 39,\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = false,\n@@ -1313,6 +1330,7 @@ static const struct tegra_dma_chip_data tegra186_dma_chip_data = {\n \n static const struct tegra_dma_chip_data tegra194_dma_chip_data = {\n \t.nr_channels = 32,\n+\t.addr_bits = 39,\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = true,\n@@ -1322,6 +1340,7 @@ static const struct tegra_dma_chip_data tegra194_dma_chip_data = {\n \n static const struct tegra_dma_chip_data tegra234_dma_chip_data = {\n \t.nr_channels = 32,\n+\t.addr_bits = 39,\n \t.channel_reg_size = SZ_64K,\n \t.max_dma_count = SZ_1G,\n \t.hw_support_pause = true,\n@@ -1433,6 +1452,8 @@ static int tegra_dma_probe(struct platform_device *pdev)\n \t\ttdc->stream_id = stream_id;\n \t}\n \n+\tdma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(cdata->addr_bits));\n+\n \tdma_cap_set(DMA_SLAVE, tdma->dma_dev.cap_mask);\n \tdma_cap_set(DMA_PRIVATE, tdma->dma_dev.cap_mask);\n \tdma_cap_set(DMA_MEMCPY, tdma->dma_dev.cap_mask);\n", "prefixes": [ "v4", "06/10" ] }