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GET /api/patches/2216283/?format=api
{ "id": 2216283, "url": "http://patchwork.ozlabs.org/api/patches/2216283/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260326091130.321483-3-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326091130.321483-3-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-26T09:11:16", "name": "[v2,02/14] iommufd: Extend attach/detach_hwpt callbacks to support pasid", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d92a67771ec9c6362f8a7b5dba646f6e3aa97635", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260326091130.321483-3-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497556, "url": "http://patchwork.ozlabs.org/api/series/497556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497556", "date": "2026-03-26T09:11:19", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497556/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216283/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216283/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=S/4yt/wk;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhJ3w5F1sz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 20:13:48 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5gkw-0002kj-72; Thu, 26 Mar 2026 05:11:58 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5gku-0002k7-3Y; Thu, 26 Mar 2026 05:11:56 -0400", "from mgamail.intel.com ([198.175.65.17])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5gks-0003vM-7M; Thu, 26 Mar 2026 05:11:55 -0400", "from fmviesa001.fm.intel.com ([10.60.135.141])\n by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 02:11:53 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 02:11:49 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774516315; x=1806052315;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=foksISldHtV0VQ/dVtjMN2IGqwNby9lo/p4TbgaTPyM=;\n b=S/4yt/wk+JJtZWGPA/0fcqFS6sTfDvzKLb3GDxO4s5xvoQX2QJedv/XJ\n hEN2O8Theiqsb7u9tv+U7NoDb0JmBNUSe4VmnQa4Mek7bnmxUDPi6tXyi\n JshUADtzWpgBcNkbnUCNBObxjP838jMlxM4E/bEHJgvd6HhJAiC/0xOZC\n H/ufcT7ED/QgKcBF+70pVLuD12KS1nRGtkX3JUXA5bQBQMfHNHwxlQui+\n zUo0xAcYVV0JrIHTpFa1X4QnQ4nPGC6T0DIhCOqp9lId2GPxHAUzg1ZC9\n g2nm2CNytSz0lAEvo4u2o8jPtEBIJEfQVtdYunI5ONXqQSVXFEpEuasNA A==;", "X-CSE-ConnectionGUID": [ "ZOom+LKaTpG03n+xihiHfQ==", "EfT0KxC9ReK3U9pUUCrPiw==" ], "X-CSE-MsgGUID": [ "bM1kcCCdRdGz0fiG9oMjHw==", "aXCffF3fRUiRYl1ChgUDOg==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11740\"; a=\"75531314\"", "E=Sophos;i=\"6.23,141,1770624000\"; d=\"scan'208\";a=\"75531314\"", "E=Sophos;i=\"6.23,141,1770624000\"; d=\"scan'208\";a=\"248368557\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>,\n qemu-arm@nongnu.org", "Subject": "[PATCH v2 02/14] iommufd: Extend attach/detach_hwpt callbacks to\n support pasid", "Date": "Thu, 26 Mar 2026 05:11:16 -0400", "Message-ID": "<20260326091130.321483-3-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260326091130.321483-1-zhenzhong.duan@intel.com>", "References": "<20260326091130.321483-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.17;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Same for the two wrappers and their call sites.\n\nSuggested-by: Shameer Kolothum Thodi <skolothumtho@nvidia.com>\nSuggested-by: Nicolin Chen <nicolinc@nvidia.com>\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\nReviewed-by: Yi Liu <yi.l.liu@intel.com>\n---\n include/system/iommufd.h | 16 +++++++++++-----\n backends/iommufd.c | 9 +++++----\n hw/arm/smmuv3-accel.c | 12 ++++++++----\n hw/i386/intel_iommu_accel.c | 8 +++++---\n hw/vfio/iommufd.c | 10 +++++-----\n 5 files changed, 34 insertions(+), 21 deletions(-)", "diff": "diff --git a/include/system/iommufd.h b/include/system/iommufd.h\nindex 7062944fe6..45a9e87cb0 100644\n--- a/include/system/iommufd.h\n+++ b/include/system/iommufd.h\n@@ -138,14 +138,16 @@ struct HostIOMMUDeviceIOMMUFDClass {\n *\n * @idev: host IOMMU device backed by IOMMUFD backend.\n *\n+ * @pasid: target pasid of attach.\n+ *\n * @hwpt_id: ID of IOMMUFD hardware page table.\n *\n * @errp: pass an Error out when attachment fails.\n *\n * Returns: true on success, false on failure.\n */\n- bool (*attach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, uint32_t hwpt_id,\n- Error **errp);\n+ bool (*attach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, uint32_t pasid,\n+ uint32_t hwpt_id, Error **errp);\n /**\n * @detach_hwpt: detach host IOMMU device from IOMMUFD hardware page table.\n * VFIO and VDPA device can have different implementation.\n@@ -154,15 +156,19 @@ struct HostIOMMUDeviceIOMMUFDClass {\n *\n * @idev: host IOMMU device backed by IOMMUFD backend.\n *\n+ * @pasid: target pasid of detach.\n+ *\n * @errp: pass an Error out when attachment fails.\n *\n * Returns: true on success, false on failure.\n */\n- bool (*detach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, Error **errp);\n+ bool (*detach_hwpt)(HostIOMMUDeviceIOMMUFD *idev, uint32_t pasid,\n+ Error **errp);\n };\n \n bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n- uint32_t hwpt_id, Error **errp);\n-bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n+ uint32_t pasid, uint32_t hwpt_id,\n Error **errp);\n+bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n+ uint32_t pasid, Error **errp);\n #endif\ndiff --git a/backends/iommufd.c b/backends/iommufd.c\nindex e1fee16acf..ab612e4874 100644\n--- a/backends/iommufd.c\n+++ b/backends/iommufd.c\n@@ -539,23 +539,24 @@ bool iommufd_backend_alloc_veventq(IOMMUFDBackend *be, uint32_t viommu_id,\n }\n \n bool host_iommu_device_iommufd_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n- uint32_t hwpt_id, Error **errp)\n+ uint32_t pasid, uint32_t hwpt_id,\n+ Error **errp)\n {\n HostIOMMUDeviceIOMMUFDClass *idevc =\n HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(idev);\n \n g_assert(idevc->attach_hwpt);\n- return idevc->attach_hwpt(idev, hwpt_id, errp);\n+ return idevc->attach_hwpt(idev, pasid, hwpt_id, errp);\n }\n \n bool host_iommu_device_iommufd_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n- Error **errp)\n+ uint32_t pasid, Error **errp)\n {\n HostIOMMUDeviceIOMMUFDClass *idevc =\n HOST_IOMMU_DEVICE_IOMMUFD_GET_CLASS(idev);\n \n g_assert(idevc->detach_hwpt);\n- return idevc->detach_hwpt(idev, errp);\n+ return idevc->detach_hwpt(idev, pasid, errp);\n }\n \n static int hiod_iommufd_get_cap(HostIOMMUDevice *hiod, int cap, Error **errp)\ndiff --git a/hw/arm/smmuv3-accel.c b/hw/arm/smmuv3-accel.c\nindex 65c2f44880..0af6b3296d 100644\n--- a/hw/arm/smmuv3-accel.c\n+++ b/hw/arm/smmuv3-accel.c\n@@ -300,7 +300,8 @@ bool smmuv3_accel_install_ste(SMMUv3State *s, SMMUDevice *sdev, int sid,\n return false;\n }\n \n- if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) {\n+ if (!host_iommu_device_iommufd_attach_hwpt(idev, IOMMU_NO_PASID, hwpt_id,\n+ errp)) {\n if (s1_hwpt) {\n iommufd_backend_free_id(idev->iommufd, s1_hwpt->hwpt_id);\n g_free(s1_hwpt);\n@@ -575,7 +576,8 @@ smmuv3_accel_alloc_viommu(SMMUv3State *s, HostIOMMUDeviceIOMMUFD *idev,\n \n /* Attach a HWPT based on SMMUv3 GBPA.ABORT value */\n hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel);\n- if (!host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp)) {\n+ if (!host_iommu_device_iommufd_attach_hwpt(idev, IOMMU_NO_PASID, hwpt_id,\n+ errp)) {\n goto free_veventq;\n }\n return true;\n@@ -665,7 +667,8 @@ static void smmuv3_accel_unset_iommu_device(PCIBus *bus, void *opaque,\n idev = accel_dev->idev;\n accel = accel_dev->s_accel;\n /* Re-attach the default s2 hwpt id */\n- if (!host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id, NULL)) {\n+ if (!host_iommu_device_iommufd_attach_hwpt(idev, IOMMU_NO_PASID,\n+ idev->hwpt_id, NULL)) {\n error_report(\"Unable to attach the default HW pagetable: idev devid \"\n \"0x%x\", idev->devid);\n }\n@@ -879,7 +882,8 @@ bool smmuv3_accel_attach_gbpa_hwpt(SMMUv3State *s, Error **errp)\n \n hwpt_id = smmuv3_accel_gbpa_hwpt(s, accel);\n QLIST_FOREACH(accel_dev, &accel->device_list, next) {\n- if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev, hwpt_id,\n+ if (!host_iommu_device_iommufd_attach_hwpt(accel_dev->idev,\n+ IOMMU_NO_PASID, hwpt_id,\n &local_err)) {\n error_append_hint(&local_err, \"Failed to attach GBPA hwpt %u for \"\n \"idev devid %u\", hwpt_id, accel_dev->idev->devid);\ndiff --git a/hw/i386/intel_iommu_accel.c b/hw/i386/intel_iommu_accel.c\nindex 67d54849f2..45c08c8f6f 100644\n--- a/hw/i386/intel_iommu_accel.c\n+++ b/hw/i386/intel_iommu_accel.c\n@@ -121,7 +121,8 @@ static bool vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod,\n }\n }\n \n- ret = host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp);\n+ ret = host_iommu_device_iommufd_attach_hwpt(idev, IOMMU_NO_PASID, hwpt_id,\n+ errp);\n trace_vtd_device_attach_hwpt(idev->devid, vtd_as->pasid, hwpt_id, ret);\n if (ret) {\n /* Destroy old fs_hwpt if it's a replacement */\n@@ -145,7 +146,7 @@ static bool vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod,\n bool ret;\n \n if (s->dmar_enabled && s->root_scalable) {\n- ret = host_iommu_device_iommufd_detach_hwpt(idev, errp);\n+ ret = host_iommu_device_iommufd_detach_hwpt(idev, IOMMU_NO_PASID, errp);\n trace_vtd_device_detach_hwpt(idev->devid, pasid, ret);\n } else {\n /*\n@@ -153,7 +154,8 @@ static bool vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod,\n * we fallback to the default HWPT which contains shadow page table.\n * So guest DMA could still work.\n */\n- ret = host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id, errp);\n+ ret = host_iommu_device_iommufd_attach_hwpt(idev, IOMMU_NO_PASID,\n+ idev->hwpt_id, errp);\n trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_id,\n ret);\n }\ndiff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c\nindex 93f1e61a8c..e822039858 100644\n--- a/hw/vfio/iommufd.c\n+++ b/hw/vfio/iommufd.c\n@@ -927,21 +927,21 @@ static void vfio_iommu_iommufd_class_init(ObjectClass *klass, const void *data)\n \n static bool\n host_iommu_device_iommufd_vfio_attach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n- uint32_t hwpt_id, Error **errp)\n+ uint32_t pasid, uint32_t hwpt_id,\n+ Error **errp)\n {\n VFIODevice *vbasedev = HOST_IOMMU_DEVICE(idev)->agent;\n \n- return !iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, IOMMU_NO_PASID,\n- hwpt_id, errp);\n+ return !iommufd_cdev_pasid_attach_ioas_hwpt(vbasedev, pasid, hwpt_id, errp);\n }\n \n static bool\n host_iommu_device_iommufd_vfio_detach_hwpt(HostIOMMUDeviceIOMMUFD *idev,\n- Error **errp)\n+ uint32_t pasid, Error **errp)\n {\n VFIODevice *vbasedev = HOST_IOMMU_DEVICE(idev)->agent;\n \n- return iommufd_cdev_pasid_detach_ioas_hwpt(vbasedev, IOMMU_NO_PASID, errp);\n+ return iommufd_cdev_pasid_detach_ioas_hwpt(vbasedev, pasid, errp);\n }\n \n static bool hiod_iommufd_vfio_realize(HostIOMMUDevice *hiod, void *opaque,\n", "prefixes": [ "v2", "02/14" ] }