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GET /api/patches/2216277/?format=api
{ "id": 2216277, "url": "http://patchwork.ozlabs.org/api/patches/2216277/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260326091136.709342-7-Alexander.Feilke@ew.tq-group.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326091136.709342-7-Alexander.Feilke@ew.tq-group.com>", "list_archive_url": null, "date": "2026-03-26T09:11:34", "name": "[v3,6/8] board: tqma7: add code for u-boot with spl", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "1665aa60ea6972dd09d22f759bbc0f3c2d58cb37", "submitter": { "id": 92142, "url": "http://patchwork.ozlabs.org/api/people/92142/?format=api", "name": "Alexander Feilke", "email": "Alexander.Feilke@ew.tq-group.com" }, "delegate": { "id": 151988, "url": "http://patchwork.ozlabs.org/api/users/151988/?format=api", "username": "festevam", "first_name": "Fabio", "last_name": "Estevam", "email": "festevam@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260326091136.709342-7-Alexander.Feilke@ew.tq-group.com/mbox/", "series": [ { "id": 497555, "url": "http://patchwork.ozlabs.org/api/series/497555/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497555", "date": "2026-03-26T09:11:30", "name": "Add support for TQMa7x", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497555/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216277/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216277/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ew.tq-group.com header.i=@ew.tq-group.com\n header.a=rsa-sha256 header.s=default2602 header.b=DeG7eKdG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; helo=phobos.denx.de;\n envelope-from=u-boot-bounces@lists.denx.de; receiver=patchwork.ozlabs.org)", "phobos.denx.de;\n dmarc=fail (p=quarantine dis=none) header.from=ew.tq-group.com", "phobos.denx.de;\n spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de", "phobos.denx.de;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n unprotected) header.d=ew.tq-group.com header.i=@ew.tq-group.com\n header.b=\"DeG7eKdG\";\n\tdkim-atps=neutral", "phobos.denx.de; dmarc=pass (p=quarantine dis=none)\n header.from=ew.tq-group.com", "phobos.denx.de; spf=pass\n smtp.mailfrom=Alexander.Feilke@ew.tq-group.com" ], "Received": [ "from phobos.denx.de (phobos.denx.de [85.214.62.61])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhJ3J5PgLz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 20:13:16 +1100 (AEDT)", "from h2850616.stratoserver.net (localhost [IPv6:::1])\n\tby phobos.denx.de (Postfix) with ESMTP id 6C58C8406D;\n\tThu, 26 Mar 2026 10:12:14 +0100 (CET)", "by phobos.denx.de (Postfix, from userid 109)\n id E05DF83CD3; Thu, 26 Mar 2026 10:12:08 +0100 (CET)", "from www537.your-server.de (www537.your-server.de [188.40.3.216])\n (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits))\n (No client certificate requested)\n by phobos.denx.de (Postfix) with ESMTPS id CD07281E18\n for <u-boot@lists.denx.de>; Thu, 26 Mar 2026 10:12:04 +0100 (CET)", "from sslproxy07.your-server.de ([78.47.199.104])\n by www537.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384\n (Exim 4.96.2) (envelope-from <Alexander.Feilke@ew.tq-group.com>)\n id 1w5gkz-000O7p-1Z; Thu, 26 Mar 2026 10:12:01 +0100", "from localhost ([127.0.0.1])\n by sslproxy07.your-server.de with esmtpsa (TLS1.3) tls TLS_AES_256_GCM_SHA384\n (Exim 4.96) (envelope-from <Alexander.Feilke@ew.tq-group.com>)\n id 1w5gkz-000DCP-0w; Thu, 26 Mar 2026 10:12:01 +0100" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.2 (2018-09-13) on phobos.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.0 required=5.0 tests=BAYES_00,DKIM_SIGNED,\n DKIM_VALID,DKIM_VALID_AU,RCVD_IN_DNSWL_BLOCKED,\n RCVD_IN_VALIDITY_CERTIFIED_BLOCKED,RCVD_IN_VALIDITY_RPBL_BLOCKED,\n SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.2", "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n d=ew.tq-group.com; s=default2602; h=Content-Transfer-Encoding:MIME-Version:\n References:In-Reply-To:Message-Id:Date:Subject:Cc:To:From:Sender:Reply-To:\n Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From:\n Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID;\n bh=j/7gTQjMymRIaucaSjgUlDSq8h98bqT4rW6/+w+aolc=; b=DeG7eKdGvnDJ/G+dAzuaHBjbOp\n zMfyJv4TKK2yjqBuZBZpuiYmlYQnR/ixzHBg1dpWjTnboaqtOQZZdHQFDCa5sbrCJJJwx96ja9Xf6\n wOHqVAO3lQzxVMFT2qH+eatOTnd+aiIVQsoX7fMb0QwCutezHpDXXtX+FRFbB/XrVO/9WFEOmrYFY\n ErTVpL+EoCUz7+oMSQLmuKfdHYNbrtfAhDhpOi+FgGiFOwMU6mBUDP71ppaOLvdR75YR0qNikPNPr\n EIzhtPH3HhYd9bXkemMmIsSvTg2B88omSDpfLKrvD9J6OjQrhqxitsTk06lXWdONX45Oi8SmfyOUr\n ZL6lnYlg==;", "From": "Alexander Feilke <Alexander.Feilke@ew.tq-group.com>", "To": "\"NXP i.MX U-Boot Team\" <uboot-imx@nxp.com>, u-boot@lists.denx.de,\n u-boot@ew.tq-group.com", "Cc": "Alexander Feilke <alexander.feilke@ew.tq-group.com>,\n Tom Rini <trini@konsulko.com>,\n Alexander Feilke <Alexander.Feilke@ew.tq-group.com>,\n Stefano Babic <sbabic@nabladev.com>, Fabio Estevam <festevam@gmail.com>,\n Peng Fan <peng.fan@nxp.com>, Jaehoon Chung <jh80.chung@samsung.com>", "Subject": "[PATCH v3 6/8] board: tqma7: add code for u-boot with spl", "Date": "Thu, 26 Mar 2026 10:11:34 +0100", "Message-Id": "<20260326091136.709342-7-Alexander.Feilke@ew.tq-group.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260326091136.709342-1-Alexander.Feilke@ew.tq-group.com>", "References": "<20260326091136.709342-1-Alexander.Feilke@ew.tq-group.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.39", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<https://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n <mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>", "X-Virus-Scanned": "clamav-milter 0.103.8 at phobos.denx.de", "X-Virus-Status": "Clean" }, "content": "From: Alexander Feilke <alexander.feilke@ew.tq-group.com>\n\nThe TQMa7x is a SoM family with a pluggable board connector based on the\ni.MX7 SoCs. Add support for the SoM and its combination with our\nMBa7x carrier board.\n\nAcked-by: Peng Fan <peng.fan@nxp.com>\nSigned-off-by: Alexander Feilke <alexander.feilke@ew.tq-group.com>\n---\n arch/arm/mach-imx/mx7/Kconfig | 16 +++\n board/tq/MAINTAINERS | 9 ++\n board/tq/tqma7/Kconfig | 103 +++++++++++++++++++\n board/tq/tqma7/Makefile | 14 +++\n board/tq/tqma7/spl.c | 123 ++++++++++++++++++++++\n board/tq/tqma7/spl_mba7.c | 182 +++++++++++++++++++++++++++++++++\n board/tq/tqma7/spl_tqma7_ram.c | 171 +++++++++++++++++++++++++++++++\n board/tq/tqma7/tqma7.c | 96 +++++++++++++++++\n board/tq/tqma7/tqma7.cfg | 26 +++++\n board/tq/tqma7/tqma7.env | 35 +++++++\n board/tq/tqma7/tqma7_mba7.c | 148 +++++++++++++++++++++++++++\n include/configs/tqma7.h | 71 +++++++++++++\n include/configs/tqma7_mba7.h | 16 +++\n include/env/tq/spi.env | 4 +\n 14 files changed, 1014 insertions(+)\n create mode 100644 board/tq/tqma7/Kconfig\n create mode 100644 board/tq/tqma7/Makefile\n create mode 100644 board/tq/tqma7/spl.c\n create mode 100644 board/tq/tqma7/spl_mba7.c\n create mode 100644 board/tq/tqma7/spl_tqma7_ram.c\n create mode 100644 board/tq/tqma7/tqma7.c\n create mode 100644 board/tq/tqma7/tqma7.cfg\n create mode 100644 board/tq/tqma7/tqma7.env\n create mode 100644 board/tq/tqma7/tqma7_mba7.c\n create mode 100644 include/configs/tqma7.h\n create mode 100644 include/configs/tqma7_mba7.h", "diff": "diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig\nindex f576ee650f0..597eca142af 100644\n--- a/arch/arm/mach-imx/mx7/Kconfig\n+++ b/arch/arm/mach-imx/mx7/Kconfig\n@@ -90,6 +90,21 @@ config TARGET_COLIBRI_IMX7\n \tselect MX7D\n \timply CMD_DM\n \n+config TARGET_TQMA7\n+\tbool \"TQ-Systems TQMa7x SoM\"\n+\tselect BOARD_LATE_INIT\n+\tselect SUPPORT_SPL\n+\tselect SPL_SEPARATE_BSS if SPL\n+\tselect DM\n+\tselect DM_SERIAL\n+\tselect MX7\n+\timply MX7D\n+\timply CMD_DM\n+\timply DM_THERMAL\n+\thelp\n+\t TQMa7x is a TQ SoM with i.MX7 CPU\n+\t The SoM can be used on various baseboards.\n+\n endchoice\n \n config SYS_SOC\n@@ -102,6 +117,7 @@ source \"board/novtech/meerkat96/Kconfig\"\n source \"board/storopack/smegw01/Kconfig\"\n source \"board/technexion/pico-imx7d/Kconfig\"\n source \"board/toradex/colibri_imx7/Kconfig\"\n+source \"board/tq/tqma7/Kconfig\"\n source \"board/warp7/Kconfig\"\n \n endif\ndiff --git a/board/tq/MAINTAINERS b/board/tq/MAINTAINERS\nindex e6f3dc4da21..b31c5793432 100644\n--- a/board/tq/MAINTAINERS\n+++ b/board/tq/MAINTAINERS\n@@ -6,3 +6,12 @@ W:\thttps://www.tq-group.com/en/products/tq-embedded/\n F:\tarch/arm/dts/*mba6*.dts*\n F:\tarch/arm/dts/*tqma6*.dts*\n F:\tconfigs/tqma6*config\n+\n+TQMA7\n+M:\tAlexander Feilke <Alexander.Feilke@ew.tq-group.com>\n+L:\tu-boot@ew.tq-group.com\n+S:\tMaintained\n+W:\thttps://www.tq-group.com/en/products/tq-embedded/\n+F:\tarch/arm/dts/*mba7*.dts*\n+F:\tarch/arm/dts/*tqma7*.dts*\n+F:\tconfigs/tqma7*config\ndiff --git a/board/tq/tqma7/Kconfig b/board/tq/tqma7/Kconfig\nnew file mode 100644\nindex 00000000000..477ce3f3d53\n--- /dev/null\n+++ b/board/tq/tqma7/Kconfig\n@@ -0,0 +1,103 @@\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+# D-82229 Seefeld, Germany.\n+# Author: Markus Niebel, Steffen Doster\n+#\n+\n+if TARGET_TQMA7\n+\n+config SYS_BOARD\n+\tdefault \"tqma7\"\n+\n+config SYS_VENDOR\n+\tdefault \"tq\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"tqma7\"\n+\n+choice\n+\tprompt \"TQMa7x RAM configuration\"\n+\tdefault TQMA7_RAM_MULTI\n+\thelp\n+\t Select RAM configuration. Normally use default here but for\n+\t specific setup it is possible to use a single RAM size.\n+\n+config TQMA7_RAM_MULTI\n+\tbool \"TQMa7x with 512/1024/2048 MB RAM - Single image\"\n+\tselect TQMA7_RAM_2G\n+\tselect TQMA7_RAM_1G\n+\tselect TQMA7_RAM_512M\n+\thelp\n+\t Build a single U-Boot solely for variants\n+\t with 512/1024/2048 MB RAM.\n+\n+config TQMA7_RAM_SINGLE_2G\n+\tbool \"TQMa7x with 2 GB RAM\"\n+\tselect TQMA7_RAM_2G\n+\thelp\n+\t Build U-Boot solely for variants\n+\t with 2 GB RAM.\n+\n+config TQMA7_RAM_SINGLE_1G\n+\tbool \"TQMa7x with 1 GB RAM\"\n+\tselect TQMA7_RAM_1G\n+\thelp\n+\t Build U-Boot solely for variants\n+\t with 1 GB RAM.\n+\n+config TQMA7_RAM_SINGLE_512M\n+\tbool \"TQMa7x with 512 MB RAM\"\n+\tselect TQMA7_RAM_512M\n+\thelp\n+\t Build U-Boot solely for variants\n+\t with 512 MB RAM.\n+\n+endchoice\n+\n+config TQMA7_RAM_2G\n+\tbool\n+\n+config TQMA7_RAM_1G\n+\tbool\n+\n+config TQMA7_RAM_512M\n+\tbool\n+\n+choice\n+\tprompt \"TQMa7x base board variant\"\n+\tdefault MBA7\n+\thelp\n+\t Select base board\n+\t for TQMa7x\n+\n+config MBA7\n+\tbool \"TQMa7x on MBa7x Starterkit\"\n+\tselect TQ_COMMON_BB\n+\tselect TQ_COMMON_SOM\n+\tselect TQ_COMMON_SYSINFO\n+\tselect I2C_EEPROM\n+\tselect MISC\n+\timply USB\n+\timply CMD_USB\n+\timply USB_STORAGE\n+\timply PHYLIB\n+\timply CONFIG_PHY_TI_DP83867\n+\tselect MXC_UART\n+\tselect DM_MMC\n+\tselect DM_SPI\n+\tselect DM_I2C\n+\tselect DM_GPIO\n+\timply DM_ETH\n+\thelp\n+\t Select the MBa7x\n+\t starterkit.\n+\n+endchoice\n+\n+config IMX_CONFIG\n+\tdefault \"board/tq/tqma7/tqma7.cfg\"\n+\n+source \"board/tq/common/Kconfig\"\n+\n+endif\ndiff --git a/board/tq/tqma7/Makefile b/board/tq/tqma7/Makefile\nnew file mode 100644\nindex 00000000000..b1fb270e861\n--- /dev/null\n+++ b/board/tq/tqma7/Makefile\n@@ -0,0 +1,14 @@\n+# SPDX-License-Identifier: GPL-2.0-or-later\n+#\n+# Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+# D-82229 Seefeld, Germany.\n+\n+\n+obj-y += tqma7.o\n+obj-$(CONFIG_MBA7) += tqma7_mba7.o\n+\n+ifdef CONFIG_SPL_BUILD\n+obj-y += spl.o\n+obj-y += spl_tqma7_ram.o\n+obj-$(CONFIG_MBA7) += spl_mba7.o\n+endif\ndiff --git a/board/tq/tqma7/spl.c b/board/tq/tqma7/spl.c\nnew file mode 100644\nindex 00000000000..62db30e81f2\n--- /dev/null\n+++ b/board/tq/tqma7/spl.c\n@@ -0,0 +1,123 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2014-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Alexander Feilke\n+ */\n+\n+#include <fsl_esdhc_imx.h>\n+#include <hang.h>\n+#include <spl.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch-mx7/mx7d_pins.h>\n+#include <asm/mach-imx/boot_mode.h>\n+#include <asm/mach-imx/iomux-v3.h>\n+\n+#include \"../common/tq_bb.h\"\n+#include \"../common/tq_som.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+#define USDHC_PAD_CTRL\t\t(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \\\n+\tPAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)\n+\n+#define USDHC_CMD_PAD_CTRL\t(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \\\n+\tPAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)\n+\n+#define USDHC_CLK_PAD_CTRL\t(PAD_CTL_DSE_3P3V_98OHM | \\\n+\tPAD_CTL_SRE_SLOW | PAD_CTL_PUS_PU47KOHM)\n+\n+#define USDHC_STROBE_PAD_CTRL\t(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \\\n+\tPAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM)\n+\n+/* eMMC on USDHCI3 always present */\n+static const iomux_v3_cfg_t tqma7_usdhc3_pads[] = {\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_CLK__SD3_CLK,\t\tUSDHC_CLK_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_CMD__SD3_CMD,\t\tUSDHC_CMD_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA0__SD3_DATA0,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA1__SD3_DATA1,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA2__SD3_DATA2,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA3__SD3_DATA3,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA4__SD3_DATA4,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA5__SD3_DATA5,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA6__SD3_DATA6,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_DATA7__SD3_DATA7,\tUSDHC_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD3_STROBE__SD3_STROBE,\tUSDHC_STROBE_PAD_CTRL),\n+};\n+\n+static struct fsl_esdhc_cfg tqma7_usdhc3_cfg = {\n+\t.esdhc_base = USDHC3_BASE_ADDR,\n+\t.max_bus_width = 8,\n+};\n+\n+int board_mmc_getcd(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC3_BASE_ADDR)\n+\t\t/* eMMC/uSDHC3 is always present */\n+\t\tret = 1;\n+\telse\n+\t\tret = tq_bb_board_mmc_getcd(mmc);\n+\n+\treturn ret;\n+}\n+\n+int board_mmc_getwp(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC3_BASE_ADDR)\n+\t\t/* eMMC/uSDHC3 is not WP */\n+\t\tret = 0;\n+\telse\n+\t\tret = tq_bb_board_mmc_getwp(mmc);\n+\n+\treturn ret;\n+}\n+\n+int board_mmc_init(struct bd_info *bis)\n+{\n+\timx_iomux_v3_setup_multiple_pads(tqma7_usdhc3_pads,\n+\t\t\t\t\t ARRAY_SIZE(tqma7_usdhc3_pads));\n+\n+\ttqma7_usdhc3_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);\n+\n+\tif (fsl_esdhc_initialize(bis, &tqma7_usdhc3_cfg))\n+\t\tputs(\"Warning: failed to initialize eMMC dev\\n\");\n+\n+\ttq_bb_board_mmc_init(bis);\n+\n+\treturn 0;\n+}\n+\n+int board_init(void)\n+{\n+\t/* address of boot parameters */\n+\tgd->bd->bi_boot_params = PHYS_SDRAM + 0x100;\n+\n+\treturn tq_bb_board_init();\n+}\n+\n+/*\n+ * called from C runtime startup code (arch/arm/lib/crt0.S:_main)\n+ * - we have a stack and a place to store GD, both in SRAM\n+ * - no variable global data is available\n+ */\n+void board_init_f(ulong dummy)\n+{\n+\t/* setup AIPS and disable watchdog */\n+\tarch_cpu_init();\n+\n+\ttimer_init();\n+\n+\ttq_bb_board_early_init_f();\n+\n+\tpreloader_console_init();\n+\n+\t/* DDR initialization */\n+\ttq_som_ram_init();\n+}\n+\ndiff --git a/board/tq/tqma7/spl_mba7.c b/board/tq/tqma7/spl_mba7.c\nnew file mode 100644\nindex 00000000000..13438247731\n--- /dev/null\n+++ b/board/tq/tqma7/spl_mba7.c\n@@ -0,0 +1,182 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2014-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Alexander Feilke\n+ */\n+\n+#include <fsl_esdhc_imx.h>\n+#include <spl.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/crm_regs.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/gpio.h>\n+#include <asm/mach-imx/boot_mode.h>\n+#include <asm/mach-imx/iomux-v3.h>\n+#include <asm/arch-mx7/mx7d_pins.h>\n+\n+#include \"../common/tq_bb.h\"\n+\n+#define UART_RX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \\\n+\tPAD_CTL_PUE | PAD_CTL_HYS | PAD_CTL_SRE_SLOW)\n+\n+#define UART_TX_PAD_CTRL (PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_PUS_PU100KOHM | \\\n+\tPAD_CTL_PUE | PAD_CTL_SRE_SLOW)\n+\n+#define USDHC_DATA_PAD_CTRL\t(PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \\\n+\tPAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)\n+\n+#define USDHC_CMD_PAD_CTRL\t(PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \\\n+\tPAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)\n+\n+#define USDHC_CLK_PAD_CTRL\t(PAD_CTL_DSE_3P3V_49OHM | PAD_CTL_SRE_FAST | \\\n+\tPAD_CTL_PUE | PAD_CTL_PUS_PU47KOHM)\n+\n+#define USDHC_STROBE_PAD_CTRL\t(PAD_CTL_DSE_3P3V_98OHM | PAD_CTL_SRE_FAST | \\\n+\tPAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PUS_PD100KOHM)\n+\n+#define GPIO_IN_PAD_CTRL\t(PAD_CTL_PUS_PU100KOHM | \\\n+\tPAD_CTL_DSE_3P3V_196OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW)\n+#define GPIO_OUT_PAD_CTRL\t(PAD_CTL_PUS_PU100KOHM | \\\n+\tPAD_CTL_DSE_3P3V_98OHM | PAD_CTL_HYS | PAD_CTL_SRE_SLOW)\n+\n+static const iomux_v3_cfg_t mba7_uart6_pads[] = {\n+\tNEW_PAD_CTRL(MX7D_PAD_EPDC_DATA08__UART6_DCE_RX, UART_RX_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_EPDC_DATA09__UART6_DCE_TX, UART_TX_PAD_CTRL),\n+};\n+\n+static void mba7_setup_iomuxc_uart(void)\n+{\n+\timx_iomux_v3_setup_multiple_pads(mba7_uart6_pads, ARRAY_SIZE(mba7_uart6_pads));\n+}\n+\n+static const iomux_v3_cfg_t mba7_usdhc1_pads[] = {\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_CLK__SD1_CLK,\t\tUSDHC_CLK_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_CMD__SD1_CMD,\t\tUSDHC_CMD_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_DATA0__SD1_DATA0,\tUSDHC_DATA_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_DATA1__SD1_DATA1,\tUSDHC_DATA_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_DATA2__SD1_DATA2,\tUSDHC_DATA_PAD_CTRL),\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_DATA3__SD1_DATA3,\tUSDHC_DATA_PAD_CTRL),\n+\t/* CD */\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_CD_B__GPIO5_IO0,\tGPIO_IN_PAD_CTRL),\n+\t/* WP */\n+\tNEW_PAD_CTRL(MX7D_PAD_SD1_WP__GPIO5_IO1,\tGPIO_IN_PAD_CTRL),\n+};\n+\n+#define USDHC1_CD_GPIO\tIMX_GPIO_NR(5, 0)\n+#define USDHC1_WP_GPIO\tIMX_GPIO_NR(5, 1)\n+\n+int tq_bb_board_mmc_getcd(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC1_BASE_ADDR)\n+\t\tret = !gpio_get_value(USDHC1_CD_GPIO);\n+\n+\treturn ret;\n+}\n+\n+int tq_bb_board_mmc_getwp(struct mmc *mmc)\n+{\n+\tstruct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;\n+\tint ret = 0;\n+\n+\tif (cfg->esdhc_base == USDHC1_BASE_ADDR)\n+\t\tret = gpio_get_value(USDHC1_WP_GPIO);\n+\n+\treturn ret;\n+}\n+\n+static struct fsl_esdhc_cfg mba7_usdhc_cfg = {\n+\t.esdhc_base = USDHC1_BASE_ADDR,\n+\t.max_bus_width = 4,\n+};\n+\n+int tq_bb_board_mmc_init(struct bd_info *bis)\n+{\n+\timx_iomux_v3_setup_multiple_pads(mba7_usdhc1_pads,\n+\t\t\t\t\t ARRAY_SIZE(mba7_usdhc1_pads));\n+\tgpio_request(USDHC1_CD_GPIO, \"usdhc1-cd\");\n+\tgpio_request(USDHC1_WP_GPIO, \"usdhc1-wp\");\n+\tgpio_direction_input(USDHC1_CD_GPIO);\n+\tgpio_direction_input(USDHC1_WP_GPIO);\n+\n+\tmba7_usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);\n+\tif (fsl_esdhc_initialize(bis, &mba7_usdhc_cfg))\n+\t\tputs(\"Warning: failed to initialize SD\\n\");\n+\n+\treturn 0;\n+}\n+\n+int tq_bb_board_early_init_f(void)\n+{\n+\t/* iomux and setup of uart */\n+\tmba7_setup_iomuxc_uart();\n+\n+\treturn 0;\n+}\n+\n+/*\n+ * This is done per baseboard to allow different implementations\n+ */\n+void board_boot_order(u32 *spl_boot_list)\n+{\n+\tenum boot_device bd;\n+\t/*\n+\t * try to get sd card slots in order:\n+\t * eMMC: on Module\n+\t * -> therefore index 0 for bootloader\n+\t * index n in kernel (controller instance 3) -> patches needed for\n+\t * alias indexing\n+\t * SD1: on Mainboard\n+\t * index n in kernel (controller instance 1) -> patches needed for\n+\t * alias indexing\n+\t * we assume to have a kernel patch that will present mmcblk dev\n+\t * indexed like controller devs\n+\t */\n+\tputs(\"Boot: \");\n+\n+\tbd = get_boot_device();\n+\tswitch (bd) {\n+\tcase MMC3_BOOT:\n+\t\tputs(\"USDHC3(eMMC)\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_MMC1;\n+\t\tbreak;\n+\tcase SD1_BOOT:\n+\t\tputs(\"USDHC1(SD)\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_MMC2;\n+\t\tbreak;\n+\tcase QSPI_BOOT:\n+\t\tputs(\"QSPI\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_NOR;\n+\t\tbreak;\n+\tcase USB_BOOT:\n+\t\tputs(\"USB\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_BOARD;\n+\t\tbreak;\n+\tdefault:\n+\t\t/* Default - BOOT_DEVICE_MMC1 */\n+\t\tputs(\"WARN: unknown boot device, fallback to eMMC\\n\");\n+\t\tspl_boot_list[0] = BOOT_DEVICE_MMC1;\n+\t\tbreak;\n+\t}\n+}\n+\n+int board_fit_config_name_match(const char *name)\n+{\n+\tchar *config = NULL;\n+\n+\tif (is_cpu_type(MXC_CPU_MX7S))\n+\t\tconfig = \"imx7s-mba7\";\n+\telse if (is_cpu_type(MXC_CPU_MX7D))\n+\t\tconfig = \"imx7d-mba7\";\n+\n+\tif (strcmp(config, name))\n+\t\treturn -EINVAL;\n+\n+\tprintf(\"Device tree: %s\\n\", name);\n+\n+\treturn 0;\n+}\ndiff --git a/board/tq/tqma7/spl_tqma7_ram.c b/board/tq/tqma7/spl_tqma7_ram.c\nnew file mode 100644\nindex 00000000000..903df5d9d0f\n--- /dev/null\n+++ b/board/tq/tqma7/spl_tqma7_ram.c\n@@ -0,0 +1,171 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Alexander Feilke\n+ */\n+\n+#include <config.h>\n+#include <hang.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/mach-imx/iomux-v3.h>\n+#include <linux/sizes.h>\n+\n+#include \"../common/tq_som.h\"\n+\n+#define DDRC_RFSHTMG_512M 0x0020002B\n+#define DDRC_RFSHTMG_1G 0x00200045\n+#define DDRC_RFSHTMG_2G 0x0020005D\n+\n+#define DDRC_ADDRMAP1_512M 0x00161616\n+#define DDRC_ADDRMAP1_1G 0x00171717\n+#define DDRC_ADDRMAP1_2G 0x00181818\n+\n+#define DDRC_ADDRMAP6_512M 0x0F0F0404\n+#define DDRC_ADDRMAP6_1G 0x0F040404\n+#define DDRC_ADDRMAP6_2G 0x04040404\n+\n+#define DDR_PHY_OFFSET_RD_CON0_512M 0x0B0B0B0B\n+#define DDR_PHY_OFFSET_RD_CON0_1G 0x0B0B0B0B\n+#define DDR_PHY_OFFSET_RD_CON0_2G 0x0A0A0A0A\n+\n+#define DDR_PHY_OFFSET_WR_CON0_512M 0x06060606\n+#define DDR_PHY_OFFSET_WR_CON0_1G 0x06060606\n+#define DDR_PHY_OFFSET_WR_CON0_2G 0x04040404\n+\n+static void tqma7_ddr_exit_retention(void)\n+{\n+\t/* Clear then set bit30 to ensure exit from DDR retention */\n+\ttq_som_init_write_reg(0x30360388, 0x40000000);\n+\ttq_som_init_write_reg(0x30360384, 0x40000000);\n+}\n+\n+static void gpr_init(void)\n+{\n+\t/* reset default and enable GPR OCRAM EPDC */\n+\ttq_som_init_write_reg(0x30340004, 0x4F400005);\n+}\n+\n+static void tqma7_ccgr_init(void)\n+{\n+\ttq_som_init_write_reg(0x30384130, 0x00000000); /* CCM_CCGR19 */\n+\ttq_som_init_write_reg(0x30340020, 0x00000178); /* IOMUXC_GPR_GPR8 */\n+\ttq_som_init_write_reg(0x30384130, 0x00000002); /* CCM_CCGR19 */\n+\ttq_som_init_write_reg(0x30790018, 0x0000000f); /* DDR_PHY_LP_CON0 */\n+\n+\t/* wait for auto-ZQ calibration to complete */\n+\ttq_som_check_bits_set(0x307a0004, 0x1); /* DDRC_STAT */\n+}\n+\n+static void ddr_init_error(const char *msg)\n+{\n+\tpr_err(\"%s\", msg);\n+\thang();\n+}\n+\n+#define TQMA7_SELECT_DDR_VALUE(SIZE, NAME) \\\n+\t((SIZE) == SZ_512M ? NAME ## _512M : \\\n+\t((SIZE) == SZ_1G ? NAME ## _1G : \\\n+\t((SIZE) == SZ_2G ? NAME ## _2G : \\\n+\t(ddr_init_error(\"Invalid DDR RAM size detected\"), 0))))\n+\n+static void tqma7_init_ddr_controller(u32 size)\n+{\n+\tgpr_init();\n+\n+\t/* TQMa7 DDR config */\n+\t/* TQMa7x DRAM Timing REV0201A */\n+\t/* DCD Code i.MX7D/S 528 MHz 512 MByte Samsung K4B2G1646F */\n+\ttq_som_init_write_reg(0x30360070, 0x0070302C); /*CCM_ANALOG_PLL_DDRx*/\n+\ttq_som_init_write_reg(0x30360090, 0x00000000); /*CCM_ANALOG_PLL_NUM*/\n+\ttq_som_init_write_reg(0x30360070, 0x0060302C); /*CCM_ANALOG_PLL_DDRx*/\n+\n+\ttq_som_check_bits_set(0x30360070, 0x80000000);\n+\n+\ttq_som_init_write_reg(0x30391000, 0x00000002); /*SRC_DDRC_RCR*/\n+\ttq_som_init_write_reg(0x307a0000, 0x01040001); /*DDRC_MSTR*/\n+\ttq_som_init_write_reg(0x307a01a0, 0x80400003); /*DDRC_DFIUPD0*/\n+\ttq_som_init_write_reg(0x307a01a4, 0x00100020); /*DDRC_DFIUPD1*/\n+\ttq_som_init_write_reg(0x307a01a8, 0x80100004); /*DDRC_DFIUPD2*/\n+\ttq_som_init_write_reg(0x307a0064, TQMA7_SELECT_DDR_VALUE(size, DDRC_RFSHTMG));\n+\ttq_som_init_write_reg(0x307a0490, 0x00000001); /*DDRC_MP_PCTRL_0*/\n+\ttq_som_init_write_reg(0x307a00d0, 0x00020081); /*DDRC_INIT0*/\n+\ttq_som_init_write_reg(0x307a00d4, 0x00680000); /*DDRC_INIT1*/\n+\ttq_som_init_write_reg(0x307a00dc, 0x09300004); /*DDRC_INIT3*/\n+\ttq_som_init_write_reg(0x307a00e0, 0x00480000); /*DDRC_INIT4*/\n+\ttq_som_init_write_reg(0x307a00e4, 0x00100004); /*DDRC_INIT5*/\n+\ttq_som_init_write_reg(0x307a00f4, 0x0000033F); /*DDRC_RANKCTL*/\n+\ttq_som_init_write_reg(0x307a0100, 0x090E0809); /*DDRC_DRAMTMG0*/\n+\ttq_som_init_write_reg(0x307a0104, 0x0007020E); /*DDRC_DRAMTMG1*/\n+\ttq_som_init_write_reg(0x307a0108, 0x03040407); /*DDRC_DRAMTMG2*/\n+\ttq_som_init_write_reg(0x307a010c, 0x00002006); /*DDRC_DRAMTMG3*/\n+\ttq_som_init_write_reg(0x307a0110, 0x04020304); /*DDRC_DRAMTMG4*/\n+\ttq_som_init_write_reg(0x307a0114, 0x03030202); /*DDRC_DRAMTMG5*/\n+\ttq_som_init_write_reg(0x307a0120, 0x00000803); /*DDRC_DRAMTMG8*/\n+\ttq_som_init_write_reg(0x307a0180, 0x00800020); /*DDRC_ZQCTL0*/\n+\ttq_som_init_write_reg(0x307a0190, 0x02098204); /*DDRC_DFITMG0*/\n+\ttq_som_init_write_reg(0x307a0194, 0x00030303); /*DDRC_DFITMG1*/\n+\ttq_som_init_write_reg(0x307a0200, 0x0000001F); /*DDRC_ADDRMAP0*/\n+\ttq_som_init_write_reg(0x307a0204, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP1));\n+\ttq_som_init_write_reg(0x307a020C, 0x00000000); /*DDRC_ADDRMAP3*/\n+\ttq_som_init_write_reg(0x307a0210, 0x00000F0F); /*DDRC_ADDRMAP4*/\n+\ttq_som_init_write_reg(0x307a0214, 0x04040404); /*DDRC_ADDRMAP5*/\n+\ttq_som_init_write_reg(0x307a0218, TQMA7_SELECT_DDR_VALUE(size, DDRC_ADDRMAP6));\n+\ttq_som_init_write_reg(0x307a0240, 0x06000604); /*DDRC_ODTCFG*/\n+\ttq_som_init_write_reg(0x307a0244, 0x00000001); /*DDRC_ODTMAP*/\n+\ttq_som_init_write_reg(0x30391000, 0x00000000); /*SRC_DDRC_RCR*/\n+\ttq_som_init_write_reg(0x30790000, 0x17420F40); /*DDR_PHY_PHY_CON0*/\n+\ttq_som_init_write_reg(0x30790004, 0x10210100); /*DDR_PHY_PHY_CON1*/\n+\ttq_som_init_write_reg(0x30790010, 0x00060807); /*DDR_PHY_PHY_CON4*/\n+\ttq_som_init_write_reg(0x307900b0, 0x1010007E); /*DDR_PHY_MDLL_CON0*/\n+\ttq_som_init_write_reg(0x3079009c, 0x00000924); /*DDR_PHY_DRVDS_CON0*/\n+\n+\ttq_som_init_write_reg(0x30790020, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_RD_CON0));\n+\ttq_som_init_write_reg(0x30790030, TQMA7_SELECT_DDR_VALUE(size, DDR_PHY_OFFSET_WR_CON0));\n+\ttq_som_init_write_reg(0x30790050, 0x01000010); /*DDR_PHY_CMD_SDLL_CON0*/\n+\ttq_som_init_write_reg(0x30790050, 0x00000010); /*DDR_PHY_CMD_SDLL_CON0*/\n+\n+\ttq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/\n+\ttq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/\n+\ttq_som_init_write_reg(0x307900c0, 0x0C447306); /*DDR_PHY_ZQ_CON0*/\n+\n+\ttq_som_check_bits_set(0x307900c4, 0x1); /*ZQ Calibration is finished*/\n+\n+\ttq_som_init_write_reg(0x307900c0, 0x0C447304); /*DDR_PHY_ZQ_CON0*/\n+\ttq_som_init_write_reg(0x307900c0, 0x0C407304); /*DDR_PHY_ZQ_CON0*/\n+\n+\ttqma7_ccgr_init();\n+}\n+\n+void tq_som_ram_init(void)\n+{\n+\t/* RAM sizes need to be in descending order */\n+\tstatic const u32 ram_sizes[] = {\n+#if IS_ENABLED(CONFIG_TQMA7_RAM_2G)\n+\t\tSZ_2G,\n+#endif\n+#if IS_ENABLED(CONFIG_TQMA7_RAM_1G)\n+\t\tSZ_1G,\n+#endif\n+#if IS_ENABLED(CONFIG_TQMA7_RAM_512M)\n+\t\tSZ_512M,\n+#endif\n+\t};\n+\tint i;\n+\n+\tdebug(\"SPL: tqma7 iomux ....\\n\");\n+\ttqma7_ddr_exit_retention();\n+\n+\tfor (i = 0; i < ARRAY_SIZE(ram_sizes); i++) {\n+\t\ttqma7_init_ddr_controller(ram_sizes[i]);\n+\t\tif (tq_som_ram_check_size(ram_sizes[i]))\n+\t\t\tbreak;\n+\t}\n+\n+\tif (i < ARRAY_SIZE(ram_sizes)) {\n+\t\tdebug(\"SPL: tqma7 ddr init done ...\\n\");\n+\t} else {\n+\t\tpr_err(\"Error: Invalid DDR RAM size\\n\");\n+\t\thang();\n+\t}\n+}\ndiff --git a/board/tq/tqma7/tqma7.c b/board/tq/tqma7/tqma7.c\nnew file mode 100644\nindex 00000000000..30bd155713d\n--- /dev/null\n+++ b/board/tq/tqma7/tqma7.c\n@@ -0,0 +1,96 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Markus Niebel, Steffen Doster\n+ */\n+\n+#include <env.h>\n+#include <fdt_support.h>\n+#include <mtd_node.h>\n+#include <spi_flash.h>\n+#include <asm/bootm.h>\n+#include <asm/setup.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/imx-regs.h>\n+#include <asm/arch/sys_proto.h>\n+\n+#include \"../common/tq_bb.h\"\n+#include \"../common/tq_som.h\"\n+\n+DECLARE_GLOBAL_DATA_PTR;\n+\n+int dram_init(void)\n+{\n+\tgd->ram_size = imx_ddr_size();\n+\treturn 0;\n+}\n+\n+#if (!IS_ENABLED(CONFIG_SPL_BUILD))\n+\n+int board_init(void)\n+{\n+\t/* address of boot parameters */\n+\tgd->bd->bi_boot_params = PHYS_SDRAM + 0x100;\n+\n+\tif (IS_ENABLED(CONFIG_FSL_QSPI))\n+\t\tset_clk_qspi();\n+\n+\treturn tq_bb_board_init();\n+}\n+\n+static const char *tqma7_get_boardname(void)\n+{\n+\tswitch (get_cpu_type()) {\n+\tcase MXC_CPU_MX7S:\n+\t\treturn \"TQMa7S\";\n+\tcase MXC_CPU_MX7D:\n+\t\treturn \"TQMa7D\";\n+\tdefault:\n+\t\treturn \"??\";\n+\t};\n+}\n+\n+int board_late_init(void)\n+{\n+\tconst char *bname = tqma7_get_boardname();\n+\n+\tif (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) {\n+\t\tstruct tag_serialnr serialnr;\n+\n+\t\tget_board_serial(&serialnr);\n+\n+\t\tprintf(\"UID: %08x%08x\\n\", serialnr.high, serialnr.low);\n+\t}\n+\n+\tenv_set_runtime(\"board_name\", bname);\n+\n+\treturn tq_bb_board_late_init();\n+}\n+\n+static u32 tqma7_get_board_rev(void)\n+{\n+\t/* REV.0100 is unsupported */\n+\treturn 200;\n+}\n+\n+int checkboard(void)\n+{\n+\tprintf(\"Board: %s REV.%04u\\n\", tq_bb_get_boardname(), tqma7_get_board_rev());\n+\treturn 0;\n+}\n+\n+/*\n+ * Device Tree Support\n+ */\n+#if IS_ENABLED(CONFIG_OF_BOARD_SETUP) && IS_ENABLED(CONFIG_OF_LIBFDT)\n+\n+int ft_board_setup(void *blob, struct bd_info *bd)\n+{\n+\ttq_bb_ft_board_setup(blob, bd);\n+\n+\treturn 0;\n+}\n+#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */\n+\n+#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */\ndiff --git a/board/tq/tqma7/tqma7.cfg b/board/tq/tqma7/tqma7.cfg\nnew file mode 100644\nindex 00000000000..2e807d62348\n--- /dev/null\n+++ b/board/tq/tqma7/tqma7.cfg\n@@ -0,0 +1,26 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Markus Niebel, Steffen Doster\n+ *\n+ * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure\n+ * and create imximage boot image\n+ *\n+ * The syntax is taken as close as possible with the kwbimage\n+ */\n+\n+/* image version */\n+IMAGE_VERSION 2\n+\n+#include <config.h>\n+\n+/*\n+ * Set to sd even for QSPI boot on i.MX7, as i.MX7 uses offset 0x400 rather\n+ * than 0x1000 for QSPI\n+ */\n+BOOT_FROM sd\n+\n+#if IS_ENABLED(CONFIG_IMX_HAB)\n+CSF CONFIG_CSF_SIZE\n+#endif\ndiff --git a/board/tq/tqma7/tqma7.env b/board/tq/tqma7/tqma7.env\nnew file mode 100644\nindex 00000000000..857f16d11bb\n--- /dev/null\n+++ b/board/tq/tqma7/tqma7.env\n@@ -0,0 +1,35 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT\n+/*\n+ * Copyright (c) 2024-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Alexander Feilke\n+ *\n+ * TQMa7x environment\n+ */\n+\n+#include <env/tq/tq-imx-shared.env>\n+\n+board=tqma7\n+boot_os=bootz \"${kernel_addr_r}\" - \"${fdt_addr_r}\"\n+emmc_bootp_start=TQMA7_MMC_UBOOT_SECTOR_START\n+emmc_dev=0\n+fdt_addr_r=TQMA7_FDT_ADDRESS\n+fdtoverlay_addr_r=FDT_OVERLAY_ADDR\n+image=zImage\n+kernel_addr_r=CONFIG_SYS_LOAD_ADDR\n+netdev=eth0\n+pxefile_addr_r=CONFIG_SYS_LOAD_ADDR\n+ramdisk_addr_r=TQMA7_INITRD_ADDRESS\n+sd_dev=1\n+uboot=u-boot-with-spl.imx\n+uboot_mmc_start=TQMA7_MMC_UBOOT_SECTOR_START\n+uboot_mmc_size=TQMA7_MMC_UBOOT_SECTOR_COUNT\n+uboot_spi_sector_size=TQMA7_SPI_FLASH_SECTOR_SIZE\n+uboot_spi_start=TQMA7_SPI_UBOOT_START\n+uboot_spi_size=TQMA7_SPI_UBOOT_SIZE\n+\n+#ifdef CONFIG_FASTBOOT_UUU_SUPPORT\n+fastboot_partition_alias_all=CONFIG_FASTBOOT_FLASH_MMC_DEV:0\n+fastboot_raw_partition_bootloader=TQMA7_MMC_UBOOT_SECTOR_START TQMA7_MMC_UBOOT_SECTOR_COUNT mmcpart 1\n+fastbootcmd=fastboot usb 0\n+#endif\ndiff --git a/board/tq/tqma7/tqma7_mba7.c b/board/tq/tqma7/tqma7_mba7.c\nnew file mode 100644\nindex 00000000000..65c6c08771d\n--- /dev/null\n+++ b/board/tq/tqma7/tqma7_mba7.c\n@@ -0,0 +1,148 @@\n+// SPDX-License-Identifier: GPL-2.0-or-later\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Markus Niebel, Steffen Doster\n+ */\n+\n+#include <env.h>\n+#include <errno.h>\n+#include <asm/arch/clock.h>\n+#include <asm/arch/sys_proto.h>\n+#include <asm/arch-mx7/imx-regs.h>\n+#include <asm/mach-imx/boot_mode.h>\n+\n+#include \"../common/tq_bb.h\"\n+\n+const char *tq_bb_get_boardname(void)\n+{\n+\treturn \"MBa7x\";\n+}\n+\n+#if !IS_ENABLED(CONFIG_SPL_BUILD)\n+\n+static int mba7_setup_fec(int fec_id)\n+{\n+\tstruct iomuxc_gpr_base_regs *const iomuxc_gpr_regs =\n+\t\t(struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR;\n+\tint ret;\n+\n+\tswitch (fec_id) {\n+\tcase 0:\n+\t\t/* Use 125M anatop REF_CLK1 for ENET1, clear gpr1[13], gpr1[17]*/\n+\t\tclrsetbits_le32(&iomuxc_gpr_regs->gpr[1],\n+\t\t\t\tIOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_MASK |\n+\t\t\t\tIOMUXC_GPR_GPR1_GPR_ENET1_CLK_DIR_MASK, 0);\n+\t\tbreak;\n+\tcase 1:\n+\t\t/* Use 125M anatop REF_CLK2 for ENET2, clear gpr1[14], gpr1[18]*/\n+\t\tclrsetbits_le32(&iomuxc_gpr_regs->gpr[1],\n+\t\t\t\tIOMUXC_GPR_GPR1_GPR_ENET2_TX_CLK_SEL_MASK |\n+\t\t\t\tIOMUXC_GPR_GPR1_GPR_ENET2_CLK_DIR_MASK, 0);\n+\t\tbreak;\n+\tdefault:\n+\t\tprintf(\"FEC%d: unsupported\\n\", fec_id);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\tret = set_clk_enet(ENET_125MHZ);\n+\tif (ret)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+int tq_bb_board_init(void)\n+{\n+\tmba7_setup_fec(0);\n+\n+\tif (!is_cpu_type(MXC_CPU_MX7S))\n+\t\tmba7_setup_fec(1);\n+\n+\treturn 0;\n+}\n+\n+int tq_bb_board_late_init(void)\n+{\n+\tputs(\"Boot: \");\n+\n+\tif (is_boot_from_usb()) {\n+\t\tputs(\"USB\\n\");\n+\t\tenv_set_runtime(\"boot_dev\", \"mmc\");\n+\t\tenv_set_runtime(\"mmcdev\", \"0\");\n+\t\tenv_set_runtime(\"mmcblkdev\", \"0\");\n+\t} else {\n+\t\t/*\n+\t\t * try to get sd card slots in order:\n+\t\t * eMMC: on Module\n+\t\t * -> therefore index 0 for bootloader\n+\t\t * index n in kernel (controller instance 3) -> patches needed for\n+\t\t * alias indexing\n+\t\t * SD1: on Mainboard\n+\t\t * index n in kernel (controller instance 1) -> patches needed for\n+\t\t * alias indexing\n+\t\t * we assume to have a kernel patch that will present mmcblk dev\n+\t\t * indexed like controller devs\n+\t\t */\n+\t\tenum boot_device bd = get_boot_device();\n+\n+\t\tswitch (bd) {\n+\t\tcase MMC3_BOOT:\n+\t\t\tputs(\"USDHC3(eMMC)\\n\");\n+\t\t\tenv_set_runtime(\"boot_dev\", \"mmc\");\n+\t\t\tenv_set_runtime(\"mmcdev\", \"0\");\n+\t\t\tenv_set_runtime(\"mmcblkdev\", \"0\");\n+\t\t\tbreak;\n+\t\tcase SD1_BOOT:\n+\t\t\tputs(\"USDHC1(SD)\\n\");\n+\t\t\tenv_set_runtime(\"boot_dev\", \"mmc\");\n+\t\t\tenv_set_runtime(\"mmcdev\", \"1\");\n+\t\t\tenv_set_runtime(\"mmcblkdev\", \"1\");\n+\t\t\tbreak;\n+\t\tcase QSPI_BOOT:\n+\t\t\tputs(\"QSPI\\n\");\n+\t\t\tenv_set_runtime(\"boot_dev\", \"qspi\");\n+\t\t\tenv_set_runtime(\"mmcdev\", \"0\");\n+\t\t\tenv_set_runtime(\"mmcblkdev\", \"0\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tprintf(\"unhandled boot device %d\\n\", (int)bd);\n+\t\t\tenv_set_runtime(\"mmcdev\", \"0\");\n+\t\t\tenv_set_runtime(\"mmcblkdev\", \"0\");\n+\t\t}\n+\t}\n+\n+\tif (!env_get(\"fdtfile\")) {\n+\t\t/* provide default setting for fdtfile if nothing in env is set */\n+\n+\t\tswitch (get_cpu_type()) {\n+\t\tcase MXC_CPU_MX7S:\n+\t\t\tenv_set_runtime(\"fdtfile\", \"imx7s-mba7.dtb\");\n+\t\t\tbreak;\n+\t\tcase MXC_CPU_MX7D:\n+\t\t\tenv_set_runtime(\"fdtfile\", \"imx7d-mba7.dtb\");\n+\t\t\tbreak;\n+\t\tdefault:\n+\t\t\tdebug(\"unknown CPU\");\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+int board_mmc_get_env_dev(int devno)\n+{\n+\tswitch (devno) {\n+\tcase 2:\n+\t\t/* eMMC */\n+\t\treturn 0;\n+\tcase 0:\n+\t\t/* SD card */\n+\t\treturn 1;\n+\tdefault:\n+\t\t/* Unknown */\n+\t\treturn 0;\n+\t}\n+}\n+\n+#endif /* !IS_ENABLED(CONFIG_SPL_BUILD) */\ndiff --git a/include/configs/tqma7.h b/include/configs/tqma7.h\nnew file mode 100644\nindex 00000000000..6b77139f09d\n--- /dev/null\n+++ b/include/configs/tqma7.h\n@@ -0,0 +1,71 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Copyright (C) 2016 Freescale Semiconductor, Inc.\n+ *\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Markus Niebel, Steffen Doster\n+ *\n+ * Configuration settings for the TQ-Systems TQMa7x SOM\n+ */\n+\n+#ifndef __TQMA7_CONFIG_H\n+#define __TQMA7_CONFIG_H\n+\n+#include \"mx7_common.h\"\n+#include <linux/build_bug.h>\n+\n+/* MMC Configs */\n+#define CFG_SYS_FSL_ESDHC_ADDR\t0\n+\n+/*\n+ * 128 MiB offset as recommended in Linux' `Documentation/arch/arm/booting.rst`\n+ * TQMA7_FDT_ADDRESS = MMDC0_ARB_BASE_ADDR + 0x8000000\n+ */\n+#define TQMA7_FDT_ADDRESS\t\t0x88000000\n+/* FDT_OVERLAY_ADDR = (TQMA7_FDT_ADDRESS + SZ_256K) */\n+#define FDT_OVERLAY_ADDR\t\t0x88040000\n+/*\n+ * DTB is loaded at 128 MiB, so use just 16 MiB more\n+ * TQMA7_INITRD_ADDRESS = (TQMA7_FDT_ADDRESS + SZ_16M)\n+ */\n+#define TQMA7_INITRD_ADDRESS\t\t0x89000000\n+\n+#ifndef __ASSEMBLY__\n+\n+static_assert(TQMA7_FDT_ADDRESS == (MMDC0_ARB_BASE_ADDR + 0x8000000));\n+static_assert(FDT_OVERLAY_ADDR == (TQMA7_FDT_ADDRESS + SZ_256K));\n+static_assert(TQMA7_INITRD_ADDRESS == (TQMA7_FDT_ADDRESS + SZ_16M));\n+\n+#endif\n+\n+#define TQMA7_UBOOT_OFFSET\t\tSZ_1K\n+#define TQMA7_MMC_UBOOT_SECTOR_START\t0x2\n+#define TQMA7_MMC_UBOOT_SECTOR_COUNT\t0x7fe\n+#define TQMA7_SPI_FLASH_SECTOR_SIZE\tSZ_64K\n+#define TQMA7_SPI_UBOOT_START\t\t0x1000\n+#define TQMA7_SPI_UBOOT_SIZE\t\t0xf0000\n+\n+/* Physical Memory Map */\n+#define PHYS_SDRAM\t\tMMDC0_ARB_BASE_ADDR\n+\n+#define CFG_SYS_SDRAM_BASE\tPHYS_SDRAM\n+#define CFG_SYS_INIT_RAM_ADDR\tIRAM_BASE_ADDR\n+#define CFG_SYS_INIT_RAM_SIZE\tIRAM_SIZE\n+\n+/* u-boot.img base address for SPI-NOR boot */\n+#define CFG_SYS_UBOOT_BASE\t(QSPI0_ARB_BASE_ADDR + TQMA7_UBOOT_OFFSET + CONFIG_SPL_PAD_TO)\n+\n+/*\n+ * All the defines above are for the TQMa7x SoM\n+ *\n+ * Now include the baseboard specific configuration\n+ */\n+\n+#if IS_ENABLED(CONFIG_MBA7)\n+#include \"tqma7_mba7.h\"\n+#else\n+#error \"No baseboard for the TQMa7x SOM defined!\"\n+#endif\n+\n+#endif /* __TQMA7_CONFIG_H */\ndiff --git a/include/configs/tqma7_mba7.h b/include/configs/tqma7_mba7.h\nnew file mode 100644\nindex 00000000000..8b6ac6d4fc0\n--- /dev/null\n+++ b/include/configs/tqma7_mba7.h\n@@ -0,0 +1,16 @@\n+/* SPDX-License-Identifier: GPL-2.0-or-later */\n+/*\n+ * Copyright (c) 2016-2026 TQ-Systems GmbH <u-boot@ew.tq-group.com>,\n+ * D-82229 Seefeld, Germany.\n+ * Author: Markus Niebel, Steffen Doster\n+ *\n+ * Configuration settings for the TQ-Systems MBa7x carrier board for\n+ * TQMa7x module.\n+ */\n+\n+#ifndef __CONFIG_TQMA7_MBA7_H\n+#define __CONFIG_TQMA7_MBA7_H\n+\n+#define CFG_MXC_UART_BASE\tUART6_IPS_BASE_ADDR\n+\n+#endif /* __CONFIG_TQMA7_MBA7_H */\ndiff --git a/include/env/tq/spi.env b/include/env/tq/spi.env\nindex 47dcfea7d3f..242aa4da784 100644\n--- a/include/env/tq/spi.env\n+++ b/include/env/tq/spi.env\n@@ -20,4 +20,8 @@ update_uboot_spi=\n \t\tfi;\n \tfi;\n \n+#ifdef CONFIG_CMD_QSPIHDR\n+write_uboot_spi=qspihdr init ${loadaddr} ${filesize} safe;\n+#else\n write_uboot_spi=sf update \"${loadaddr}\" \"${uboot_spi_start}\" \"${filesize}\"\n+#endif\n", "prefixes": [ "v3", "6/8" ] }