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GET /api/patches/2216270/?format=api
{ "id": 2216270, "url": "http://patchwork.ozlabs.org/api/patches/2216270/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260326091130.321483-6-zhenzhong.duan@intel.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326091130.321483-6-zhenzhong.duan@intel.com>", "list_archive_url": null, "date": "2026-03-26T09:11:19", "name": "[v2,05/14] intel_iommu: Change pasid property from bool to uint8", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8cae9cf8bad90b9be23b790ee52b0e7fc764bc3c", "submitter": { "id": 81636, "url": "http://patchwork.ozlabs.org/api/people/81636/?format=api", "name": "Duan, Zhenzhong", "email": "zhenzhong.duan@intel.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260326091130.321483-6-zhenzhong.duan@intel.com/mbox/", "series": [ { "id": 497556, "url": "http://patchwork.ozlabs.org/api/series/497556/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=497556", "date": "2026-03-26T09:11:19", "name": "intel_iommu: Enable PASID support for passthrough device", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497556/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216270/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216270/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=Cv1BLycE;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists.gnu.org (lists.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhJ2W3ZPNz1yGL\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 20:12:35 +1100 (AEDT)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1w5gl4-0002mG-3g; Thu, 26 Mar 2026 05:12:06 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5gl3-0002m4-88\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 05:12:05 -0400", "from mgamail.intel.com ([198.175.65.17])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <zhenzhong.duan@intel.com>)\n id 1w5gl1-0003w6-JC\n for qemu-devel@nongnu.org; Thu, 26 Mar 2026 05:12:04 -0400", "from fmviesa001.fm.intel.com ([10.60.135.141])\n by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 02:12:03 -0700", "from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229])\n by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 26 Mar 2026 02:11:59 -0700" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple;\n d=intel.com; i=@intel.com; q=dns/txt; s=Intel;\n t=1774516324; x=1806052324;\n h=from:to:cc:subject:date:message-id:in-reply-to:\n references:mime-version:content-transfer-encoding;\n bh=gEO4mm7GUuNyoAnrhbBxoWB+2NKEH5s6i40gVa6WBEE=;\n b=Cv1BLycERgbHyzkKSSuM6ufRZMcVvyfb4aOirnfLQByabR12TRQq2C0T\n vy7hwEVXpOh1ZwUUc4uREjzSjbX7DbNRCZvy5+H+SgqNWW6SCuXm/tECx\n TMbq3Xz6Zfo5zwgbhDD0UijZJVXzRz5+5QxyGSDF+cPSmgCVnkUrlVB/u\n y4raG1zDFRK+w/cP7QG9gj0WFWoBqDO66wM3lWexRs3nfPfDru7v9EO7C\n lsFlCnfX/xWeSQJ3hNO/B4V252a5b6MwOqjXxDjNbrYNv8m7Rk5osayO2\n hazlrVif2cIlzr4TJfWDvFKLI918qi087Vgj7I3Z9voiTW1FJAQBAyMGX A==;", "X-CSE-ConnectionGUID": [ "oA5K9hKqTq24X/MguxfbHg==", "9tprphlWSHKHz6ua8uugNQ==" ], "X-CSE-MsgGUID": [ "fl2gjsGHR7meD/cci/qBAg==", "+7LL2XhMSUuFepMw2Q6Rtw==" ], "X-IronPort-AV": [ "E=McAfee;i=\"6800,10657,11740\"; a=\"75531340\"", "E=Sophos;i=\"6.23,141,1770624000\"; d=\"scan'208\";a=\"75531340\"", "E=Sophos;i=\"6.23,141,1770624000\"; d=\"scan'208\";a=\"248368576\"" ], "X-ExtLoop1": "1", "From": "Zhenzhong Duan <zhenzhong.duan@intel.com>", "To": "qemu-devel@nongnu.org", "Cc": "alex@shazbot.org, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com,\n jasowang@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com,\n skolothumtho@nvidia.com, joao.m.martins@oracle.com,\n clement.mathieu--drif@bull.com, kevin.tian@intel.com, yi.l.liu@intel.com,\n xudong.hao@intel.com, Zhenzhong Duan <zhenzhong.duan@intel.com>", "Subject": "[PATCH v2 05/14] intel_iommu: Change pasid property from bool to\n uint8", "Date": "Thu, 26 Mar 2026 05:11:19 -0400", "Message-ID": "<20260326091130.321483-6-zhenzhong.duan@intel.com>", "X-Mailer": "git-send-email 2.47.3", "In-Reply-To": "<20260326091130.321483-1-zhenzhong.duan@intel.com>", "References": "<20260326091130.321483-1-zhenzhong.duan@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=198.175.65.17;\n envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com", "X-Spam_score_int": "-43", "X-Spam_score": "-4.4", "X-Spam_bar": "----", "X-Spam_report": "(-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001,\n DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001,\n RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "'x-pasid-mode' is a bool property, we need an extra 'pss' property to\nrepresent PASID size supported. Because there is no any device in QEMU\nsupporting pasid capability yet, no guest could use the pasid feature\nuntil now, 'x-pasid-mode' takes no effect.\n\nSo instead of an extra 'pss' property we can use a single 'pasid'\nproperty of uint8 type to represent if pasid is supported and the PASID\nbits size. A value of N > 0 means pasid is supported and N - 1 is the\nvalue in PSS field in ECAP register.\n\nPASID bits size should also be no more than 20 bits according to PCI spec.\n\nSigned-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>\n---\n hw/i386/intel_iommu_internal.h | 2 +-\n include/hw/i386/intel_iommu.h | 2 +-\n hw/i386/intel_iommu.c | 11 +++++++++--\n 3 files changed, 11 insertions(+), 4 deletions(-)", "diff": "diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h\nindex 11a53aa369..db4f186a3e 100644\n--- a/hw/i386/intel_iommu_internal.h\n+++ b/hw/i386/intel_iommu_internal.h\n@@ -195,7 +195,7 @@\n #define VTD_ECAP_MHMV (15ULL << 20)\n #define VTD_ECAP_SRS (1ULL << 31)\n #define VTD_ECAP_NWFS (1ULL << 33)\n-#define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid */\n+#define VTD_ECAP_SET_PSS(x, v) ((x)->ecap = deposit64((x)->ecap, 35, 5, v))\n #define VTD_ECAP_PASID (1ULL << 40)\n #define VTD_ECAP_PDS (1ULL << 42)\n #define VTD_ECAP_SMTS (1ULL << 43)\ndiff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h\nindex e44ce31841..95c76015e4 100644\n--- a/include/hw/i386/intel_iommu.h\n+++ b/include/hw/i386/intel_iommu.h\n@@ -314,7 +314,7 @@ struct IntelIOMMUState {\n bool intr_eime; /* Extended interrupt mode enabled */\n OnOffAuto intr_eim; /* Toggle for EIM cabability */\n uint8_t aw_bits; /* Host/IOVA address width (in bits) */\n- bool pasid; /* Whether to support PASID */\n+ uint8_t pasid; /* PASID supported in bits, 0 if not */\n bool fs1gp; /* First Stage 1-GByte Page Support */\n \n /* Transient Mapping, Reserved(0) since VTD spec revision 3.2 */\ndiff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c\nindex f395fa248c..a7b676cd13 100644\n--- a/hw/i386/intel_iommu.c\n+++ b/hw/i386/intel_iommu.c\n@@ -4203,7 +4203,7 @@ static const Property vtd_properties[] = {\n DEFINE_PROP_BOOL(\"x-scalable-mode\", IntelIOMMUState, scalable_mode, FALSE),\n DEFINE_PROP_BOOL(\"x-flts\", IntelIOMMUState, fsts, FALSE),\n DEFINE_PROP_BOOL(\"snoop-control\", IntelIOMMUState, snoop_control, false),\n- DEFINE_PROP_BOOL(\"x-pasid-mode\", IntelIOMMUState, pasid, false),\n+ DEFINE_PROP_UINT8(\"pasid\", IntelIOMMUState, pasid, 0),\n DEFINE_PROP_BOOL(\"svm\", IntelIOMMUState, svm, false),\n DEFINE_PROP_BOOL(\"stale-tm\", IntelIOMMUState, stale_tm, false),\n DEFINE_PROP_BOOL(\"fs1gp\", IntelIOMMUState, fs1gp, true),\n@@ -5042,7 +5042,8 @@ static void vtd_cap_init(IntelIOMMUState *s)\n }\n \n if (s->pasid) {\n- s->ecap |= VTD_ECAP_PASID | VTD_ECAP_PSS;\n+ VTD_ECAP_SET_PSS(s, s->pasid - 1);\n+ s->ecap |= VTD_ECAP_PASID;\n }\n }\n \n@@ -5583,6 +5584,12 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp)\n return false;\n }\n \n+ if (s->pasid > PCI_EXT_CAP_PASID_MAX_WIDTH) {\n+ error_setg(errp, \"PASID width %d, exceed Max PASID Width %d allowed \"\n+ \"in PCI spec\", s->pasid, PCI_EXT_CAP_PASID_MAX_WIDTH);\n+ return false;\n+ }\n+\n if (s->svm) {\n if (!x86_iommu->dt_supported) {\n error_setg(errp, \"Need to set device IOTLB for svm\");\n", "prefixes": [ "v2", "05/14" ] }