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GET /api/patches/2216263/?format=api
{ "id": 2216263, "url": "http://patchwork.ozlabs.org/api/patches/2216263/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260326084302.2947190-1-vijay@linux.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326084302.2947190-1-vijay@linux.ibm.com>", "list_archive_url": null, "date": "2026-03-26T08:43:02", "name": "[v2] rs6000: Add POWER10 wide-immediate fusion patterns [PR108018]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3ce38b102f165ad4f33fb523b4945065a18eb1a0", "submitter": { "id": 91942, "url": "http://patchwork.ozlabs.org/api/people/91942/?format=api", "name": "Vijay Telidevulapalli", "email": "vijay@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260326084302.2947190-1-vijay@linux.ibm.com/mbox/", "series": [ { "id": 497552, "url": "http://patchwork.ozlabs.org/api/series/497552/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=497552", "date": "2026-03-26T08:43:02", "name": "[v2] rs6000: Add POWER10 wide-immediate fusion patterns [PR108018]", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/497552/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216263/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216263/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=ibm.com header.i=@ibm.com header.a=rsa-sha256\n header.s=pp1 header.b=MI2nUtSb;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=38.145.34.32; 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server2.sourceware.org", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc\n :content-transfer-encoding:date:from:message-id:mime-version\n :subject:to; s=pp1; bh=itIIYsETsUP62L3/TJ1RRoxMnk/nKXS/I8osMdghh\n KE=; b=MI2nUtSbl3LGFUZhHDEJRYGrUPGbbHGrlZEoz6LWxDFFw5zq7SZav92UL\n dakeDgJGTOTxoBJzF8A3uJGXtUVZcDC7iaUXQOtoroIt0X+0gjwf+A8Azfe7BMzv\n o7kRnVvAc9p4tsDRnhKVsA4u7bo+xKBsND95X2IM2JFusnkDfuzGvnrdgW24KRh7\n WvUtgbvNU8HlrHiBmQWgucq6AMTbQHCCVphnoOiwgnzawptHNd6yTv3JCp9cL3Kw\n EXv2Ox4p6uW0nbgzCVMMAdgTjRdR7YHpkLXN5GyyIwnUwDc9xJK4FCFfa8I52YBS\n E7/gmzWRbAsKyRUEoqA9z2O/KQKTA==", "From": "Vijay Shankar <vijay@linux.ibm.com>", "To": "gcc-patches@gcc.gnu.org, segher@kernel.crashing.org,\n jskumari@linux.ibm.com, avinashd@linux.ibm.com", "Cc": "jeevitha@linux.ibm.com, meissner@linux.ibm.com, kishan@linux.ibm.com,\n Vijay Shankar <vijay@linux.ibm.com>", "Subject": "[PATCH v2] rs6000: Add POWER10 wide-immediate fusion patterns\n [PR108018]", "Date": "Thu, 26 Mar 2026 03:43:02 -0500", "Message-ID": "<20260326084302.2947190-1-vijay@linux.ibm.com>", "X-Mailer": "git-send-email 2.47.3", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-GUID": "32J5DhnYdhMdA_JYOJbHiU2HCuW6QrTS", "X-Proofpoint-ORIG-GUID": "32J5DhnYdhMdA_JYOJbHiU2HCuW6QrTS", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzI2MDA2MCBTYWx0ZWRfX5NCYRHdk2lGy\n 2UHzgHsZZT1pSADfwVIND0lqcGCKm9HAy6lvGqRsV/B7U5EsWBU4BjsdrxAE9z8Z0EKuz4160ow\n ZFw/h/01YiIlfFtk/XW+yo7xJWJDTIXIweEvDXAPYUoAnwiSoFA8QHniKleznG5EZSbJ1yfrtu7\n WcFEpO1Zg2ebGfZMhsW+ejzt6pvPzvD/yHrTNZfYk2gUSb0N4pstnt4/Pxi+aWiR8IBjj1EIn7S\n T/EQ3ObDoAen3NUBrAlIdtzw63EJNA0bbSDwkJDNb2ugh5EDBRHpFNhYFmdKIOOSzuGM/l4Emir\n Tg3l6g6LnKdrt+it5oTwfPEAAqJ0xee1ChRVKRtyB0fCUHtTKY074sXbbyHt7wpsemJzfK+gu2E\n HuZx6evmpY+g0/0hrWpKc87pKcYspQbfnU0IcTbVNIQ+ktRDKgzcHJC835jG9/5CwLChqmh2ogS\n ebdcbWzu5DxiHNABgMw==", "X-Authority-Analysis": "v=2.4 cv=KbXfcAYD c=1 sm=1 tr=0 ts=69c4f19b cx=c_pps\n a=bLidbwmWQ0KltjZqbj+ezA==:117 a=bLidbwmWQ0KltjZqbj+ezA==:17\n a=Yq5XynenixoA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22\n a=RzCfie-kr_QcCd8fBx8p:22 a=VnNF1IyMAAAA:8 a=HWoq-wqtVqM-S9_n5RYA:9", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-03-26_02,2026-03-24_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n suspectscore=0 impostorscore=0 malwarescore=0 adultscore=0 clxscore=1015\n priorityscore=1501 bulkscore=0 lowpriorityscore=0 phishscore=0 spamscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2603050001 definitions=main-2603260060", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Hello,\n\nChanges form v1:\n * Cleaned up naming in rs6000.md\n * Cleaned up guards to be on same line.\n * Test case use \\m...\\M instead of relying on space\n\nThank you,\nVijay.\n\nPOWER10 has instruction fusion for addis+addi pairs. However,\nthe scheduler was breaking these pairs apart to optimize for\ndependency chains, losing the fusion benefit.\n\nThis patch implements \"fake\" instructions that represent both\ninstructions as a single pattern. This prevents the scheduler from\nreordering them while still generating the correct two-instruction\nsequence.\n\nExisting high/low patterns are guarded with !TARGET_POWER10 to\nprevent conflicts with the new fusion patterns.\n\nBootstrapped and tested on powerpc64le-linux-gnu with no regressions.\n\n2026-03-16 Vijay Shankar <vijay@linux.ibm.com>\n\ngcc/ChangeLog:\n\tPR target/108018\n\t* config/rs6000/rs6000.md (*largetoc_high): Add !TARGET_POWER10 guard.\n\t(*largetoc_high_aix<mode>): Likewise.\n\t(*largetoc_high_plus): Likewise.\n\t(*largetoc_high_plus_aix<mode>): Likewise.\n\t(*largetoc_low): Likewise.\n\t(*largetoc_low_aix<mode>): Likewise.\n\t(*largetocp10_aix<mode>): New define_insn.\n\t(*largetocp10_plus_aix<mode>): Likewise.\n\t(*largetocp10): Likewise.\n\t(*largetocp10_plus): Likewise.\n\t(*tocref<mode>): Add !TARGET_POWER10 guard.\n\ngcc/testsuite/ChangeLog:\n\tPR target/108018\n\t* gcc.target/powerpc/pr108018-1.c: New test.\n---\n gcc/config/rs6000/rs6000.md | 51 ++++++++++++++++---\n gcc/testsuite/gcc.target/powerpc/pr108018-1.c | 14 +++++\n 2 files changed, 58 insertions(+), 7 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/pr108018-1.c", "diff": "diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md\nindex 308955155..f8fe8f6de 100644\n--- a/gcc/config/rs6000/rs6000.md\n+++ b/gcc/config/rs6000/rs6000.md\n@@ -11283,7 +11283,7 @@\n \t (unspec [(match_operand:DI 1 \"\" \"\")\n \t\t (match_operand:DI 2 \"gpc_reg_operand\" \"b\")]\n \t\t UNSPEC_TOCREL)))]\n- \"TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"!TARGET_POWER10 && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n \"addis %0,%2,%1@toc@ha\")\n \n (define_insn \"*largetoc_high_aix<mode>\"\n@@ -11292,7 +11292,7 @@\n \t (unspec [(match_operand:P 1 \"\" \"\")\n \t\t (match_operand:P 2 \"gpc_reg_operand\" \"b\")]\n \t\t UNSPEC_TOCREL)))]\n- \"TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"!TARGET_POWER10 && TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n \"addis %0,%1@u(%2)\")\n \n (define_insn \"*largetoc_high_plus\"\n@@ -11303,7 +11303,7 @@\n \t\t (match_operand:DI 2 \"gpc_reg_operand\" \"b\")]\n \t\t UNSPEC_TOCREL)\n \t (match_operand:DI 3 \"add_cint_operand\" \"n\"))))]\n- \"TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"!TARGET_POWER10 && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n \"addis %0,%2,%1+%3@toc@ha\")\n \n (define_insn \"*largetoc_high_plus_aix<mode>\"\n@@ -11314,28 +11314,65 @@\n \t\t (match_operand:P 2 \"gpc_reg_operand\" \"b\")]\n \t\t UNSPEC_TOCREL)\n \t (match_operand:P 3 \"add_cint_operand\" \"n\"))))]\n- \"TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"!TARGET_POWER10 && TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n \"addis %0,%1+%3@u(%2)\")\n \n (define_insn \"*largetoc_low\"\n [(set (match_operand:DI 0 \"gpc_reg_operand\" \"=r\")\n (lo_sum:DI (match_operand:DI 1 \"gpc_reg_operand\" \"b\")\n \t (match_operand:DI 2 \"\" \"\")))]\n- \"TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"!TARGET_POWER10 && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n \"addi %0,%1,%2@l\")\n \n (define_insn \"*largetoc_low_aix<mode>\"\n [(set (match_operand:P 0 \"gpc_reg_operand\" \"=r\")\n (lo_sum:P (match_operand:P 1 \"gpc_reg_operand\" \"b\")\n \t (match_operand:P 2 \"\" \"\")))]\n- \"TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"!TARGET_POWER10 && TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n \"la %0,%2@l(%1)\")\n \n+(define_insn \"*largetocp10_aix<mode>\"\n+ [(set (match_operand:P 0 \"gpc_reg_operand\" \"=b\")\n+\t(unspec [(match_operand:P 1 \"\" \"\")\n+\t\t (match_operand:P 2 \"gpc_reg_operand\" \"b\")]\n+\t\tUNSPEC_TOCREL))]\n+ \"TARGET_POWER10 && TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"addis %0,%1@u(%2)\\;la %0,%1@l(%0)\")\n+\n+(define_insn \"*largetocp10_plus_aix<mode>\"\n+ [(set (match_operand:P 0 \"gpc_reg_operand\" \"=b\")\n+\t(plus:P\n+\t (unspec [(match_operand:P 1 \"\" \"\")\n+\t\t (match_operand:P 2 \"gpc_reg_operand\" \"b\")]\n+\t\t UNSPEC_TOCREL)\n+\t (match_operand:P 3 \"add_cint_operand\" \"n\")))]\n+ \"TARGET_POWER10 && TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"addis %0,%1+%3@u(%2)\\;la %0,%1+%3@l(%0)\")\n+\n+(define_insn \"*largetocp10\"\n+ [(set (match_operand:DI 0 \"gpc_reg_operand\" \"=b\")\n+\t(unspec [(match_operand:DI 1 \"\" \"\")\n+\t\t (match_operand:DI 2 \"gpc_reg_operand\" \"b\")]\n+\t\tUNSPEC_TOCREL))]\n+ \"TARGET_POWER10 && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"addis %0,%2,%1@toc@ha\\;addi %0,%0,%1@toc@l\")\n+\n+(define_insn \"*largetocp10_plus\"\n+ [(set (match_operand:DI 0 \"gpc_reg_operand\" \"=b\")\n+\t(plus:DI\n+\t (unspec [(match_operand:DI 1 \"\" \"\")\n+\t\t (match_operand:DI 2 \"gpc_reg_operand\" \"b\")]\n+\t\t UNSPEC_TOCREL)\n+\t (match_operand:DI 3 \"add_cint_operand\" \"n\")))]\n+ \"TARGET_POWER10 && TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL\"\n+ \"addis %0,%2,%1+%3@toc@ha\\;addi %0,%0,%1+%3@toc@l\")\n+\n (define_insn_and_split \"*tocref<mode>\"\n [(set (match_operand:P 0 \"gpc_reg_operand\" \"=b\")\n \t(match_operand:P 1 \"small_toc_ref\" \"R\"))]\n \"TARGET_TOC\n- && legitimate_constant_pool_address_p (operands[1], QImode, false)\"\n+ && legitimate_constant_pool_address_p (operands[1], QImode, false)\n+ && !TARGET_POWER10\"\n \"la %0,%a1\"\n \"&& TARGET_CMODEL != CMODEL_SMALL && reload_completed\"\n [(set (match_dup 0) (high:P (match_dup 1)))\ndiff --git a/gcc/testsuite/gcc.target/powerpc/pr108018-1.c b/gcc/testsuite/gcc.target/powerpc/pr108018-1.c\nnew file mode 100644\nindex 000000000..78ce4668a\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/pr108018-1.c\n@@ -0,0 +1,14 @@\n+/* { dg-do compile } */\n+/* { dg-skip-if \"\" { powerpc*-*-aix* } } */\n+/* { dg-options \"-O2 -mdejagnu-cpu=power10 -mno-pcrel\" } */\n+\n+/* Verify that the test case from PR108018 won't fail. */\n+\n+static int foo, bar;\n+\n+unsigned long test(void)\n+{\n+ return (unsigned long)&foo + (unsigned long)&bar;\n+}\n+\n+/* { dg-final { scan-assembler-times {\\maddis[^\\n]*\\n\\taddi\\M} 3 } } */\n", "prefixes": [ "v2" ] }