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GET /api/patches/2216262/?format=api
{ "id": 2216262, "url": "http://patchwork.ozlabs.org/api/patches/2216262/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/20260326083752.2946164-1-vijay@linux.ibm.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326083752.2946164-1-vijay@linux.ibm.com>", "list_archive_url": null, "date": "2026-03-26T08:37:52", "name": "[v5] rs6000: Reduces a multi-step comparison sequence to a single vcmpnez instruction [PR116004]", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "9b8e4d1e149d58442a676994ff3063cda4cef380", "submitter": { "id": 91942, "url": "http://patchwork.ozlabs.org/api/people/91942/?format=api", "name": "Vijay Telidevulapalli", "email": "vijay@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/20260326083752.2946164-1-vijay@linux.ibm.com/mbox/", "series": [ { "id": 497551, "url": "http://patchwork.ozlabs.org/api/series/497551/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=497551", "date": "2026-03-26T08:37:52", "name": "[v5] rs6000: Reduces a multi-step comparison sequence to a single vcmpnez instruction [PR116004]", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/497551/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216262/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216262/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ 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FGU9ah8f90twuAK13RtMez0oLo29A==", "From": "Vijay Shankar <vijay@linux.ibm.com>", "To": "gcc-patches@gcc.gnu.org, segher@kernel.crashing.org,\n jskumari@linux.ibm.com, avinashd@linux.ibm.com", "Cc": "jeevitha@linux.ibm.com, meissner@linux.ibm.com, kishan@linux.ibm.com,\n Vijay Shankar <vijay@linux.ibm.com>", "Subject": "[PATCH v5] rs6000: Reduces a multi-step comparison sequence to a\n single vcmpnez instruction [PR116004]", "Date": "Thu, 26 Mar 2026 03:37:52 -0500", "Message-ID": "<20260326083752.2946164-1-vijay@linux.ibm.com>", "X-Mailer": "git-send-email 2.47.3", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "X-TM-AS-GCONF": "00", "X-Proofpoint-ORIG-GUID": "CMVThXOmE0CfY2KatwjB4NFHoiKx4cIN", "X-Proofpoint-Spam-Details-Enc": "AW1haW4tMjYwMzI2MDA2MCBTYWx0ZWRfX8ybmgNtKtg0R\n DEywoUNPQGiua3L/EY19iQn/hXolFpr+piCIEbntnoZvj0yJLEGi3O8Yp+VldlpMogPYM23OJY/\n JcmMm5Hel6WfIXE5QCWeOjTg9paIS+b2cM95ntDrDLd4WGpeGCOrZEC5BzHPH5nnqYKjVZVSVJ1\n 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impostorscore=0\n malwarescore=0 lowpriorityscore=0 suspectscore=0 bulkscore=0\n priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc=\n route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2603050001\n definitions=main-2603260060", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "Changes from v4:\n * Update to use Use \\m...\\M in\nChanges from v3:\n\t* Added New testcase.\nChanges from v2:\n\t* Some formatting.\nChanges from v1:\n\t* Added more info to commit message fixed indentation.\n\nThis patch removes redundant vector compare instructions and logic\nfrom the vec_first_mismatch_or_eos_index intrinsic.\nCurrently, GCC generates extra vcmpneb instructions and additional\nmasking logic (xxland, xxlorc) to handle EOS and mismatch comparisons.\nHowever, a single vcmpnezb instruction already suffices, as it covers\nboth By eliminating the redundant comparisons (vcmpneb) and the\nassociated logic (xxland/xxlorc) we produce shorter,\nmore efficient code.\n\nBootstrapped and tested on powerpc64le-linux-gnu with no regressions.\n\n2025-10-22 Vijay Shankar <vijay@linux.ibm.com>\n\ngcc/ChangeLog:\n\tPR target/116004\n\t* config/rs6000/vsx.md (first_mismatch_or_eos_index): Remove redundant\n\temit_insns.\n\ngcc/testsuite/ChangeLog:\n\tPR target/116004\n\t* gcc.target/powerpc/pr116004.c: New Test.\n---\n gcc/config/rs6000/vsx.md | 22 ++------\n gcc/testsuite/gcc.target/powerpc/pr116004.c | 58 +++++++++++++++++++++\n 2 files changed, 61 insertions(+), 19 deletions(-)\n create mode 100644 gcc/testsuite/gcc.target/powerpc/pr116004.c", "diff": "diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md\nindex cfad9b8c6..3c2319a53 100644\n--- a/gcc/config/rs6000/vsx.md\n+++ b/gcc/config/rs6000/vsx.md\n@@ -5668,29 +5668,13 @@\n \"TARGET_P9_VECTOR\"\n {\n int sh;\n- rtx cmpz1_result = gen_reg_rtx (<MODE>mode);\n- rtx cmpz2_result = gen_reg_rtx (<MODE>mode);\n- rtx cmpz_result = gen_reg_rtx (<MODE>mode);\n- rtx not_cmpz_result = gen_reg_rtx (<MODE>mode);\n- rtx and_result = gen_reg_rtx (<MODE>mode);\n rtx result = gen_reg_rtx (<MODE>mode);\n- rtx vzero = gen_reg_rtx (<MODE>mode);\n-\n- /* Vector with zeros in elements that correspond to zeros in operands. */\n- emit_move_insn (vzero, CONST0_RTX (<MODE>mode));\n \n- emit_insn (gen_vcmpne<VSX_EXTRACT_WIDTH> (cmpz1_result, operands[1], vzero));\n- emit_insn (gen_vcmpne<VSX_EXTRACT_WIDTH> (cmpz2_result, operands[2], vzero));\n- emit_insn (gen_and<mode>3 (and_result, cmpz1_result, cmpz2_result));\n+ /* Vector with ones in elements that do not match or elements corresponding\n+ to zeros in operands. */\n \n- /* Vector with ones in elments that match. */\n- emit_insn (gen_vcmpnez<VSX_EXTRACT_WIDTH> (cmpz_result, operands[1],\n+ emit_insn (gen_vcmpnez<VSX_EXTRACT_WIDTH> (result, operands[1],\n operands[2]));\n- emit_insn (gen_one_cmpl<mode>2 (not_cmpz_result, cmpz_result));\n-\n- /* Create vector with ones in elements where there was a zero in one of\n- the source elements or the elements did not match. */\n- emit_insn (gen_nand<mode>3 (result, and_result, not_cmpz_result));\n sh = GET_MODE_SIZE (GET_MODE_INNER (<MODE>mode)) / 2;\n \n if (<MODE>mode == V16QImode)\ndiff --git a/gcc/testsuite/gcc.target/powerpc/pr116004.c b/gcc/testsuite/gcc.target/powerpc/pr116004.c\nnew file mode 100644\nindex 000000000..3f240c1c4\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/powerpc/pr116004.c\n@@ -0,0 +1,58 @@\n+/* { dg-do compile } */\n+/* { dg-options \"-mdejagnu-cpu=power9 -O2\" } */\n+/* { dg-final { scan-assembler-times {\\mvcmpnezb\\M} 2 } } */\n+/* { dg-final { scan-assembler-times {\\mvcmpnezh\\M} 2 } } */\n+/* { dg-final { scan-assembler-times {\\mvcmpnezw\\M} 2 } } */\n+/* { dg-final { scan-assembler-not {\\mvcmpneb\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mvcmpneh\\M} } } */\n+/* { dg-final { scan-assembler-not {\\mvcmpnew\\M} } } */\n+\n+#include <altivec.h>\n+#include <stdint.h>\n+\n+int main(void) {\n+ vector signed char char_src1, char_src2;\n+ vector unsigned char uchar_src1, uchar_src2;\n+ vector signed short short_src1, short_src2;\n+ vector unsigned short ushort_src1, ushort_src2;\n+ vector signed int int_src1, int_src2;\n+ vector unsigned int uint_src1, uint_src2;\n+\n+ volatile unsigned int r1, r2, r3, r4, r5, r6;\n+\n+ /* signed char */\n+ char_src1 = (vector signed char) {-1, 2, 3, 0, -5, 6, 7, 8,\n+ 9, 10, 11, 12, 13, 14, 15, 16};\n+ char_src2 = (vector signed char) {2, 3, 20, 0, -5, 6, 7, 8,\n+ 9, 10, 11, 12, 13, 14, 15, 16};\n+ r1 = vec_first_mismatch_or_eos_index(char_src1, char_src2);\n+\n+ /* unsigned char */\n+ uchar_src1 = (vector unsigned char) {1, 2, 3, 4, 5, 6, 7, 8,\n+ 9, 10, 11, 12, 13, 14, 15, 16};\n+ uchar_src2 = (vector unsigned char) {1, 0, 3, 4, 5, 6, 7, 8,\n+ 9, 10, 11, 12, 13, 14, 15, 16};\n+ r2 = vec_first_mismatch_or_eos_index(uchar_src1, uchar_src2);\n+\n+ /* signed short */\n+ short_src1 = (vector signed short) {-10, -20, 30, 40, 50, 60, 70, 80};\n+ short_src2 = (vector signed short) {-10, 20, 30, 40, 50, 60, 70, 80};\n+ r3 = vec_first_mismatch_or_eos_index(short_src1, short_src2);\n+\n+ /* unsigned short */\n+ ushort_src1 = (vector unsigned short) {10, 20, 30, 40, 50, 60, 70, 0};\n+ ushort_src2 = (vector unsigned short) {10, 20, 30, 40, 50, 60, 70, 80};\n+ r4 = vec_first_mismatch_or_eos_index(ushort_src1, ushort_src2);\n+\n+ /* signed int */\n+ int_src1 = (vector signed int) {1, 2, 3, 4};\n+ int_src2 = (vector signed int) {1, 20, 3, 4};\n+ r5 = vec_first_mismatch_or_eos_index(int_src1, int_src2);\n+\n+ /* unsigned int */\n+ uint_src1 = (vector unsigned int) {1, 2, 3, 0};\n+ uint_src2 = (vector unsigned int) {1, 2, 3, 0};\n+ r6 = vec_first_mismatch_or_eos_index(uint_src1, uint_src2);\n+\n+ return 0;\n+}\n", "prefixes": [ "v5" ] }