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GET /api/patches/2216249/?format=api
{ "id": 2216249, "url": "http://patchwork.ozlabs.org/api/patches/2216249/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326-pci-m2-e-v7-7-43324a7866e6@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326-pci-m2-e-v7-7-43324a7866e6@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-26T08:06:35", "name": "[v7,7/8] power: sequencing: pcie-m2: Add support for PCIe M.2 Key E connectors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6835202323c1a6547c3fe1c47e9723ddbfb71bf6", "submitter": { "id": 91277, "url": "http://patchwork.ozlabs.org/api/people/91277/?format=api", "name": "Manivannan Sadhasivam via B4 Relay", "email": "devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326-pci-m2-e-v7-7-43324a7866e6@oss.qualcomm.com/mbox/", "series": [ { "id": 497544, "url": "http://patchwork.ozlabs.org/api/series/497544/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497544", "date": "2026-03-26T08:06:33", "name": "Add support for handling PCIe M.2 Key E connectors in devicetree", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/497544/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216249/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216249/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51157-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=mdUouJFO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-51157-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"mdUouJFO\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fhGjP577Kz1y1G\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 19:12:41 +1100 (AEDT)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id C907F30C961E\n\tfor <incoming@patchwork.ozlabs.org>; Thu, 26 Mar 2026 08:07:02 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 447373BC67C;\n\tThu, 26 Mar 2026 08:06:42 +0000 (UTC)", "from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 2E19B3AEF58;\n\tThu, 26 Mar 2026 08:06:41 +0000 (UTC)", "by smtp.kernel.org (Postfix) with ESMTPS id E41F6C2BC87;\n\tThu, 26 Mar 2026 08:06:40 +0000 (UTC)", "from aws-us-west-2-korg-lkml-1.web.codeaurora.org\n (localhost.localdomain [127.0.0.1])\n\tby smtp.lore.kernel.org (Postfix) with ESMTP id DACB1106F2F4;\n\tThu, 26 Mar 2026 08:06:40 +0000 (UTC)" ], "ARC-Seal": "i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774512401; cv=none;\n b=ciubWUSrznWY8uoo/ft0ywR7jDWTdRAHrNkb8nDvn7larZyw2IuRosNrqQnyZdnnzrm9SL/Vg3YSK1CPVKF0hwmF33tzTLLTamlmAzp4a6RcL0T7yQw0jNElW3Fjg2po3cEKheW9MK9arZbrgDSX5t9yJnTCTtUUkQ5gz0/6kxw=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774512401; c=relaxed/simple;\n\tbh=QPg5ucT2J9JR6E3rS7caTqzm372tAM2YlgwRdg7/hwg=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=MKaiSzj8oT6OmqUO/9Dhf6Lnu58lTCpZpScdser/ecWsHQC4sSe1kSzmZRIOD365cmRbhhkFG0IalAsg0Gicvek6Y8exZ9cSYPPTtvwCsIse7Z054G0wKODjyDh2rQIcKwpE2GtUpVSXpczN4S1g6024ELWGfzEEnJop29adxPU=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=mdUouJFO; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774512401;\n\tbh=QPg5ucT2J9JR6E3rS7caTqzm372tAM2YlgwRdg7/hwg=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=mdUouJFOe7iVby+PU1+ECWuAy6xXL4uRrYoOlf2oK9U68N9lM0OlJfevgSOMFfrMx\n\t x5FKszNh2kFIBPGd2yFGfb8nriW4UE7SPk9R+gjKm8ndGP2bu3J0l1qAEwPzP2W5DO\n\t 0CNi4DiOvewbTJQ0a6QTgkmviXyrqwOR8w6QviSGTebdqDw1oJcAVrNyMYHtcPj2+g\n\t WINP5kMJIjkiaDEyuxci+0zroEGoBQtd73rFLU9KTaPz7VM74BY/Ao/qthBcFpwgIK\n\t 7SC4Vk81T7ey/Ky+B0rZ5PsB5mBHvK35CdV2s9s6JwPiJDgWQM54m9TV/OCeDfHPNl\n\t 5q6ej8qzEChhQ==", "From": "Manivannan Sadhasivam via B4 Relay\n <devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org>", "Date": "Thu, 26 Mar 2026 13:36:35 +0530", "Subject": "[PATCH v7 7/8] power: sequencing: pcie-m2: Add support for PCIe\n M.2 Key E connectors", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260326-pci-m2-e-v7-7-43324a7866e6@oss.qualcomm.com>", "References": "<20260326-pci-m2-e-v7-0-43324a7866e6@oss.qualcomm.com>", "In-Reply-To": "<20260326-pci-m2-e-v7-0-43324a7866e6@oss.qualcomm.com>", "To": "Rob Herring <robh@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Jiri Slaby <jirislaby@kernel.org>, Nathan Chancellor <nathan@kernel.org>,\n Nicolas Schier <nicolas.schier@linux.dev>, Hans de Goede <hansg@kernel.org>,\n =?utf-8?q?Ilpo_J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>,\n Mark Pearson <mpearson-lenovo@squebb.ca>,\n \"Derek J. Clark\" <derekjohn.clark@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Marcel Holtmann <marcel@holtmann.org>,\n Luiz Augusto von Dentz <luiz.dentz@gmail.com>,\n Bartosz Golaszewski <brgl@bgdev.pl>,\n Andy Shevchenko <andriy.shevchenko@linux.intel.com>,\n Bartosz Golaszewski <brgl@kernel.org>", "Cc": "linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-kbuild@vger.kernel.org, platform-driver-x86@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-bluetooth@vger.kernel.org,\n linux-pm@vger.kernel.org, Stephan Gerhold <stephan.gerhold@linaro.org>,\n Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,\n linux-acpi@vger.kernel.org,\n Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>,\n Hans de Goede <johannes.goede@oss.qualcomm.com>", "X-Mailer": "b4 0.15.0", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=6901;\n i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id;\n bh=HRGptE1JIyA395dlxkM3raRO8gPG2oSfeqDUBhjL6YY=;\n b=kA0DAAoBVZ8R5v6RzvUByyZiAGnE6Q2hXkEob2zwJaf4tJlYmf+8mDScgkgd22Ujhq84tXZHo\n IkBMwQAAQoAHRYhBGelQyqBSMvYpFgnl1WfEeb+kc71BQJpxOkNAAoJEFWfEeb+kc710RYIAJdV\n OwNYBVHVoy340ClaeQUqbv3iuxJutNdyMvn2I3K6Otq8/3Te+1dtfB8VGt4uysULp4Js49LvewG\n L9cgRMIwX1J+zcxbdtSieXfE0LOp3F4ZBz3UlIA0KPvSHxbn297ojpePAK8pteYhoSyve1uKjEt\n tjDDALlqDHBy7NVcEEMt+5l+Gc471FWutJrjqaNiZt0aKrMNMAf5CMZze8WKyI7MB9E05WrDKcO\n 5ujoWawieDxUob74VuzWB6iMVudd5JAWbbcwairLzWqTTwkltPO3mhC3D/s4gsXzaGCiLNFG42d\n Cxg/cgaF8oIreBPDXwiTfSpIbUjWVtzLNTM44fg=", "X-Developer-Key": "i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp;\n fpr=C668AEC3C3188E4C611465E7488550E901166008", "X-Endpoint-Received": "by B4 Relay for\n manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461", "X-Original-From": "Manivannan Sadhasivam\n <manivannan.sadhasivam@oss.qualcomm.com>", "Reply-To": "manivannan.sadhasivam@oss.qualcomm.com" }, "content": "From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>\n\nAdd support for handling the power sequence of the PCIe M.2 Key E\nconnectors. These connectors are used to attach the Wireless Connectivity\ndevices to the host machine including combinations of WiFi, BT, NFC using\ninterfaces such as PCIe/SDIO for WiFi, USB/UART for BT and I2C for NFC.\n\nCurrently, this driver supports only the PCIe interface for WiFi and UART\ninterface for BT. The driver also only supports driving the 3.3v/1.8v power\nsupplies and W_DISABLE{1/2}# GPIOs. The optional signals of the Key E\nconnectors are not currently supported.\n\nTested-by: Hans de Goede <johannes.goede@oss.qualcomm.com> # ThinkPad T14s gen6 (arm64)\nSigned-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>\n---\n drivers/power/sequencing/pwrseq-pcie-m2.c | 107 ++++++++++++++++++++++++++++--\n 1 file changed, 101 insertions(+), 6 deletions(-)", "diff": "diff --git a/drivers/power/sequencing/pwrseq-pcie-m2.c b/drivers/power/sequencing/pwrseq-pcie-m2.c\nindex d31a7dd8b35c..3507cdcb1e7b 100644\n--- a/drivers/power/sequencing/pwrseq-pcie-m2.c\n+++ b/drivers/power/sequencing/pwrseq-pcie-m2.c\n@@ -5,10 +5,13 @@\n */\n \n #include <linux/device.h>\n+#include <linux/delay.h>\n+#include <linux/gpio/consumer.h>\n #include <linux/mod_devicetable.h>\n #include <linux/module.h>\n #include <linux/of.h>\n #include <linux/of_graph.h>\n+#include <linux/of_platform.h>\n #include <linux/platform_device.h>\n #include <linux/pwrseq/provider.h>\n #include <linux/regulator/consumer.h>\n@@ -25,16 +28,18 @@ struct pwrseq_pcie_m2_ctx {\n \tstruct regulator_bulk_data *regs;\n \tsize_t num_vregs;\n \tstruct notifier_block nb;\n+\tstruct gpio_desc *w_disable1_gpio;\n+\tstruct gpio_desc *w_disable2_gpio;\n };\n \n-static int pwrseq_pcie_m2_m_vregs_enable(struct pwrseq_device *pwrseq)\n+static int pwrseq_pcie_m2_vregs_enable(struct pwrseq_device *pwrseq)\n {\n \tstruct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);\n \n \treturn regulator_bulk_enable(ctx->num_vregs, ctx->regs);\n }\n \n-static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq)\n+static int pwrseq_pcie_m2_vregs_disable(struct pwrseq_device *pwrseq)\n {\n \tstruct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);\n \n@@ -43,18 +48,84 @@ static int pwrseq_pcie_m2_m_vregs_disable(struct pwrseq_device *pwrseq)\n \n static const struct pwrseq_unit_data pwrseq_pcie_m2_vregs_unit_data = {\n \t.name = \"regulators-enable\",\n-\t.enable = pwrseq_pcie_m2_m_vregs_enable,\n-\t.disable = pwrseq_pcie_m2_m_vregs_disable,\n+\t.enable = pwrseq_pcie_m2_vregs_enable,\n+\t.disable = pwrseq_pcie_m2_vregs_disable,\n };\n \n-static const struct pwrseq_unit_data *pwrseq_pcie_m2_m_unit_deps[] = {\n+static const struct pwrseq_unit_data *pwrseq_pcie_m2_unit_deps[] = {\n \t&pwrseq_pcie_m2_vregs_unit_data,\n \tNULL\n };\n \n+static int pwrseq_pci_m2_e_uart_enable(struct pwrseq_device *pwrseq)\n+{\n+\tstruct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);\n+\n+\treturn gpiod_set_value_cansleep(ctx->w_disable2_gpio, 0);\n+}\n+\n+static int pwrseq_pci_m2_e_uart_disable(struct pwrseq_device *pwrseq)\n+{\n+\tstruct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);\n+\n+\treturn gpiod_set_value_cansleep(ctx->w_disable2_gpio, 1);\n+}\n+\n+static const struct pwrseq_unit_data pwrseq_pcie_m2_e_uart_unit_data = {\n+\t.name = \"uart-enable\",\n+\t.deps = pwrseq_pcie_m2_unit_deps,\n+\t.enable = pwrseq_pci_m2_e_uart_enable,\n+\t.disable = pwrseq_pci_m2_e_uart_disable,\n+};\n+\n+static int pwrseq_pci_m2_e_pcie_enable(struct pwrseq_device *pwrseq)\n+{\n+\tstruct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);\n+\n+\treturn gpiod_set_value_cansleep(ctx->w_disable1_gpio, 0);\n+}\n+\n+static int pwrseq_pci_m2_e_pcie_disable(struct pwrseq_device *pwrseq)\n+{\n+\tstruct pwrseq_pcie_m2_ctx *ctx = pwrseq_device_get_drvdata(pwrseq);\n+\n+\treturn gpiod_set_value_cansleep(ctx->w_disable1_gpio, 1);\n+}\n+\n+static const struct pwrseq_unit_data pwrseq_pcie_m2_e_pcie_unit_data = {\n+\t.name = \"pcie-enable\",\n+\t.deps = pwrseq_pcie_m2_unit_deps,\n+\t.enable = pwrseq_pci_m2_e_pcie_enable,\n+\t.disable = pwrseq_pci_m2_e_pcie_disable,\n+};\n+\n static const struct pwrseq_unit_data pwrseq_pcie_m2_m_pcie_unit_data = {\n \t.name = \"pcie-enable\",\n-\t.deps = pwrseq_pcie_m2_m_unit_deps,\n+\t.deps = pwrseq_pcie_m2_unit_deps,\n+};\n+\n+static int pwrseq_pcie_m2_e_pwup_delay(struct pwrseq_device *pwrseq)\n+{\n+\t/*\n+\t * FIXME: This delay is only required for some Qcom WLAN/BT cards like\n+\t * WCN7850 and not for all devices. But currently, there is no way to\n+\t * identify the device model before enumeration.\n+\t */\n+\tmsleep(50);\n+\n+\treturn 0;\n+}\n+\n+static const struct pwrseq_target_data pwrseq_pcie_m2_e_uart_target_data = {\n+\t.name = \"uart\",\n+\t.unit = &pwrseq_pcie_m2_e_uart_unit_data,\n+\t.post_enable = pwrseq_pcie_m2_e_pwup_delay,\n+};\n+\n+static const struct pwrseq_target_data pwrseq_pcie_m2_e_pcie_target_data = {\n+\t.name = \"pcie\",\n+\t.unit = &pwrseq_pcie_m2_e_pcie_unit_data,\n+\t.post_enable = pwrseq_pcie_m2_e_pwup_delay,\n };\n \n static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = {\n@@ -62,11 +133,21 @@ static const struct pwrseq_target_data pwrseq_pcie_m2_m_pcie_target_data = {\n \t.unit = &pwrseq_pcie_m2_m_pcie_unit_data,\n };\n \n+static const struct pwrseq_target_data *pwrseq_pcie_m2_e_targets[] = {\n+\t&pwrseq_pcie_m2_e_pcie_target_data,\n+\t&pwrseq_pcie_m2_e_uart_target_data,\n+\tNULL\n+};\n+\n static const struct pwrseq_target_data *pwrseq_pcie_m2_m_targets[] = {\n \t&pwrseq_pcie_m2_m_pcie_target_data,\n \tNULL\n };\n \n+static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_e_of_data = {\n+\t.targets = pwrseq_pcie_m2_e_targets,\n+};\n+\n static const struct pwrseq_pcie_m2_pdata pwrseq_pcie_m2_m_of_data = {\n \t.targets = pwrseq_pcie_m2_m_targets,\n };\n@@ -125,6 +206,16 @@ static int pwrseq_pcie_m2_probe(struct platform_device *pdev)\n \t\treturn dev_err_probe(dev, ret,\n \t\t\t\t \"Failed to get all regulators\\n\");\n \n+\tctx->w_disable1_gpio = devm_gpiod_get_optional(dev, \"w-disable1\", GPIOD_OUT_HIGH);\n+\tif (IS_ERR(ctx->w_disable1_gpio))\n+\t\treturn dev_err_probe(dev, PTR_ERR(ctx->w_disable1_gpio),\n+\t\t\t\t \"Failed to get the W_DISABLE_1# GPIO\\n\");\n+\n+\tctx->w_disable2_gpio = devm_gpiod_get_optional(dev, \"w-disable2\", GPIOD_OUT_HIGH);\n+\tif (IS_ERR(ctx->w_disable2_gpio))\n+\t\treturn dev_err_probe(dev, PTR_ERR(ctx->w_disable2_gpio),\n+\t\t\t\t \"Failed to get the W_DISABLE_2# GPIO\\n\");\n+\n \tctx->num_vregs = ret;\n \n \tret = devm_add_action_or_reset(dev, pwrseq_pcie_m2_free_regulators, ctx);\n@@ -150,6 +241,10 @@ static const struct of_device_id pwrseq_pcie_m2_of_match[] = {\n \t\t.compatible = \"pcie-m2-m-connector\",\n \t\t.data = &pwrseq_pcie_m2_m_of_data,\n \t},\n+\t{\n+\t\t.compatible = \"pcie-m2-e-connector\",\n+\t\t.data = &pwrseq_pcie_m2_e_of_data,\n+\t},\n \t{ }\n };\n MODULE_DEVICE_TABLE(of, pwrseq_pcie_m2_of_match);\n", "prefixes": [ "v7", "7/8" ] }