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GET /api/patches/2216235/?format=api
{ "id": 2216235, "url": "http://patchwork.ozlabs.org/api/patches/2216235/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326-pci-m2-e-v7-5-43324a7866e6@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260326-pci-m2-e-v7-5-43324a7866e6@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-03-26T08:06:33", "name": "[v7,5/8] dt-bindings: connector: Add PCIe M.2 Mechanical Key E connector", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "2366c7fbfc07a1d3ff3c7183b51473d68d123dbf", "submitter": { "id": 91277, "url": "http://patchwork.ozlabs.org/api/people/91277/?format=api", "name": "Manivannan Sadhasivam via B4 Relay", "email": "devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260326-pci-m2-e-v7-5-43324a7866e6@oss.qualcomm.com/mbox/", "series": [ { "id": 497544, "url": "http://patchwork.ozlabs.org/api/series/497544/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=497544", "date": "2026-03-26T08:06:33", "name": "Add support for handling PCIe M.2 Key E connectors in devicetree", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/497544/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216235/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216235/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-51155-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Gc86cfew;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1774512401; cv=none;\n b=kyivMnUFtiJTSpPwVCzGSxMKM4VIA+4fy/dsxkvh2Z6VeIouAEQjbHInro53t0aWQ7IQGHthPQ0EZyWo6CPBPzKTT6JLDxEvwkdyklIBo2UF2BK+neIYVxpL0F2p8QQpC2jpP6xOb40dZiWtN/0pAjcD5PmecCz+tAuEoVbV+KI=", "ARC-Message-Signature": "i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1774512401; c=relaxed/simple;\n\tbh=4ElZ70nPvlA5elMccGJEIatlJln9cC89vMOCeZptGYc=;\n\th=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References:\n\t In-Reply-To:To:Cc;\n b=soI3K9BgUTy0vRDDSButBOZsChm6NQsqd/WVD5PGhXOhw+zAvEFBUNdSOIhsKe5uu1DL1LrseEcORgGb6bsD9fnC2qsr+TsQGdk48FMRSv+zzWiWAKiL/X/xCia598J+KkQd8Cam3G8nd3KA1cntbfum2tvOhLLpRbpk75owXM0=", "ARC-Authentication-Results": "i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=Gc86cfew; arc=none smtp.client-ip=10.30.226.201", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1774512400;\n\tbh=4ElZ70nPvlA5elMccGJEIatlJln9cC89vMOCeZptGYc=;\n\th=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From;\n\tb=Gc86cfewGJKycobuexuDpcsxMRn3W1xG2u0ua1YvDlCauqFh7ug1oI/0+kKz9BscX\n\t V4Al4lYAlTqSElijd+IP7WD2UKtAj0SYDnb7yxoN20ooDt5sa1klyHLp+NSn6M8h+V\n\t uGmklA8AQkfDr06j890pPruDl3oMv1Gc574OL6Cgk9XYGiQLpVFmUYNmJ9dZgR0WLK\n\t IFdeJUN1lFZW1PA8cXQ9PGYQdyG0rNHOhakELJE3s1NFJRa3Y7LbsjIg6mS7pdehVx\n\t hKtZL3GujBw1bM/8IrIFE48dec1bkx0shHIzr04Nk+sF/pVaKkMg6WQes2omf80IoH\n\t HpocZWm1oDJTA==", "From": "Manivannan Sadhasivam via B4 Relay\n <devnull+manivannan.sadhasivam.oss.qualcomm.com@kernel.org>", "Date": "Thu, 26 Mar 2026 13:36:33 +0530", "Subject": "[PATCH v7 5/8] dt-bindings: connector: Add PCIe M.2 Mechanical Key\n E connector", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260326-pci-m2-e-v7-5-43324a7866e6@oss.qualcomm.com>", "References": "<20260326-pci-m2-e-v7-0-43324a7866e6@oss.qualcomm.com>", "In-Reply-To": "<20260326-pci-m2-e-v7-0-43324a7866e6@oss.qualcomm.com>", "To": "Rob Herring <robh@kernel.org>,\n Greg Kroah-Hartman <gregkh@linuxfoundation.org>,\n Jiri Slaby <jirislaby@kernel.org>, Nathan Chancellor <nathan@kernel.org>,\n Nicolas Schier <nicolas.schier@linux.dev>, Hans de Goede <hansg@kernel.org>,\n =?utf-8?q?Ilpo_J=C3=A4rvinen?= <ilpo.jarvinen@linux.intel.com>,\n Mark Pearson <mpearson-lenovo@squebb.ca>,\n \"Derek J. Clark\" <derekjohn.clark@gmail.com>,\n Manivannan Sadhasivam <mani@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>,\n Conor Dooley <conor+dt@kernel.org>, Marcel Holtmann <marcel@holtmann.org>,\n Luiz Augusto von Dentz <luiz.dentz@gmail.com>,\n Bartosz Golaszewski <brgl@bgdev.pl>,\n Andy Shevchenko <andriy.shevchenko@linux.intel.com>,\n Bartosz Golaszewski <brgl@kernel.org>", "Cc": "linux-serial@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-kbuild@vger.kernel.org, platform-driver-x86@vger.kernel.org,\n linux-pci@vger.kernel.org, devicetree@vger.kernel.org,\n linux-arm-msm@vger.kernel.org, linux-bluetooth@vger.kernel.org,\n linux-pm@vger.kernel.org, Stephan Gerhold <stephan.gerhold@linaro.org>,\n Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>,\n linux-acpi@vger.kernel.org,\n Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>", "X-Mailer": "b4 0.15.0", "X-Developer-Signature": "v=1; a=openpgp-sha256; l=8239;\n i=manivannan.sadhasivam@oss.qualcomm.com; h=from:subject:message-id;\n bh=slhKwJysU03VOabgWllbdo/9+CasPWvvWWbRPmMU8Iw=;\n b=owEBbQGS/pANAwAKAVWfEeb+kc71AcsmYgBpxOkNpfiNlrcUD/nA8Hs2SeqKsUnqiWp9NCgqJ\n 2aoxNQx9GqJATMEAAEKAB0WIQRnpUMqgUjL2KRYJ5dVnxHm/pHO9QUCacTpDQAKCRBVnxHm/pHO\n 9S6mCACgacV0mPyQuXRwv/xYMOwIPS7a4P7C8CQjR0vQiXyMuAmmv5LPV9I0mqfQYxMysYT/wTX\n tLgGTKU4rZ9guFDxpTdwbHkcq0r74/cCx8+kwHyC5P2UDU/ZYC7o4HeZW1d87P8pLCXCCJB8qlO\n hAOA4OsMI0I2v8cPE3TbCbKjhN2jPTOKyWehqSWcV4rYL+ro/k1xdgJ6EJ7kOPr399td6FjKl1k\n DPGdJfPJiJEf92XzCo7vUOiCBKz4+vVKRqAwKARFJ7m5NsHCK2DhYzF0assIG6yShQ26EijiFmf\n t9G43nNWYyYfNyfOQk1gsk6NCbkW1o4L8PdB1pen5T0Zo0uX", "X-Developer-Key": "i=manivannan.sadhasivam@oss.qualcomm.com; a=openpgp;\n fpr=C668AEC3C3188E4C611465E7488550E901166008", "X-Endpoint-Received": "by B4 Relay for\n manivannan.sadhasivam@oss.qualcomm.com/default with auth_id=461", "X-Original-From": "Manivannan Sadhasivam\n <manivannan.sadhasivam@oss.qualcomm.com>", "Reply-To": "manivannan.sadhasivam@oss.qualcomm.com" }, "content": "From: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>\n\nAdd the devicetree binding for PCIe M.2 Mechanical Key E connector defined\nin the PCI Express M.2 Specification, r4.0, sec 5.1.2. This connector\nprovides interfaces like PCIe or SDIO to attach the WiFi devices to the\nhost machine, USB or UART+PCM interfaces to attach the Bluetooth (BT)\ndevices. Spec also provides an optional interface to connect the UIM card,\nbut that is not covered in this binding.\n\nThe connector provides a primary power supply of 3.3v, along with an\noptional 1.8v VIO supply for the Adapter I/O buffer circuitry operating at\n1.8v sideband signaling.\n\nThe connector also supplies optional signals in the form of GPIOs for fine\ngrained power management.\n\nReviewed-by: Rob Herring (Arm) <robh@kernel.org>\nSigned-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>\n---\n .../bindings/connector/pcie-m2-e-connector.yaml | 184 +++++++++++++++++++++\n MAINTAINERS | 1 +\n 2 files changed, 185 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml\nnew file mode 100644\nindex 000000000000..f7859aa9b634\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml\n@@ -0,0 +1,184 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/connector/pcie-m2-e-connector.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: PCIe M.2 Mechanical Key E Connector\n+\n+maintainers:\n+ - Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>\n+\n+description:\n+ A PCIe M.2 E connector node represents a physical PCIe M.2 Mechanical Key E\n+ connector. Mechanical Key E connectors are used to connect Wireless\n+ Connectivity devices including combinations of Wi-Fi, BT, NFC to the host\n+ machine over interfaces like PCIe/SDIO, USB/UART+PCM, and I2C.\n+\n+properties:\n+ compatible:\n+ const: pcie-m2-e-connector\n+\n+ vpcie3v3-supply:\n+ description: A phandle to the regulator for 3.3v supply.\n+\n+ vpcie1v8-supply:\n+ description: A phandle to the regulator for VIO 1.8v supply.\n+\n+ i2c-parent:\n+ $ref: /schemas/types.yaml#/definitions/phandle\n+ description: I2C interface\n+\n+ clocks:\n+ description: 32.768 KHz Suspend Clock (SUSCLK) input from the host system to\n+ the M.2 card. Refer, PCI Express M.2 Specification r4.0, sec 3.1.12.1 for\n+ more details.\n+ maxItems: 1\n+\n+ w-disable1-gpios:\n+ description: GPIO output to W_DISABLE1# signal. This signal is used by the\n+ host system to disable WiFi radio in the M.2 card. Refer, PCI Express M.2\n+ Specification r4.0, sec 3.1.12.3 for more details.\n+ maxItems: 1\n+\n+ w-disable2-gpios:\n+ description: GPIO output to W_DISABLE2# signal. This signal is used by the\n+ host system to disable BT radio in the M.2 card. Refer, PCI Express M.2\n+ Specification r4.0, sec 3.1.12.3 for more details.\n+ maxItems: 1\n+\n+ viocfg-gpios:\n+ description: GPIO input to IO voltage configuration (VIO_CFG) signal. The\n+ card drives this signal to indicate to the host system whether the card\n+ supports an independent IO voltage domain for sideband signals. Refer,\n+ PCI Express M.2 Specification r4.0, sec 3.1.15.1 for more details.\n+ maxItems: 1\n+\n+ uart-wake-gpios:\n+ description: GPIO input to UART_WAKE# signal. The card asserts this signal\n+ to wake the host system and initiate UART interface communication. Refer,\n+ PCI Express M.2 Specification r4.0, sec 3.1.8.1 for more details.\n+ maxItems: 1\n+\n+ sdio-wake-gpios:\n+ description: GPIO input to SDIO_WAKE# signal. The card asserts this signal\n+ to wake the host system and initiate SDIO interface communication. Refer,\n+ PCI Express M.2 Specification r4.0, sec 3.1.7 for more details.\n+ maxItems: 1\n+\n+ sdio-reset-gpios:\n+ description: GPIO output to SDIO_RESET# signal. This signal is used by the\n+ host system to reset SDIO interface of the M.2 card. Refer, PCI Express\n+ M.2 Specification r4.0, sec 3.1.7 for more details.\n+ maxItems: 1\n+\n+ vendor-porta-gpios:\n+ description: GPIO for the first vendor specific signal (VENDOR_PORTA). This\n+ signal's functionality is defined by the card manufacturer and may be\n+ used for proprietary features. Refer the card vendor's documentation for\n+ details.\n+ maxItems: 1\n+\n+ vendor-portb-gpios:\n+ description: GPIO for the second vendor specific signal (VENDOR_PORTB). This\n+ signal's functionality is defined by the card manufacturer and may be\n+ used for proprietary features. Refer the card vendor's documentation for\n+ details.\n+ maxItems: 1\n+\n+ vendor-portc-gpios:\n+ description: GPIO for the third vendor specific signal (VENDOR_PORTC). This\n+ signal's functionality is defined by the card manufacturer and may be\n+ used for proprietary features. Refer the card vendor's documentation for\n+ details.\n+ maxItems: 1\n+\n+ ports:\n+ $ref: /schemas/graph.yaml#/properties/ports\n+ description: OF graph bindings modeling the interfaces exposed on the\n+ connector. Since a single connector can have multiple interfaces, every\n+ interface has an assigned OF graph port number as described below.\n+\n+ properties:\n+ port@0:\n+ $ref: /schemas/graph.yaml#/properties/port\n+ description: PCIe interface for Wi-Fi\n+\n+ port@1:\n+ $ref: /schemas/graph.yaml#/properties/port\n+ description: SDIO interface for Wi-Fi\n+\n+ port@2:\n+ $ref: /schemas/graph.yaml#/properties/port\n+ description: USB 2.0 interface for BT\n+\n+ port@3:\n+ $ref: /schemas/graph.yaml#/properties/port\n+ description: UART interface for BT\n+\n+ port@4:\n+ $ref: /schemas/graph.yaml#/properties/port\n+ description: PCM/I2S interface\n+\n+ anyOf:\n+ - anyOf:\n+ - required:\n+ - port@0\n+ - required:\n+ - port@1\n+ - anyOf:\n+ - required:\n+ - port@2\n+ - required:\n+ - port@3\n+\n+required:\n+ - compatible\n+ - vpcie3v3-supply\n+\n+additionalProperties: false\n+\n+examples:\n+ # PCI M.2 Key E connector for Wi-Fi/BT with PCIe/UART interfaces\n+ - |\n+ #include <dt-bindings/gpio/gpio.h>\n+\n+ connector {\n+ compatible = \"pcie-m2-e-connector\";\n+ vpcie3v3-supply = <&vreg_wcn_3p3>;\n+ vpcie1v8-supply = <&vreg_l15b_1p8>;\n+ i2c-parent = <&i2c0>;\n+ w-disable1-gpios = <&tlmm 115 GPIO_ACTIVE_LOW>;\n+ w-disable2-gpios = <&tlmm 116 GPIO_ACTIVE_LOW>;\n+ viocfg-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>;\n+ uart-wake-gpios = <&tlmm 118 GPIO_ACTIVE_LOW>;\n+ sdio-wake-gpios = <&tlmm 119 GPIO_ACTIVE_LOW>;\n+ sdio-reset-gpios = <&tlmm 120 GPIO_ACTIVE_LOW>;\n+\n+ ports {\n+ #address-cells = <1>;\n+ #size-cells = <0>;\n+\n+ port@0 {\n+ reg = <0>;\n+ #address-cells = <1>;\n+ #size-cells = <0>;\n+\n+ endpoint@0 {\n+ reg = <0>;\n+ remote-endpoint = <&pcie4_port0_ep>;\n+ };\n+ };\n+\n+ port@3 {\n+ reg = <3>;\n+ #address-cells = <1>;\n+ #size-cells = <0>;\n+\n+ endpoint@0 {\n+ reg = <0>;\n+ remote-endpoint = <&uart14_ep>;\n+ };\n+ };\n+ };\n+ };\ndiff --git a/MAINTAINERS b/MAINTAINERS\nindex a38fe0ed7144..bd72ce52f00c 100644\n--- a/MAINTAINERS\n+++ b/MAINTAINERS\n@@ -21029,6 +21029,7 @@ PCIE M.2 POWER SEQUENCING\n M:\tManivannan Sadhasivam <mani@kernel.org>\n L:\tlinux-pci@vger.kernel.org\n S:\tMaintained\n+F:\tDocumentation/devicetree/bindings/connector/pcie-m2-e-connector.yaml\n F:\tDocumentation/devicetree/bindings/connector/pcie-m2-m-connector.yaml\n F:\tdrivers/power/sequencing/pwrseq-pcie-m2.c\n \n", "prefixes": [ "v7", "5/8" ] }