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GET /api/patches/2216189/?format=api
{ "id": 2216189, "url": "http://patchwork.ozlabs.org/api/patches/2216189/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/20260325232149.127814-7-ian.whitfield@canonical.com/", "project": { "id": 15, "url": "http://patchwork.ozlabs.org/api/projects/15/?format=api", "name": "Ubuntu Kernel", "link_name": "ubuntu-kernel", "list_id": "kernel-team.lists.ubuntu.com", "list_email": "kernel-team@lists.ubuntu.com", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325232149.127814-7-ian.whitfield@canonical.com>", "list_archive_url": null, "date": "2026-03-25T23:21:49", "name": "[SRU,Q:linux-gcp,6/6] RDMA/irdma: Use CQ ID for CEQE context", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6d948cc4dbf54fab338510a428f46c91d62f76d6", "submitter": { "id": 89403, "url": "http://patchwork.ozlabs.org/api/people/89403/?format=api", "name": "Ian Whitfield", "email": "ian.whitfield@canonical.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/ubuntu-kernel/patch/20260325232149.127814-7-ian.whitfield@canonical.com/mbox/", "series": [ { "id": 497521, "url": "http://patchwork.ozlabs.org/api/series/497521/?format=api", "web_url": "http://patchwork.ozlabs.org/project/ubuntu-kernel/list/?series=497521", "date": "2026-03-25T23:21:43", "name": "Add irdma fixups since 6.19", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497521/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216189/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216189/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<kernel-team-bounces@lists.ubuntu.com>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (4096-bit key;\n unprotected) header.d=canonical.com header.i=@canonical.com\n header.a=rsa-sha256 header.s=20251003 header.b=Uphw+6PW;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.ubuntu.com\n (client-ip=185.125.189.65; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "kernel-team-bounces@lists.ubuntu.com", "Sender": "\"kernel-team\" <kernel-team-bounces@lists.ubuntu.com>" }, "content": "From: Jacob Moroni <jmoroni@google.com>\n\nBugLink: https://bugs.launchpad.net/bugs/2146168\n\nThe hardware allows for an opaque CQ context field to be carried\nover into CEQEs for the CQ. Previously, a pointer to the CQ was used\nfor this context. In the normal CQ destroy flow, the CEQ ring is\nscrubbed to remove any preexisting CEQEs for the CQ that may not have\nbeen processed yet so that the CQ structure is not dereferenced in the\nCEQ ISR after the CQ has been freed.\n\nHowever, in some cases, it is possible for a CEQE to be in flight in\nHW even after the CQ destroy command completion is received, so it\ncould be missed during the scrub.\n\nTo protect against this, we can take advantage of the CQ table that\nalready exists and use the CQ ID for this context rather than a CQ\npointer.\n\nSigned-off-by: Jacob Moroni <jmoroni@google.com>\nLink: https://patch.msgid.link/20260120212546.1893076-2-jmoroni@google.com\nSigned-off-by: Leon Romanovsky <leon@kernel.org>\n(cherry picked from commit 2529aead51673814ebf464723626ac608b8635a5)\nSigned-off-by: Ian Whitfield <ian.whitfield@canonical.com>\n---\n drivers/infiniband/hw/irdma/ctrl.c | 62 ++++++++------------\n drivers/infiniband/hw/irdma/hw.c | 88 +++++++++++++++++++++++++----\n drivers/infiniband/hw/irdma/puda.c | 14 +++++\n drivers/infiniband/hw/irdma/type.h | 6 +-\n drivers/infiniband/hw/irdma/utils.c | 3 +-\n drivers/infiniband/hw/irdma/verbs.c | 5 +-\n 6 files changed, 127 insertions(+), 51 deletions(-)", "diff": "diff --git a/drivers/infiniband/hw/irdma/ctrl.c b/drivers/infiniband/hw/irdma/ctrl.c\nindex c17b1c14dfe2..a996a194516f 100644\n--- a/drivers/infiniband/hw/irdma/ctrl.c\n+++ b/drivers/infiniband/hw/irdma/ctrl.c\n@@ -2886,15 +2886,6 @@ static int irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp,\n \treturn 0;\n }\n \n-/**\n- * irdma_sc_cq_ack - acknowledge completion q\n- * @cq: cq struct\n- */\n-static inline void irdma_sc_cq_ack(struct irdma_sc_cq *cq)\n-{\n-\twritel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);\n-}\n-\n /**\n * irdma_sc_cq_init - initialize completion q\n * @cq: cq struct\n@@ -2956,7 +2947,7 @@ static int irdma_sc_cq_create(struct irdma_sc_cq *cq, u64 scratch,\n \t\treturn -ENOMEM;\n \n \tset_64bit_val(wqe, 0, cq->cq_uk.cq_size);\n-\tset_64bit_val(wqe, 8, (uintptr_t)cq >> 1);\n+\tset_64bit_val(wqe, 8, cq->cq_uk.cq_id);\n \tset_64bit_val(wqe, 16,\n \t\t FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold));\n \tset_64bit_val(wqe, 32, (cq->virtual_map ? 0 : cq->cq_pa));\n@@ -3013,7 +3004,7 @@ int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq)\n \t\treturn -ENOMEM;\n \n \tset_64bit_val(wqe, 0, cq->cq_uk.cq_size);\n-\tset_64bit_val(wqe, 8, (uintptr_t)cq >> 1);\n+\tset_64bit_val(wqe, 8, cq->cq_uk.cq_id);\n \tset_64bit_val(wqe, 40, cq->shadow_area_pa);\n \tset_64bit_val(wqe, 48,\n \t\t (cq->virtual_map ? cq->first_pm_pbl_idx : 0));\n@@ -3082,7 +3073,7 @@ static int irdma_sc_cq_modify(struct irdma_sc_cq *cq,\n \t\treturn -ENOMEM;\n \n \tset_64bit_val(wqe, 0, info->cq_size);\n-\tset_64bit_val(wqe, 8, (uintptr_t)cq >> 1);\n+\tset_64bit_val(wqe, 8, cq->cq_uk.cq_id);\n \tset_64bit_val(wqe, 16,\n \t\t FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold));\n \tset_64bit_val(wqe, 32, info->cq_pa);\n@@ -4460,47 +4451,38 @@ int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq)\n * irdma_sc_process_ceq - process ceq\n * @dev: sc device struct\n * @ceq: ceq sc structure\n+ * @cq_idx: Pointer to a CQ ID that will be populated.\n *\n * It is expected caller serializes this function with cleanup_ceqes()\n * because these functions manipulate the same ceq\n+ *\n+ * Return: True if cq_idx has been populated with a CQ ID.\n */\n-void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq)\n+bool irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq,\n+\t\t\t u32 *cq_idx)\n {\n \tu64 temp;\n \t__le64 *ceqe;\n-\tstruct irdma_sc_cq *cq = NULL;\n-\tstruct irdma_sc_cq *temp_cq;\n \tu8 polarity;\n-\tu32 cq_idx;\n \n \tdo {\n-\t\tcq_idx = 0;\n \t\tceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq);\n \t\tget_64bit_val(ceqe, 0, &temp);\n \t\tpolarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp);\n \t\tif (polarity != ceq->polarity)\n-\t\t\treturn NULL;\n+\t\t\treturn false;\n \n-\t\ttemp_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1);\n-\t\tif (!temp_cq) {\n-\t\t\tcq_idx = IRDMA_INVALID_CQ_IDX;\n-\t\t\tIRDMA_RING_MOVE_TAIL(ceq->ceq_ring);\n-\n-\t\t\tif (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring))\n-\t\t\t\tceq->polarity ^= 1;\n-\t\t\tcontinue;\n-\t\t}\n-\n-\t\tcq = temp_cq;\n+\t\t/* Truncate. Discard valid bit which is MSb of temp. */\n+\t\t*cq_idx = temp;\n+\t\tif (*cq_idx >= dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt)\n+\t\t\t*cq_idx = IRDMA_INVALID_CQ_IDX;\n \n \t\tIRDMA_RING_MOVE_TAIL(ceq->ceq_ring);\n \t\tif (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring))\n \t\t\tceq->polarity ^= 1;\n-\t} while (cq_idx == IRDMA_INVALID_CQ_IDX);\n+\t} while (*cq_idx == IRDMA_INVALID_CQ_IDX);\n \n-\tif (cq)\n-\t\tirdma_sc_cq_ack(cq);\n-\treturn cq;\n+\treturn true;\n }\n \n /**\n@@ -4514,10 +4496,10 @@ void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq)\n */\n void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq)\n {\n-\tstruct irdma_sc_cq *next_cq;\n \tu8 ceq_polarity = ceq->polarity;\n \t__le64 *ceqe;\n \tu8 polarity;\n+\tu32 cq_idx;\n \tu64 temp;\n \tint next;\n \tu32 i;\n@@ -4532,9 +4514,10 @@ void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq)\n \t\tif (polarity != ceq_polarity)\n \t\t\treturn;\n \n-\t\tnext_cq = (struct irdma_sc_cq *)(unsigned long)(temp << 1);\n-\t\tif (cq == next_cq)\n-\t\t\tset_64bit_val(ceqe, 0, temp & IRDMA_CEQE_VALID);\n+\t\tcq_idx = temp;\n+\t\tif (cq_idx == cq->cq_uk.cq_id)\n+\t\t\tset_64bit_val(ceqe, 0, (temp & IRDMA_CEQE_VALID) |\n+\t\t\t\t IRDMA_INVALID_CQ_IDX);\n \n \t\tnext = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i);\n \t\tif (!next)\n@@ -4974,7 +4957,7 @@ int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq)\n \t\treturn -ENOMEM;\n \n \tset_64bit_val(wqe, 0, ccq->cq_uk.cq_size);\n-\tset_64bit_val(wqe, 8, (uintptr_t)ccq >> 1);\n+\tset_64bit_val(wqe, 8, ccq->cq_uk.cq_id);\n \tset_64bit_val(wqe, 40, ccq->shadow_area_pa);\n \n \thdr = ccq->cq_uk.cq_id |\n@@ -6461,6 +6444,9 @@ int irdma_sc_dev_init(enum irdma_vers ver, struct irdma_sc_dev *dev,\n \tint ret_code = 0;\n \tu8 db_size;\n \n+\tspin_lock_init(&dev->puda_cq_lock);\n+\tdev->ilq_cq = NULL;\n+\tdev->ieq_cq = NULL;\n \tINIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */\n \tmutex_init(&dev->ws_mutex);\n \tdev->hmc_fn_id = info->hmc_fn_id;\ndiff --git a/drivers/infiniband/hw/irdma/hw.c b/drivers/infiniband/hw/irdma/hw.c\nindex da63e00b4264..616588552b9c 100644\n--- a/drivers/infiniband/hw/irdma/hw.c\n+++ b/drivers/infiniband/hw/irdma/hw.c\n@@ -98,6 +98,74 @@ static void irdma_puda_ce_handler(struct irdma_pci_f *rf,\n \tirdma_sc_ccq_arm(cq);\n }\n \n+/**\n+ * irdma_process_normal_ceqe - Handle a CEQE for a normal CQ.\n+ * @rf: RDMA PCI function.\n+ * @dev: iWARP device.\n+ * @cq_idx: CQ ID. Must be in table bounds.\n+ *\n+ * Context: Atomic (CEQ lock must be held)\n+ */\n+static void irdma_process_normal_ceqe(struct irdma_pci_f *rf,\n+\t\t\t\t struct irdma_sc_dev *dev, u32 cq_idx)\n+{\n+\t/* cq_idx bounds validated in irdma_sc_process_ceq. */\n+\tstruct irdma_cq *icq = READ_ONCE(rf->cq_table[cq_idx]);\n+\tstruct irdma_sc_cq *cq;\n+\n+\tif (unlikely(!icq)) {\n+\t\t/* Should not happen since CEQ is scrubbed upon CQ delete. */\n+\t\tibdev_warn_ratelimited(to_ibdev(dev), \"Stale CEQE for CQ %u\",\n+\t\t\t\t cq_idx);\n+\t\treturn;\n+\t}\n+\n+\tcq = &icq->sc_cq;\n+\n+\tif (unlikely(cq->cq_type != IRDMA_CQ_TYPE_IWARP)) {\n+\t\tibdev_warn_ratelimited(to_ibdev(dev), \"Unexpected CQ type %u\",\n+\t\t\t\t cq->cq_type);\n+\t\treturn;\n+\t}\n+\n+\twritel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);\n+\tirdma_iwarp_ce_handler(cq);\n+}\n+\n+/**\n+ * irdma_process_reserved_ceqe - Handle a CEQE for a reserved CQ.\n+ * @rf: RDMA PCI function.\n+ * @dev: iWARP device.\n+ * @cq_idx: CQ ID.\n+ *\n+ * Context: Atomic\n+ */\n+static void irdma_process_reserved_ceqe(struct irdma_pci_f *rf,\n+\t\t\t\t\tstruct irdma_sc_dev *dev, u32 cq_idx)\n+{\n+\tstruct irdma_sc_cq *cq;\n+\n+\tif (cq_idx == IRDMA_RSVD_CQ_ID_CQP) {\n+\t\tcq = &rf->ccq.sc_cq;\n+\t\t/* CQP CQ lifetime > CEQ. */\n+\t\twritel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);\n+\t\tqueue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work);\n+\t} else if (cq_idx == IRDMA_RSVD_CQ_ID_ILQ ||\n+\t\t cq_idx == IRDMA_RSVD_CQ_ID_IEQ) {\n+\t\tscoped_guard(spinlock_irqsave, &dev->puda_cq_lock) {\n+\t\t\tcq = (cq_idx == IRDMA_RSVD_CQ_ID_ILQ) ?\n+\t\t\t\tdev->ilq_cq : dev->ieq_cq;\n+\t\t\tif (!cq) {\n+\t\t\t\tibdev_warn_ratelimited(to_ibdev(dev),\n+\t\t\t\t\t\t \"Stale ILQ/IEQ CEQE\");\n+\t\t\t\treturn;\n+\t\t\t}\n+\t\t\twritel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db);\n+\t\t\tirdma_puda_ce_handler(rf, cq);\n+\t\t}\n+\t}\n+}\n+\n /**\n * irdma_process_ceq - handle ceq for completions\n * @rf: RDMA PCI function\n@@ -107,28 +175,28 @@ static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq)\n {\n \tstruct irdma_sc_dev *dev = &rf->sc_dev;\n \tstruct irdma_sc_ceq *sc_ceq;\n-\tstruct irdma_sc_cq *cq;\n \tunsigned long flags;\n+\tu32 cq_idx;\n \n \tsc_ceq = &ceq->sc_ceq;\n \tdo {\n \t\tspin_lock_irqsave(&ceq->ce_lock, flags);\n-\t\tcq = irdma_sc_process_ceq(dev, sc_ceq);\n-\t\tif (!cq) {\n+\n+\t\tif (!irdma_sc_process_ceq(dev, sc_ceq, &cq_idx)) {\n \t\t\tspin_unlock_irqrestore(&ceq->ce_lock, flags);\n \t\t\tbreak;\n \t\t}\n \n-\t\tif (cq->cq_type == IRDMA_CQ_TYPE_IWARP)\n-\t\t\tirdma_iwarp_ce_handler(cq);\n+\t\t/* Normal CQs must be handled while holding CEQ lock. */\n+\t\tif (likely(cq_idx > IRDMA_RSVD_CQ_ID_IEQ)) {\n+\t\t\tirdma_process_normal_ceqe(rf, dev, cq_idx);\n+\t\t\tspin_unlock_irqrestore(&ceq->ce_lock, flags);\n+\t\t\tcontinue;\n+\t\t}\n \n \t\tspin_unlock_irqrestore(&ceq->ce_lock, flags);\n \n-\t\tif (cq->cq_type == IRDMA_CQ_TYPE_CQP)\n-\t\t\tqueue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work);\n-\t\telse if (cq->cq_type == IRDMA_CQ_TYPE_ILQ ||\n-\t\t\t cq->cq_type == IRDMA_CQ_TYPE_IEQ)\n-\t\t\tirdma_puda_ce_handler(rf, cq);\n+\t\tirdma_process_reserved_ceqe(rf, dev, cq_idx);\n \t} while (1);\n }\n \ndiff --git a/drivers/infiniband/hw/irdma/puda.c b/drivers/infiniband/hw/irdma/puda.c\nindex cee47ddbd1b5..4f1a8c97faf1 100644\n--- a/drivers/infiniband/hw/irdma/puda.c\n+++ b/drivers/infiniband/hw/irdma/puda.c\n@@ -809,6 +809,13 @@ static int irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc)\n \t\tdma_free_coherent(dev->hw->device, rsrc->cqmem.size,\n \t\t\t\t rsrc->cqmem.va, rsrc->cqmem.pa);\n \t\trsrc->cqmem.va = NULL;\n+\t} else {\n+\t\tscoped_guard(spinlock_irqsave, &dev->puda_cq_lock) {\n+\t\t\tif (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ)\n+\t\t\t\tdev->ilq_cq = cq;\n+\t\t\telse\n+\t\t\t\tdev->ieq_cq = cq;\n+\t\t}\n \t}\n \n \treturn ret;\n@@ -856,6 +863,13 @@ static void irdma_puda_free_cq(struct irdma_puda_rsrc *rsrc)\n \tstruct irdma_ccq_cqe_info compl_info;\n \tstruct irdma_sc_dev *dev = rsrc->dev;\n \n+\tscoped_guard(spinlock_irqsave, &dev->puda_cq_lock) {\n+\t\tif (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ)\n+\t\t\tdev->ilq_cq = NULL;\n+\t\telse\n+\t\t\tdev->ieq_cq = NULL;\n+\t}\n+\n \tif (rsrc->dev->ceq_valid) {\n \t\tirdma_cqp_cq_destroy_cmd(dev, &rsrc->cq);\n \t\treturn;\ndiff --git a/drivers/infiniband/hw/irdma/type.h b/drivers/infiniband/hw/irdma/type.h\nindex 3de9240b727f..da8c54d1f035 100644\n--- a/drivers/infiniband/hw/irdma/type.h\n+++ b/drivers/infiniband/hw/irdma/type.h\n@@ -707,6 +707,9 @@ struct irdma_sc_dev {\n \tstruct irdma_sc_aeq *aeq;\n \tstruct irdma_sc_ceq *ceq[IRDMA_CEQ_MAX_COUNT];\n \tstruct irdma_sc_cq *ccq;\n+\tspinlock_t puda_cq_lock;\n+\tstruct irdma_sc_cq *ilq_cq;\n+\tstruct irdma_sc_cq *ieq_cq;\n \tconst struct irdma_irq_ops *irq_ops;\n \tstruct irdma_qos qos[IRDMA_MAX_USER_PRIORITY];\n \tstruct irdma_hmc_fpm_misc hmc_fpm_misc;\n@@ -1344,7 +1347,8 @@ int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq);\n int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq,\n \t\t struct irdma_ceq_init_info *info);\n void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq);\n-void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq);\n+bool irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq,\n+\t\t\t u32 *cq_idx);\n \n int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq,\n \t\t struct irdma_aeq_init_info *info);\ndiff --git a/drivers/infiniband/hw/irdma/utils.c b/drivers/infiniband/hw/irdma/utils.c\nindex a1d9ebe4f731..90aeb687b1c5 100644\n--- a/drivers/infiniband/hw/irdma/utils.c\n+++ b/drivers/infiniband/hw/irdma/utils.c\n@@ -829,7 +829,8 @@ void irdma_cq_rem_ref(struct ib_cq *ibcq)\n \t\treturn;\n \t}\n \n-\tiwdev->rf->cq_table[iwcq->cq_num] = NULL;\n+\t/* May be asynchronously sampled by CEQ ISR without holding tbl lock. */\n+\tWRITE_ONCE(iwdev->rf->cq_table[iwcq->cq_num], NULL);\n \tspin_unlock_irqrestore(&iwdev->rf->cqtable_lock, flags);\n \tcomplete(&iwcq->free_cq);\n }\ndiff --git a/drivers/infiniband/hw/irdma/verbs.c b/drivers/infiniband/hw/irdma/verbs.c\nindex 5e098215d1c0..ee08d97e56f1 100644\n--- a/drivers/infiniband/hw/irdma/verbs.c\n+++ b/drivers/infiniband/hw/irdma/verbs.c\n@@ -2658,9 +2658,12 @@ static int irdma_create_cq(struct ib_cq *ibcq,\n \t\t\tgoto cq_destroy;\n \t\t}\n \t}\n-\trf->cq_table[cq_num] = iwcq;\n+\n \tinit_completion(&iwcq->free_cq);\n \n+\t/* Populate table entry after CQ is fully created. */\n+\tsmp_store_release(&rf->cq_table[cq_num], iwcq);\n+\n \treturn 0;\n cq_destroy:\n \tirdma_cq_wq_destroy(rf, cq);\n", "prefixes": [ "SRU", "Q:linux-gcp", "6/6" ] }