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GET /api/patches/2216171/?format=api
{ "id": 2216171, "url": "http://patchwork.ozlabs.org/api/patches/2216171/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260325223232.1553212-16-raymondmaoca@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325223232.1553212-16-raymondmaoca@gmail.com>", "list_archive_url": null, "date": "2026-03-25T22:32:31", "name": "[v3,15/16] power: regulator: add support for Spacemit P1 SoC", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b01c626e71a7d330c16d18f65d498f881e171c6f", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260325223232.1553212-16-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 497518, "url": "http://patchwork.ozlabs.org/api/series/497518/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497518", "date": "2026-03-25T22:32:17", "name": "Add board support for Spacemit K1 SoC in SPL", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497518/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216171/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216171/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=KkLnfIzr;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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It contains 6 BUCKs\nand 11 LDOs.\n\nSigned-off-by: Raymond Mao <raymond.mao@riscstar.com>\nAcked-by: Peng Fan <peng.fan@nxp.com>\n---\nChanges in v3:\n- Drop SPL_DM_REGULATOR_SPACEMIT_P1 Kconfig\n\n drivers/power/regulator/Kconfig | 8 +\n drivers/power/regulator/Makefile | 1 +\n .../power/regulator/spacemit_p1_regulator.c | 460 ++++++++++++++++++\n 3 files changed, 469 insertions(+)\n create mode 100644 drivers/power/regulator/spacemit_p1_regulator.c", "diff": "diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig\nindex 4f39e46cebd..ddfbfd1483d 100644\n--- a/drivers/power/regulator/Kconfig\n+++ b/drivers/power/regulator/Kconfig\n@@ -547,3 +547,11 @@ config DM_REGULATOR_MT6359\n \t MediaTek MT6359 PMIC.\n \t This driver supports the control of different power rails of device\n \t through regulator interface.\n+\n+config DM_REGULATOR_SPACEMIT_P1\n+\tbool \"Enable driver for Spacemit P1 PMIC regulators\"\n+\tdepends on DM_REGULATOR && PMIC_SPACEMIT_P1\n+\thelp\n+\t Enable implementation of driver-model regulator uclass features\n+\t for regulator P1. The driver supports BUCKs, LDOs and SWITCHes.\n+\ndiff --git a/drivers/power/regulator/Makefile b/drivers/power/regulator/Makefile\nindex 9e303d4f7f8..8103382951b 100644\n--- a/drivers/power/regulator/Makefile\n+++ b/drivers/power/regulator/Makefile\n@@ -29,6 +29,7 @@ obj-$(CONFIG_$(PHASE_)REGULATOR_RK8XX) += rk8xx.o\n obj-$(CONFIG_DM_REGULATOR_S2MPS11) += s2mps11_regulator.o\n obj-$(CONFIG_REGULATOR_S5M8767) += s5m8767.o\n obj-$(CONFIG_DM_REGULATOR_SANDBOX) += sandbox.o\n+obj-$(CONFIG_DM_REGULATOR_SPACEMIT_P1) += spacemit_p1_regulator.o\n obj-$(CONFIG_REGULATOR_TPS65090) += tps65090_regulator.o\n obj-$(CONFIG_$(PHASE_)DM_REGULATOR_PALMAS) += palmas_regulator.o\n obj-$(CONFIG_$(PHASE_)DM_REGULATOR_PBIAS) += pbias_regulator.o\ndiff --git a/drivers/power/regulator/spacemit_p1_regulator.c b/drivers/power/regulator/spacemit_p1_regulator.c\nnew file mode 100644\nindex 00000000000..ab3ca489f0b\n--- /dev/null\n+++ b/drivers/power/regulator/spacemit_p1_regulator.c\n@@ -0,0 +1,460 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright (C) 2025-2026 RISCstar Ltd.\n+ */\n+\n+#include <dm.h>\n+#include <dm/lists.h>\n+#include <errno.h>\n+#include <log.h>\n+#include <power/pmic.h>\n+#include <power/regulator.h>\n+#include <power/spacemit_p1.h>\n+\n+struct p1_reg_info {\n+\tuint min_uv;\n+\tuint step_uv;\n+\tu8 vsel_reg;\n+\tu8 vsel_sleep_reg;\n+\tu8 config_reg;\n+\tu8 vsel_mask;\n+\tu8 min_sel;\n+\tu8 max_sel;\n+};\n+\n+static const struct p1_reg_info p1_bucks[] = {\n+\t/* BUCK 1 */\n+\t{ 500000, 5000, P1_BUCK_VSEL(1), P1_BUCK_SVSEL(1), P1_BUCK_CTRL(1),\n+\t BUCK_VSEL_MASK, 0x00, 0xaa },\n+\t{ 1375000, 25000, P1_BUCK_VSEL(1), P1_BUCK_SVSEL(1), P1_BUCK_CTRL(1),\n+\t BUCK_VSEL_MASK, 0xab, 0xfe },\n+\t/* BUCK 2 */\n+\t{ 500000, 5000, P1_BUCK_VSEL(2), P1_BUCK_SVSEL(2), P1_BUCK_CTRL(2),\n+\t BUCK_VSEL_MASK, 0x00, 0xaa },\n+\t{ 1375000, 25000, P1_BUCK_VSEL(2), P1_BUCK_SVSEL(2), P1_BUCK_CTRL(2),\n+\t BUCK_VSEL_MASK, 0xab, 0xfe },\n+\t/* BUCK 3 */\n+\t{ 500000, 5000, P1_BUCK_VSEL(3), P1_BUCK_SVSEL(3), P1_BUCK_CTRL(3),\n+\t BUCK_VSEL_MASK, 0x00, 0xaa },\n+\t{ 1375000, 25000, P1_BUCK_VSEL(3), P1_BUCK_SVSEL(3), P1_BUCK_CTRL(3),\n+\t BUCK_VSEL_MASK, 0xab, 0xfe },\n+\t/* BUCK 4 */\n+\t{ 500000, 5000, P1_BUCK_VSEL(4), P1_BUCK_SVSEL(4), P1_BUCK_CTRL(4),\n+\t BUCK_VSEL_MASK, 0x00, 0xaa },\n+\t{ 1375000, 25000, P1_BUCK_VSEL(4), P1_BUCK_SVSEL(4), P1_BUCK_CTRL(4),\n+\t BUCK_VSEL_MASK, 0xab, 0xfe },\n+\t/* BUCK 5 */\n+\t{ 500000, 5000, P1_BUCK_VSEL(5), P1_BUCK_SVSEL(5), P1_BUCK_CTRL(5),\n+\t BUCK_VSEL_MASK, 0x00, 0xaa },\n+\t{ 1375000, 25000, P1_BUCK_VSEL(5), P1_BUCK_SVSEL(5), P1_BUCK_CTRL(5),\n+\t BUCK_VSEL_MASK, 0xab, 0xfe },\n+\t/* BUCK 6 */\n+\t{ 500000, 5000, P1_BUCK_VSEL(6), P1_BUCK_SVSEL(6), P1_BUCK_CTRL(6),\n+\t BUCK_VSEL_MASK, 0x00, 0xaa },\n+\t{ 1375000, 25000, P1_BUCK_VSEL(6), P1_BUCK_SVSEL(6), P1_BUCK_CTRL(6),\n+\t BUCK_VSEL_MASK, 0xab, 0xfe },\n+};\n+\n+static const struct p1_reg_info p1_aldos[] = {\n+\t/* ALDO 1 */\n+\t{ 500000, 25000, P1_ALDO_VOLT(1), P1_ALDO_SVOLT(1), P1_ALDO_CTRL(1),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* ALDO 2 */\n+\t{ 500000, 25000, P1_ALDO_VOLT(2), P1_ALDO_SVOLT(2), P1_ALDO_CTRL(2),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* ALDO 3 */\n+\t{ 500000, 25000, P1_ALDO_VOLT(3), P1_ALDO_SVOLT(3), P1_ALDO_CTRL(3),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* ALDO 4 */\n+\t{ 500000, 25000, P1_ALDO_VOLT(4), P1_ALDO_SVOLT(4), P1_ALDO_CTRL(4),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+};\n+\n+static const struct p1_reg_info p1_dldos[] = {\n+\t/* DLDO 1 */\n+\t{ 500000, 25000, P1_DLDO_VOLT(1), P1_DLDO_SVOLT(1), P1_DLDO_CTRL(1),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* DLDO 2 */\n+\t{ 500000, 25000, P1_DLDO_VOLT(2), P1_DLDO_SVOLT(2), P1_DLDO_CTRL(2),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* DLDO 3 */\n+\t{ 500000, 25000, P1_DLDO_VOLT(3), P1_DLDO_SVOLT(3), P1_DLDO_CTRL(3),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* DLDO 4 */\n+\t{ 500000, 25000, P1_DLDO_VOLT(4), P1_DLDO_SVOLT(4), P1_DLDO_CTRL(4),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* DLDO 5 */\n+\t{ 500000, 25000, P1_DLDO_VOLT(5), P1_DLDO_SVOLT(5), P1_DLDO_CTRL(5),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* DLDO 6 */\n+\t{ 500000, 25000, P1_DLDO_VOLT(6), P1_DLDO_SVOLT(6), P1_DLDO_CTRL(6),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+\t/* DLDO 7 */\n+\t{ 500000, 25000, P1_DLDO_VOLT(7), P1_DLDO_SVOLT(7), P1_DLDO_CTRL(7),\n+\t ALDO_VSEL_MASK, 0x0b, 0x7f },\n+};\n+\n+static const struct p1_reg_info *get_buck_reg(struct udevice *pmic,\n+\t\t\t\t\t int idx, int uvolt)\n+{\n+\tif (idx < 0)\n+\t\treturn NULL;\n+\tif (uvolt < 1375000)\n+\t\treturn &p1_bucks[(idx - 1) * 2 + 0];\n+\treturn &p1_bucks[(idx - 1) * 2 + 1];\n+}\n+\n+static const struct p1_reg_info *get_aldo_reg(struct udevice *pmic,\n+\t\t\t\t\t int idx, int uvolt)\n+{\n+\treturn &p1_aldos[idx];\n+}\n+\n+static const struct p1_reg_info *get_dldo_reg(struct udevice *pmic,\n+\t\t\t\t\t int idx, int uvolt)\n+{\n+\treturn &p1_dldos[idx];\n+}\n+\n+static int buck_get_value(struct udevice *dev)\n+{\n+\tconst struct dm_pmic_ops *ops = device_get_ops(dev->parent);\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tif (!ops || !ops->read)\n+\t\treturn -ENOSYS;\n+\n+\tinfo = get_buck_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\tret = pmic_reg_read(dev->parent, info->vsel_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tval = ret & info->vsel_mask;\n+\twhile (val > info->max_sel)\n+\t\tinfo++;\n+\n+\treturn info->min_uv + (val - info->min_sel) * info->step_uv;\n+}\n+\n+static int buck_set_value(struct udevice *dev, int uvolt)\n+{\n+\tconst struct dm_pmic_ops *ops = device_get_ops(dev->parent);\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tif (!ops || !ops->write)\n+\t\treturn -ENOSYS;\n+\n+\tinfo = get_buck_reg(dev->parent, dev->driver_data, uvolt);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\tval = (uvolt - info->min_uv);\n+\tval = val / info->step_uv;\n+\tval += info->min_sel;\n+\tret = pmic_reg_write(dev->parent, info->vsel_reg, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn 0;\n+}\n+\n+static int buck_get_enable(struct udevice *dev)\n+{\n+\tconst struct p1_reg_info *info;\n+\tint ret;\n+\n+\tinfo = get_buck_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->config_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn ret & BUCK_EN_MASK;\n+}\n+\n+static int buck_set_enable(struct udevice *dev, bool enable)\n+{\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tinfo = get_buck_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->config_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tval = (unsigned int)ret;\n+\tval &= BUCK_EN_MASK;\n+\n+\tif (enable == val)\n+\t\treturn 0;\n+\n+\tval = enable;\n+\tret = pmic_clrsetbits(dev->parent, info->config_reg, BUCK_EN_MASK, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_regulator_ops p1_buck_ops = {\n+\t.get_value = buck_get_value,\n+\t.set_value = buck_set_value,\n+\t.get_enable = buck_get_enable,\n+\t.set_enable = buck_set_enable,\n+};\n+\n+static int p1_buck_probe(struct udevice *dev)\n+{\n+\tstruct dm_regulator_uclass_plat *uc_pdata;\n+\n+\tuc_pdata = dev_get_uclass_plat(dev);\n+\n+\tuc_pdata->type = REGULATOR_TYPE_BUCK;\n+\tuc_pdata->mode_count = 0;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(p1_buck) = {\n+\t.name\t\t= P1_BUCK_DRIVER,\n+\t.id\t\t= UCLASS_REGULATOR,\n+\t.ops\t\t= &p1_buck_ops,\n+\t.probe\t\t= p1_buck_probe,\n+};\n+\n+static int aldo_get_value(struct udevice *dev)\n+{\n+\tconst struct dm_pmic_ops *ops = device_get_ops(dev->parent);\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tif (!ops || !ops->read)\n+\t\treturn -ENOSYS;\n+\n+\tinfo = get_aldo_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->vsel_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = ret & info->vsel_mask;\n+\twhile (val > info->max_sel)\n+\t\tinfo++;\n+\n+\treturn info->min_uv + (val - info->min_sel) * info->step_uv;\n+}\n+\n+static int aldo_set_value(struct udevice *dev, int uvolt)\n+{\n+\tconst struct dm_pmic_ops *ops = device_get_ops(dev->parent);\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tif (!ops || !ops->write)\n+\t\treturn -ENOSYS;\n+\n+\tinfo = get_aldo_reg(dev->parent, dev->driver_data, uvolt);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\tval = (uvolt - info->min_uv);\n+\tval = val / info->step_uv;\n+\tval += info->min_sel;\n+\tret = pmic_reg_write(dev->parent, info->vsel_reg, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn 0;\n+}\n+\n+static int aldo_get_enable(struct udevice *dev)\n+{\n+\tconst struct p1_reg_info *info;\n+\tint ret;\n+\n+\tinfo = get_aldo_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->config_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn ret & ALDO_EN_MASK;\n+}\n+\n+static int aldo_set_enable(struct udevice *dev, bool enable)\n+{\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tinfo = get_aldo_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->config_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tval = (unsigned int)ret;\n+\tval &= ALDO_EN_MASK;\n+\n+\tif (enable == val)\n+\t\treturn 0;\n+\n+\tval = enable;\n+\tret = pmic_clrsetbits(dev->parent, info->config_reg, ALDO_EN_MASK, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_regulator_ops p1_aldo_ops = {\n+\t.get_value\t= aldo_get_value,\n+\t.set_value\t= aldo_set_value,\n+\t.get_enable\t= aldo_get_enable,\n+\t.set_enable\t= aldo_set_enable,\n+};\n+\n+static int p1_aldo_probe(struct udevice *dev)\n+{\n+\tstruct dm_regulator_uclass_plat *uc_pdata;\n+\n+\tuc_pdata = dev_get_uclass_plat(dev);\n+\n+\tuc_pdata->type = REGULATOR_TYPE_LDO;\n+\tuc_pdata->mode_count = 0;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(p1_aldo) = {\n+\t.name\t\t= P1_ALDO_DRIVER,\n+\t.id\t\t= UCLASS_REGULATOR,\n+\t.ops\t\t= &p1_aldo_ops,\n+\t.probe\t\t= p1_aldo_probe,\n+};\n+\n+static int dldo_get_value(struct udevice *dev)\n+{\n+\tconst struct dm_pmic_ops *ops = device_get_ops(dev->parent);\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tif (!ops || !ops->read)\n+\t\treturn -ENOSYS;\n+\n+\tinfo = get_dldo_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->vsel_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\tval = ret & info->vsel_mask;\n+\twhile (val > info->max_sel)\n+\t\tinfo++;\n+\n+\treturn info->min_uv + (val - info->min_sel) * info->step_uv;\n+}\n+\n+static int dldo_set_value(struct udevice *dev, int uvolt)\n+{\n+\tconst struct dm_pmic_ops *ops = device_get_ops(dev->parent);\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tif (!ops || !ops->write)\n+\t\treturn -ENOSYS;\n+\n+\tinfo = get_dldo_reg(dev->parent, dev->driver_data, uvolt);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\tval = (uvolt - info->min_uv);\n+\tval = val / info->step_uv;\n+\tval += info->min_sel;\n+\tret = pmic_reg_write(dev->parent, info->vsel_reg, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn 0;\n+}\n+\n+static int dldo_get_enable(struct udevice *dev)\n+{\n+\tconst struct p1_reg_info *info;\n+\tint ret;\n+\n+\tinfo = get_dldo_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->config_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\treturn ret & DLDO_EN_MASK;\n+}\n+\n+static int dldo_set_enable(struct udevice *dev, bool enable)\n+{\n+\tconst struct p1_reg_info *info;\n+\tuint val;\n+\tint ret;\n+\n+\tinfo = get_dldo_reg(dev->parent, dev->driver_data, 0);\n+\tif (!info)\n+\t\treturn -ENOENT;\n+\n+\tret = pmic_reg_read(dev->parent, info->config_reg);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\tval = (unsigned int)ret;\n+\tval &= DLDO_EN_MASK;\n+\n+\tif (enable == val)\n+\t\treturn 0;\n+\n+\tval = enable;\n+\tret = pmic_clrsetbits(dev->parent, info->config_reg, DLDO_EN_MASK, val);\n+\tif (ret < 0)\n+\t\treturn ret;\n+\n+\treturn 0;\n+}\n+\n+static const struct dm_regulator_ops p1_dldo_ops = {\n+\t.get_value\t= dldo_get_value,\n+\t.set_value\t= dldo_set_value,\n+\t.get_enable\t= dldo_get_enable,\n+\t.set_enable\t= dldo_set_enable,\n+};\n+\n+static int p1_dldo_probe(struct udevice *dev)\n+{\n+\tstruct dm_regulator_uclass_plat *uc_pdata;\n+\n+\tuc_pdata = dev_get_uclass_plat(dev);\n+\n+\tuc_pdata->type = REGULATOR_TYPE_LDO;\n+\tuc_pdata->mode_count = 0;\n+\n+\treturn 0;\n+}\n+\n+U_BOOT_DRIVER(p1_dldo) = {\n+\t.name\t\t= P1_DLDO_DRIVER,\n+\t.id\t\t= UCLASS_REGULATOR,\n+\t.ops\t\t= &p1_dldo_ops,\n+\t.probe\t\t= p1_dldo_probe,\n+};\n", "prefixes": [ "v3", "15/16" ] }