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GET /api/patches/2216161/?format=api
{ "id": 2216161, "url": "http://patchwork.ozlabs.org/api/patches/2216161/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20260325223232.1553212-6-raymondmaoca@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325223232.1553212-6-raymondmaoca@gmail.com>", "list_archive_url": null, "date": "2026-03-25T22:32:21", "name": "[v3,05/16] dt-bindings: clock: import k1-syscon from upstream", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "ded5d8952e5d359086ce4360963c1d635098033b", "submitter": { "id": 91989, "url": "http://patchwork.ozlabs.org/api/people/91989/?format=api", "name": "Raymond Mao", "email": "raymondmaoca@gmail.com" }, "delegate": { "id": 20174, "url": "http://patchwork.ozlabs.org/api/users/20174/?format=api", "username": "Andes", "first_name": "Andes", "last_name": "", "email": "uboot@andestech.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20260325223232.1553212-6-raymondmaoca@gmail.com/mbox/", "series": [ { "id": 497518, "url": "http://patchwork.ozlabs.org/api/series/497518/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=497518", "date": "2026-03-25T22:32:17", "name": "Add board support for Spacemit K1 SoC in SPL", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/497518/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216161/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216161/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=rs1uyNIw;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=lists.denx.de\n (client-ip=85.214.62.61; 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And remove\nduplicated reset IDs in it.\n\nSigned-off-by: Raymond Mao <raymond.mao@riscstar.com>\n---\nChanges in v3:\n- None.\n\n .../dt-bindings/clock/spacemit,k1-syscon.h | 253 ++++++++++++++++++\n 1 file changed, 253 insertions(+)\n create mode 100644 include/dt-bindings/clock/spacemit,k1-syscon.h", "diff": "diff --git a/include/dt-bindings/clock/spacemit,k1-syscon.h b/include/dt-bindings/clock/spacemit,k1-syscon.h\nnew file mode 100644\nindex 00000000000..c33da4ce73b\n--- /dev/null\n+++ b/include/dt-bindings/clock/spacemit,k1-syscon.h\n@@ -0,0 +1,253 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/*\n+ * Copyright (C) 2024-2025 Haylen Chu <heylenay@outlook.com>\n+ */\n+\n+#ifndef _DT_BINDINGS_SPACEMIT_CCU_H_\n+#define _DT_BINDINGS_SPACEMIT_CCU_H_\n+\n+/* APBS (PLL) clocks */\n+#define CLK_PLL1\t\t0\n+#define CLK_PLL2\t\t1\n+#define CLK_PLL3\t\t2\n+#define CLK_PLL1_D2\t\t3\n+#define CLK_PLL1_D3\t\t4\n+#define CLK_PLL1_D4\t\t5\n+#define CLK_PLL1_D5\t\t6\n+#define CLK_PLL1_D6\t\t7\n+#define CLK_PLL1_D7\t\t8\n+#define CLK_PLL1_D8\t\t9\n+#define CLK_PLL1_D11\t\t10\n+#define CLK_PLL1_D13\t\t11\n+#define CLK_PLL1_D23\t\t12\n+#define CLK_PLL1_D64\t\t13\n+#define CLK_PLL1_D10_AUD\t14\n+#define CLK_PLL1_D100_AUD\t15\n+#define CLK_PLL2_D1\t\t16\n+#define CLK_PLL2_D2\t\t17\n+#define CLK_PLL2_D3\t\t18\n+#define CLK_PLL2_D4\t\t19\n+#define CLK_PLL2_D5\t\t20\n+#define CLK_PLL2_D6\t\t21\n+#define CLK_PLL2_D7\t\t22\n+#define CLK_PLL2_D8\t\t23\n+#define CLK_PLL3_D1\t\t24\n+#define CLK_PLL3_D2\t\t25\n+#define CLK_PLL3_D3\t\t26\n+#define CLK_PLL3_D4\t\t27\n+#define CLK_PLL3_D5\t\t28\n+#define CLK_PLL3_D6\t\t29\n+#define CLK_PLL3_D7\t\t30\n+#define CLK_PLL3_D8\t\t31\n+#define CLK_PLL3_80\t\t32\n+#define CLK_PLL3_40\t\t33\n+#define CLK_PLL3_20\t\t34\n+\n+/* MPMU clocks */\n+#define CLK_PLL1_307P2\t\t0\n+#define CLK_PLL1_76P8\t\t1\n+#define CLK_PLL1_61P44\t\t2\n+#define CLK_PLL1_153P6\t\t3\n+#define CLK_PLL1_102P4\t\t4\n+#define CLK_PLL1_51P2\t\t5\n+#define CLK_PLL1_51P2_AP\t6\n+#define CLK_PLL1_57P6\t\t7\n+#define CLK_PLL1_25P6\t\t8\n+#define CLK_PLL1_12P8\t\t9\n+#define CLK_PLL1_12P8_WDT\t10\n+#define CLK_PLL1_6P4\t\t11\n+#define CLK_PLL1_3P2\t\t12\n+#define CLK_PLL1_1P6\t\t13\n+#define CLK_PLL1_0P8\t\t14\n+#define CLK_PLL1_409P6\t\t15\n+#define CLK_PLL1_204P8\t\t16\n+#define CLK_PLL1_491\t\t17\n+#define CLK_PLL1_245P76\t\t18\n+#define CLK_PLL1_614\t\t19\n+#define CLK_PLL1_47P26\t\t20\n+#define CLK_PLL1_31P5\t\t21\n+#define CLK_PLL1_819\t\t22\n+#define CLK_PLL1_1228\t\t23\n+#define CLK_SLOW_UART\t\t24\n+#define CLK_SLOW_UART1\t\t25\n+#define CLK_SLOW_UART2\t\t26\n+#define CLK_WDT\t\t\t27\n+#define CLK_RIPC\t\t28\n+#define CLK_I2S_SYSCLK\t\t29\n+#define CLK_I2S_BCLK\t\t30\n+#define CLK_APB\t\t\t31\n+#define CLK_WDT_BUS\t\t32\n+#define CLK_I2S_153P6\t\t33\n+#define CLK_I2S_153P6_BASE\t34\n+#define CLK_I2S_SYSCLK_SRC\t35\n+#define CLK_I2S_BCLK_FACTOR\t36\n+\n+/* APBC clocks */\n+#define CLK_UART0\t\t0\n+#define CLK_UART2\t\t1\n+#define CLK_UART3\t\t2\n+#define CLK_UART4\t\t3\n+#define CLK_UART5\t\t4\n+#define CLK_UART6\t\t5\n+#define CLK_UART7\t\t6\n+#define CLK_UART8\t\t7\n+#define CLK_UART9\t\t8\n+#define CLK_GPIO\t\t9\n+#define CLK_PWM0\t\t10\n+#define CLK_PWM1\t\t11\n+#define CLK_PWM2\t\t12\n+#define CLK_PWM3\t\t13\n+#define CLK_PWM4\t\t14\n+#define CLK_PWM5\t\t15\n+#define CLK_PWM6\t\t16\n+#define CLK_PWM7\t\t17\n+#define CLK_PWM8\t\t18\n+#define CLK_PWM9\t\t19\n+#define CLK_PWM10\t\t20\n+#define CLK_PWM11\t\t21\n+#define CLK_PWM12\t\t22\n+#define CLK_PWM13\t\t23\n+#define CLK_PWM14\t\t24\n+#define CLK_PWM15\t\t25\n+#define CLK_PWM16\t\t26\n+#define CLK_PWM17\t\t27\n+#define CLK_PWM18\t\t28\n+#define CLK_PWM19\t\t29\n+#define CLK_SSP3\t\t30\n+#define CLK_RTC\t\t\t31\n+#define CLK_TWSI0\t\t32\n+#define CLK_TWSI1\t\t33\n+#define CLK_TWSI2\t\t34\n+#define CLK_TWSI4\t\t35\n+#define CLK_TWSI5\t\t36\n+#define CLK_TWSI6\t\t37\n+#define CLK_TWSI7\t\t38\n+#define CLK_TWSI8\t\t39\n+#define CLK_TIMERS1\t\t40\n+#define CLK_TIMERS2\t\t41\n+#define CLK_AIB\t\t\t42\n+#define CLK_ONEWIRE\t\t43\n+#define CLK_SSPA0\t\t44\n+#define CLK_SSPA1\t\t45\n+#define CLK_DRO\t\t\t46\n+#define CLK_IR\t\t\t47\n+#define CLK_TSEN\t\t48\n+#define CLK_IPC_AP2AUD\t\t49\n+#define CLK_CAN0\t\t50\n+#define CLK_CAN0_BUS\t\t51\n+#define CLK_UART0_BUS\t\t52\n+#define CLK_UART2_BUS\t\t53\n+#define CLK_UART3_BUS\t\t54\n+#define CLK_UART4_BUS\t\t55\n+#define CLK_UART5_BUS\t\t56\n+#define CLK_UART6_BUS\t\t57\n+#define CLK_UART7_BUS\t\t58\n+#define CLK_UART8_BUS\t\t59\n+#define CLK_UART9_BUS\t\t60\n+#define CLK_GPIO_BUS\t\t61\n+#define CLK_PWM0_BUS\t\t62\n+#define CLK_PWM1_BUS\t\t63\n+#define CLK_PWM2_BUS\t\t64\n+#define CLK_PWM3_BUS\t\t65\n+#define CLK_PWM4_BUS\t\t66\n+#define CLK_PWM5_BUS\t\t67\n+#define CLK_PWM6_BUS\t\t68\n+#define CLK_PWM7_BUS\t\t69\n+#define CLK_PWM8_BUS\t\t70\n+#define CLK_PWM9_BUS\t\t71\n+#define CLK_PWM10_BUS\t\t72\n+#define CLK_PWM11_BUS\t\t73\n+#define CLK_PWM12_BUS\t\t74\n+#define CLK_PWM13_BUS\t\t75\n+#define CLK_PWM14_BUS\t\t76\n+#define CLK_PWM15_BUS\t\t77\n+#define CLK_PWM16_BUS\t\t78\n+#define CLK_PWM17_BUS\t\t79\n+#define CLK_PWM18_BUS\t\t80\n+#define CLK_PWM19_BUS\t\t81\n+#define CLK_SSP3_BUS\t\t82\n+#define CLK_RTC_BUS\t\t83\n+#define CLK_TWSI0_BUS\t\t84\n+#define CLK_TWSI1_BUS\t\t85\n+#define CLK_TWSI2_BUS\t\t86\n+#define CLK_TWSI4_BUS\t\t87\n+#define CLK_TWSI5_BUS\t\t88\n+#define CLK_TWSI6_BUS\t\t89\n+#define CLK_TWSI7_BUS\t\t90\n+#define CLK_TWSI8_BUS\t\t91\n+#define CLK_TIMERS1_BUS\t\t92\n+#define CLK_TIMERS2_BUS\t\t93\n+#define CLK_AIB_BUS\t\t94\n+#define CLK_ONEWIRE_BUS\t\t95\n+#define CLK_SSPA0_BUS\t\t96\n+#define CLK_SSPA1_BUS\t\t97\n+#define CLK_TSEN_BUS\t\t98\n+#define CLK_IPC_AP2AUD_BUS\t99\n+#define CLK_SSPA0_I2S_BCLK\t100\n+#define CLK_SSPA1_I2S_BCLK\t101\n+\n+/* APMU clocks */\n+#define CLK_CCI550\t\t0\n+#define CLK_CPU_C0_HI\t\t1\n+#define CLK_CPU_C0_CORE\t\t2\n+#define CLK_CPU_C0_ACE\t\t3\n+#define CLK_CPU_C0_TCM\t\t4\n+#define CLK_CPU_C1_HI\t\t5\n+#define CLK_CPU_C1_CORE\t\t6\n+#define CLK_CPU_C1_ACE\t\t7\n+#define CLK_CCIC_4X\t\t8\n+#define CLK_CCIC1PHY\t\t9\n+#define CLK_SDH_AXI\t\t10\n+#define CLK_SDH0\t\t11\n+#define CLK_SDH1\t\t12\n+#define CLK_SDH2\t\t13\n+#define CLK_USB_P1\t\t14\n+#define CLK_USB_AXI\t\t15\n+#define CLK_USB30\t\t16\n+#define CLK_QSPI\t\t17\n+#define CLK_QSPI_BUS\t\t18\n+#define CLK_DMA\t\t\t19\n+#define CLK_AES\t\t\t20\n+#define CLK_VPU\t\t\t21\n+#define CLK_GPU\t\t\t22\n+#define CLK_EMMC\t\t23\n+#define CLK_EMMC_X\t\t24\n+#define CLK_AUDIO\t\t25\n+#define CLK_HDMI\t\t26\n+#define CLK_PMUA_ACLK\t\t27\n+#define CLK_PCIE0_MASTER\t28\n+#define CLK_PCIE0_SLAVE\t\t29\n+#define CLK_PCIE0_DBI\t\t30\n+#define CLK_PCIE1_MASTER\t31\n+#define CLK_PCIE1_SLAVE\t\t32\n+#define CLK_PCIE1_DBI\t\t33\n+#define CLK_PCIE2_MASTER\t34\n+#define CLK_PCIE2_SLAVE\t\t35\n+#define CLK_PCIE2_DBI\t\t36\n+#define CLK_EMAC0_BUS\t\t37\n+#define CLK_EMAC0_PTP\t\t38\n+#define CLK_EMAC1_BUS\t\t39\n+#define CLK_EMAC1_PTP\t\t40\n+#define CLK_JPG\t\t\t41\n+#define CLK_CCIC2PHY\t\t42\n+#define CLK_CCIC3PHY\t\t43\n+#define CLK_CSI\t\t\t44\n+#define CLK_CAMM0\t\t45\n+#define CLK_CAMM1\t\t46\n+#define CLK_CAMM2\t\t47\n+#define CLK_ISP_CPP\t\t48\n+#define CLK_ISP_BUS\t\t49\n+#define CLK_ISP\t\t\t50\n+#define CLK_DPU_MCLK\t\t51\n+#define CLK_DPU_ESC\t\t52\n+#define CLK_DPU_BIT\t\t53\n+#define CLK_DPU_PXCLK\t\t54\n+#define CLK_DPU_HCLK\t\t55\n+#define CLK_DPU_SPI\t\t56\n+#define CLK_DPU_SPI_HBUS\t57\n+#define CLK_DPU_SPIBUS\t\t58\n+#define CLK_DPU_SPI_ACLK\t59\n+#define CLK_V2D\t\t\t60\n+#define CLK_EMMC_BUS\t\t61\n+\n+#endif /* _DT_BINDINGS_SPACEMIT_CCU_H_ */\n", "prefixes": [ "v3", "05/16" ] }