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{
    "id": 2216135,
    "url": "http://patchwork.ozlabs.org/api/patches/2216135/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325212628.1234082-2-chunn@nvidia.com/",
    "project": {
        "id": 21,
        "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api",
        "name": "Linux Tegra Development",
        "link_name": "linux-tegra",
        "list_id": "linux-tegra.vger.kernel.org",
        "list_email": "linux-tegra@vger.kernel.org",
        "web_url": null,
        "scm_url": null,
        "webscm_url": null,
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20260325212628.1234082-2-chunn@nvidia.com>",
    "list_archive_url": null,
    "date": "2026-03-25T21:26:25",
    "name": "[1/4] dt-bindings: tegra: Add Tegra238 clock and reset definitions",
    "commit_ref": null,
    "pull_url": null,
    "state": "new",
    "archived": false,
    "hash": "86841796c3b2f55e2a4619d60c3a05544a9d137b",
    "submitter": {
        "id": 92971,
        "url": "http://patchwork.ozlabs.org/api/people/92971/?format=api",
        "name": "Chun Ng",
        "email": "chunn@nvidia.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325212628.1234082-2-chunn@nvidia.com/mbox/",
    "series": [
        {
            "id": 497514,
            "url": "http://patchwork.ozlabs.org/api/series/497514/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497514",
            "date": "2026-03-25T21:26:26",
            "name": "arm64: tegra: add initial Tegra238 and E2426-1099+E2423-1099 support",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/497514/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/2216135/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/2216135/checks/",
    "tags": {},
    "related": [],
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        "From": "Chun Ng <chunn@nvidia.com>",
        "To": "<linux-tegra@vger.kernel.org>",
        "CC": "<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,\n\t<robh@kernel.org>, <krzk+dt@kernel.org>, <conor+dt@kernel.org>,\n\t<thierry.reding@gmail.com>, <jonathanh@nvidia.com>, <chunn@nvidia.com>,\n\t<ankitag@nvidia.com>",
        "Subject": "[PATCH 1/4] dt-bindings: tegra: Add Tegra238 clock and reset\n definitions",
        "Date": "Wed, 25 Mar 2026 21:26:25 +0000",
        "Message-ID": "<20260325212628.1234082-2-chunn@nvidia.com>",
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    "content": "Add device tree binding headers for Tegra238 that define the clock and\nreset resource IDs used by the BPMP firmware. The IDs are defined by\nhardware and are not software enumerations; 0 is reserved, so numbering\nstarts at 1. The reset header documents reserved ID ranges where no\nreset line is present.\n\nSigned-off-by: Chun Ng <chunn@nvidia.com>\n---\n include/dt-bindings/clock/nvidia,tegra238.h | 279 ++++++++++++++++++++\n include/dt-bindings/reset/nvidia,tegra238.h | 125 +++++++++\n 2 files changed, 404 insertions(+)\n create mode 100644 include/dt-bindings/clock/nvidia,tegra238.h\n create mode 100644 include/dt-bindings/reset/nvidia,tegra238.h",
    "diff": "diff --git a/include/dt-bindings/clock/nvidia,tegra238.h b/include/dt-bindings/clock/nvidia,tegra238.h\nnew file mode 100644\nindex 000000000000..eb1cb01ab20a\n--- /dev/null\n+++ b/include/dt-bindings/clock/nvidia,tegra238.h\n@@ -0,0 +1,279 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/* Copyright (c) 2021-2026, NVIDIA CORPORATION. All rights reserved. */\n+\n+#ifndef DT_BINDINGS_CLOCK_NVIDIA_TEGRA238_H\n+#define DT_BINDINGS_CLOCK_NVIDIA_TEGRA238_H\n+\n+#define TEGRA238_CLK_ACLK\t\t\t1\n+#define TEGRA238_CLK_ACTMON\t\t\t2\n+#define TEGRA238_CLK_ADSP\t\t\t3\n+#define TEGRA238_CLK_ADSPNEON\t\t\t4\n+#define TEGRA238_CLK_AHUB\t\t\t5\n+#define TEGRA238_CLK_AON_APB\t\t\t6\n+#define TEGRA238_CLK_AON_CPU_NIC\t\t7\n+#define TEGRA238_CLK_AON_I2C_SLOW\t\t8\n+#define TEGRA238_CLK_AON_NIC\t\t\t9\n+#define TEGRA238_CLK_AON_TOUCH\t\t\t10\n+#define TEGRA238_CLK_APB2APE\t\t\t11\n+#define TEGRA238_CLK_APE\t\t\t12\n+#define TEGRA238_CLK_AUD_MCLK\t\t\t13\n+#define TEGRA238_CLK_AXI_CBB\t\t\t14\n+#define TEGRA238_CLK_AZA_2XBIT\t\t\t15\n+#define TEGRA238_CLK_AZA_BIT\t\t\t16\n+#define TEGRA238_CLK_BPMP_CPU\t\t\t17\n+#define TEGRA238_CLK_BPMP_CPU_NIC\t\t18\n+#define TEGRA238_CLK_CLK_32K\t\t\t19\n+#define TEGRA238_CLK_CLK_M\t\t\t20\n+#define TEGRA238_CLK_CSITE\t\t\t21\n+#define TEGRA238_CLK_DBGAPB\t\t\t22\n+#define TEGRA238_CLK_DISP\t\t\t23\n+#define TEGRA238_CLK_DISPHUBPLL\t\t\t24\n+#define TEGRA238_CLK_DISPPLL\t\t\t25\n+#define TEGRA238_CLK_DISP_ROOT\t\t\t26\n+#define TEGRA238_CLK_DMIC1\t\t\t27\n+#define TEGRA238_CLK_DMIC3\t\t\t28\n+#define TEGRA238_CLK_DMIC4\t\t\t29\n+#define TEGRA238_CLK_DMIC5\t\t\t30\n+#define TEGRA238_CLK_DPAUX\t\t\t31\n+#define TEGRA238_CLK_DP_LINK_REF\t\t32\n+#define TEGRA238_CLK_DSC\t\t\t33\n+#define TEGRA238_CLK_DSIPLL_CLKOUTA\t\t34\n+#define TEGRA238_CLK_DSIPLL_CLKOUTPN\t\t35\n+#define TEGRA238_CLK_DSIPLL_VCO\t\t\t36\n+#define TEGRA238_CLK_DSI_CORE\t\t\t37\n+#define TEGRA238_CLK_DSI_LP\t\t\t38\n+#define TEGRA238_CLK_DSI_PAD_INPUT\t\t39\n+#define TEGRA238_CLK_DSI_PIXEL\t\t\t40\n+#define TEGRA238_CLK_DSPK1\t\t\t41\n+#define TEGRA238_CLK_DSPK2\t\t\t42\n+#define TEGRA238_CLK_EMC\t\t\t43\n+#define TEGRA238_CLK_EMCHUB\t\t\t44\n+#define TEGRA238_CLK_EMCSA_EMC\t\t\t45\n+#define TEGRA238_CLK_EMCSA_MC\t\t\t46\n+#define TEGRA238_CLK_EMCSA_MPLL\t\t\t47\n+#define TEGRA238_CLK_EMCSB_EMC\t\t\t48\n+#define TEGRA238_CLK_EMCSB_MC\t\t\t49\n+#define TEGRA238_CLK_EMCSB_MPLL\t\t\t50\n+#define TEGRA238_CLK_EXTPERIPH1\t\t\t51\n+#define TEGRA238_CLK_EXTPERIPH2\t\t\t52\n+#define TEGRA238_CLK_EXTPERIPH3\t\t\t53\n+#define TEGRA238_CLK_EXTPERIPH4\t\t\t54\n+#define TEGRA238_CLK_FDE\t\t\t55\n+#define TEGRA238_CLK_FR_SE\t\t\t56\n+#define TEGRA238_CLK_FR_SEU1\t\t\t57\n+#define TEGRA238_CLK_FUSE\t\t\t58\n+#define TEGRA238_CLK_FUSE_BURN\t\t\t59\n+#define TEGRA238_CLK_FUSE_SERIAL\t\t60\n+#define TEGRA238_CLK_GPC0CLK\t\t\t61\n+#define TEGRA238_CLK_GPU_PWR\t\t\t62\n+#define TEGRA238_CLK_HOST1X\t\t\t63\n+#define TEGRA238_CLK_HUB\t\t\t64\n+#define TEGRA238_CLK_HUB_ROOT\t\t\t65\n+#define TEGRA238_CLK_I2C1\t\t\t66\n+#define TEGRA238_CLK_I2C2\t\t\t67\n+#define TEGRA238_CLK_I2C3\t\t\t68\n+#define TEGRA238_CLK_I2C4\t\t\t69\n+#define TEGRA238_CLK_I2C5\t\t\t70\n+#define TEGRA238_CLK_I2C6\t\t\t71\n+#define TEGRA238_CLK_I2C7\t\t\t72\n+#define TEGRA238_CLK_I2C8\t\t\t73\n+#define TEGRA238_CLK_I2C9\t\t\t74\n+#define TEGRA238_CLK_I2C_SLOW\t\t\t75\n+#define TEGRA238_CLK_I2S1\t\t\t76\n+#define TEGRA238_CLK_I2S1_SYNC_INPUT\t\t77\n+#define TEGRA238_CLK_I2S2\t\t\t78\n+#define TEGRA238_CLK_I2S2_SYNC_INPUT\t\t79\n+#define TEGRA238_CLK_I2S3\t\t\t80\n+#define TEGRA238_CLK_I2S3_SYNC_INPUT\t\t81\n+#define TEGRA238_CLK_I2S4\t\t\t82\n+#define TEGRA238_CLK_I2S4_SYNC_INPUT\t\t83\n+#define TEGRA238_CLK_I2S5\t\t\t84\n+#define TEGRA238_CLK_I2S5_SYNC_INPUT\t\t85\n+#define TEGRA238_CLK_I2S6\t\t\t86\n+#define TEGRA238_CLK_I2S6_SYNC_INPUT\t\t87\n+#define TEGRA238_CLK_JTAG_INTFC_PRE_CG\t\t88\n+#define TEGRA238_CLK_LA\t\t\t\t89\n+#define TEGRA238_CLK_LINKA_SYM_CLKOUT\t\t90\n+#define TEGRA238_CLK_LINKF_SYM_CLKOUT\t\t91\n+#define TEGRA238_CLK_MAUD\t\t\t92\n+#define TEGRA238_CLK_MCHUB\t\t\t93\n+#define TEGRA238_CLK_MIPI_CAL\t\t\t94\n+#define TEGRA238_CLK_MPHY_CORE_PLL_FIXED\t95\n+#define TEGRA238_CLK_MPHY_FORCE_LS_MODE\t\t96\n+#define TEGRA238_CLK_MPHY_L0_RX_ANA\t\t97\n+#define TEGRA238_CLK_MPHY_L0_RX_HS_SYMB_DIV\t98\n+#define TEGRA238_CLK_MPHY_L0_RX_LS_BIT\t\t99\n+#define TEGRA238_CLK_MPHY_L0_RX_LS_BIT_DIV\t100\n+#define TEGRA238_CLK_MPHY_L0_RX_LS_SYMB_DIV\t101\n+#define TEGRA238_CLK_MPHY_L0_RX_MUX_SYMB_DIV\t102\n+#define TEGRA238_CLK_MPHY_L0_RX_SYMB\t\t103\n+#define TEGRA238_CLK_MPHY_L0_TX_2X_SYMB\t\t104\n+#define TEGRA238_CLK_MPHY_L0_TX_HS_SYMB_DIV\t105\n+#define TEGRA238_CLK_MPHY_L0_TX_LS_3XBIT\t106\n+#define TEGRA238_CLK_MPHY_L0_TX_LS_3XBIT_DIV\t107\n+#define TEGRA238_CLK_MPHY_L0_TX_LS_SYMB_DIV\t108\n+#define TEGRA238_CLK_MPHY_L0_TX_MUX_SYMB_DIV\t109\n+#define TEGRA238_CLK_MPHY_L0_TX_PRE_SYMB\t110\n+#define TEGRA238_CLK_MPHY_L0_TX_SYMB\t\t111\n+#define TEGRA238_CLK_MPHY_L1_RX_ANA\t\t112\n+#define TEGRA238_CLK_MPHY_TX_1MHZ_REF\t\t113\n+#define TEGRA238_CLK_MSS_ENCRYPT\t\t114\n+#define TEGRA238_CLK_NAFLL_BPMP\t\t\t115\n+#define TEGRA238_CLK_NAFLL_CLUSTER0_CORE\t116\n+#define TEGRA238_CLK_NAFLL_CLUSTER0_DSU\t\t117\n+#define TEGRA238_CLK_NAFLL_FDE\t\t\t118\n+#define TEGRA238_CLK_NAFLL_GPC0\t\t\t119\n+#define TEGRA238_CLK_NAFLL_NVDEC\t\t120\n+#define TEGRA238_CLK_NAFLL_NVENC\t\t121\n+#define TEGRA238_CLK_NAFLL_OFA\t\t\t122\n+#define TEGRA238_CLK_NAFLL_SE\t\t\t123\n+#define TEGRA238_CLK_NAFLL_SEU1\t\t\t124\n+#define TEGRA238_CLK_NAFLL_TSEC\t\t\t125\n+#define TEGRA238_CLK_NAFLL_VIC\t\t\t126\n+#define TEGRA238_CLK_NVDEC\t\t\t127\n+#define TEGRA238_CLK_NVDISPLAY_P0\t\t128\n+#define TEGRA238_CLK_NVDISPLAY_P1\t\t129\n+#define TEGRA238_CLK_NVENC\t\t\t130\n+#define TEGRA238_CLK_OFA\t\t\t131\n+#define TEGRA238_CLK_OSC\t\t\t132\n+#define TEGRA238_CLK_PEX0_C0_CORE\t\t133\n+#define TEGRA238_CLK_PEX0_C1_CORE\t\t134\n+#define TEGRA238_CLK_PEX0_C2_CORE\t\t135\n+#define TEGRA238_CLK_PEX0_C3_CORE\t\t136\n+#define TEGRA238_CLK_PEX_SATA_USB_RX_BYP\t137\n+#define TEGRA238_CLK_PEX_USB_PAD_PLL0_MGMT\t138\n+#define TEGRA238_CLK_PEX_USB_PAD_PLL1_MGMT\t139\n+#define TEGRA238_CLK_PEX_USB_PAD_PLL2_MGMT\t140\n+#define TEGRA238_CLK_PEX_USB_PAD_PLL3_MGMT\t141\n+#define TEGRA238_CLK_PLLA\t\t\t142\n+#define TEGRA238_CLK_PLLA1\t\t\t143\n+#define TEGRA238_CLK_PLLA1_OUT1\t\t\t144\n+#define TEGRA238_CLK_PLLAON\t\t\t145\n+#define TEGRA238_CLK_PLLA_DISP\t\t\t146\n+#define TEGRA238_CLK_PLLA_DISPHUB\t\t147\n+#define TEGRA238_CLK_PLLA_DIV2\t\t\t148\n+#define TEGRA238_CLK_PLLA_OUT0\t\t\t149\n+#define TEGRA238_CLK_PLLC\t\t\t150\n+#define TEGRA238_CLK_PLLC2\t\t\t151\n+#define TEGRA238_CLK_PLLC4\t\t\t152\n+#define TEGRA238_CLK_PLLC4_MUXED\t\t153\n+#define TEGRA238_CLK_PLLC4_OUT1\t\t\t154\n+#define TEGRA238_CLK_PLLC4_OUT2\t\t\t155\n+#define TEGRA238_CLK_PLLC4_VCO_DIV2\t\t156\n+#define TEGRA238_CLK_PLLE\t\t\t157\n+#define TEGRA238_CLK_PLLE_HPS\t\t\t158\n+#define TEGRA238_CLK_PLLHUB\t\t\t159\n+#define TEGRA238_CLK_PLLP\t\t\t160\n+#define TEGRA238_CLK_PLLP_AUDIO\t\t\t161\n+#define TEGRA238_CLK_PLLP_DIV17\t\t\t162\n+#define TEGRA238_CLK_PLLP_OUT0\t\t\t163\n+#define TEGRA238_CLK_PLLP_OUT_JTAG\t\t164\n+#define TEGRA238_CLK_PLLREFE_VCOOUT\t\t165\n+#define TEGRA238_CLK_PLLREFE_VCOOUT_GATED\t166\n+#define TEGRA238_CLK_PPC\t\t\t167\n+#define TEGRA238_CLK_PRE_SF0\t\t\t168\n+#define TEGRA238_CLK_PRE_SOR0\t\t\t169\n+#define TEGRA238_CLK_PRE_SOR0_REF\t\t170\n+#define TEGRA238_CLK_PRE_SOR1\t\t\t171\n+#define TEGRA238_CLK_PRE_SOR1_REF\t\t172\n+#define TEGRA238_CLK_PWM1\t\t\t173\n+#define TEGRA238_CLK_PWM2\t\t\t174\n+#define TEGRA238_CLK_PWM3\t\t\t175\n+#define TEGRA238_CLK_PWM4\t\t\t176\n+#define TEGRA238_CLK_PWM5\t\t\t177\n+#define TEGRA238_CLK_PWM6\t\t\t178\n+#define TEGRA238_CLK_PWM7\t\t\t179\n+#define TEGRA238_CLK_PWM8\t\t\t180\n+#define TEGRA238_CLK_QSPI0_2X_PM\t\t181\n+#define TEGRA238_CLK_QSPI0_PM\t\t\t182\n+#define TEGRA238_CLK_RG0\t\t\t183\n+#define TEGRA238_CLK_RG1\t\t\t184\n+#define TEGRA238_CLK_SDMMC1\t\t\t185\n+#define TEGRA238_CLK_SDMMC4\t\t\t186\n+#define TEGRA238_CLK_SDMMC4_AXICIF\t\t187\n+#define TEGRA238_CLK_SDMMC_LEGACY_TM\t\t188\n+#define TEGRA238_CLK_SE\t\t\t\t189\n+#define TEGRA238_CLK_SEU1\t\t\t190\n+#define TEGRA238_CLK_SF0\t\t\t191\n+#define TEGRA238_CLK_SF0_POSTMUX\t\t192\n+#define TEGRA238_CLK_SF1\t\t\t193\n+#define TEGRA238_CLK_SF1_POSTMUX\t\t194\n+#define TEGRA238_CLK_SOC_THERM\t\t\t195\n+#define TEGRA238_CLK_SOR0\t\t\t196\n+#define TEGRA238_CLK_SOR0_PAD_CLKOUT\t\t197\n+#define TEGRA238_CLK_SOR0_PLL_REF\t\t198\n+#define TEGRA238_CLK_SOR0_REF\t\t\t199\n+#define TEGRA238_CLK_SOR1\t\t\t200\n+#define TEGRA238_CLK_SOR1_PAD_CLKOUT\t\t201\n+#define TEGRA238_CLK_SOR1_PLL_REF\t\t202\n+#define TEGRA238_CLK_SOR1_REF\t\t\t203\n+#define TEGRA238_CLK_SOR_SAFE\t\t\t204\n+#define TEGRA238_CLK_SPI1\t\t\t205\n+#define TEGRA238_CLK_SPI2\t\t\t206\n+#define TEGRA238_CLK_SPI3\t\t\t207\n+#define TEGRA238_CLK_SPI4\t\t\t208\n+#define TEGRA238_CLK_SPI5\t\t\t209\n+#define TEGRA238_CLK_SPPLL0_CLKOUTA\t\t210\n+#define TEGRA238_CLK_SPPLL0_CLKOUTB\t\t211\n+#define TEGRA238_CLK_SPPLL0_CLKOUTPN\t\t212\n+#define TEGRA238_CLK_SPPLL0_DIV10\t\t213\n+#define TEGRA238_CLK_SPPLL0_DIV25\t\t214\n+#define TEGRA238_CLK_SPPLL0_DIV27PN\t\t215\n+#define TEGRA238_CLK_SPPLL0_VCO\t\t\t216\n+#define TEGRA238_CLK_SPPLL1_CLKOUTPN\t\t217\n+#define TEGRA238_CLK_SPPLL1_DIV27PN\t\t218\n+#define TEGRA238_CLK_SPPLL1_VCO\t\t\t219\n+#define TEGRA238_CLK_SYNC_DMIC1\t\t\t220\n+#define TEGRA238_CLK_SYNC_DMIC3\t\t\t221\n+#define TEGRA238_CLK_SYNC_DMIC4\t\t\t222\n+#define TEGRA238_CLK_SYNC_DSPK1\t\t\t223\n+#define TEGRA238_CLK_SYNC_DSPK2\t\t\t224\n+#define TEGRA238_CLK_SYNC_I2S1\t\t\t225\n+#define TEGRA238_CLK_SYNC_I2S2\t\t\t226\n+#define TEGRA238_CLK_SYNC_I2S3\t\t\t227\n+#define TEGRA238_CLK_SYNC_I2S4\t\t\t228\n+#define TEGRA238_CLK_SYNC_I2S5\t\t\t229\n+#define TEGRA238_CLK_SYNC_I2S6\t\t\t230\n+#define TEGRA238_CLK_TACH0\t\t\t231\n+#define TEGRA238_CLK_TACH1\t\t\t232\n+#define TEGRA238_CLK_TSC\t\t\t233\n+#define TEGRA238_CLK_TSC_REF\t\t\t234\n+#define TEGRA238_CLK_TSEC\t\t\t235\n+#define TEGRA238_CLK_TSEC_PKA\t\t\t236\n+#define TEGRA238_CLK_TSENSE\t\t\t237\n+#define TEGRA238_CLK_UARTA\t\t\t238\n+#define TEGRA238_CLK_UARTB\t\t\t239\n+#define TEGRA238_CLK_UARTC\t\t\t240\n+#define TEGRA238_CLK_UARTD\t\t\t241\n+#define TEGRA238_CLK_UARTE\t\t\t242\n+#define TEGRA238_CLK_UARTF\t\t\t243\n+#define TEGRA238_CLK_UARTG\t\t\t244\n+#define TEGRA238_CLK_UARTH\t\t\t245\n+#define TEGRA238_CLK_UART_FST_MIPI_CAL\t\t246\n+#define TEGRA238_CLK_UFSDEV_REF\t\t\t247\n+#define TEGRA238_CLK_UFSHC\t\t\t248\n+#define TEGRA238_CLK_UPHY_PLL3\t\t\t249\n+#define TEGRA238_CLK_USB2_TRK\t\t\t250\n+#define TEGRA238_CLK_UTMIPLL_CLKOUT48\t\t251\n+#define TEGRA238_CLK_UTMIPLL_CLKOUT480\t\t252\n+#define TEGRA238_CLK_UTMIP_PLL\t\t\t253\n+#define TEGRA238_CLK_VIC\t\t\t254\n+#define TEGRA238_CLK_VPLL0\t\t\t255\n+#define TEGRA238_CLK_VPLL0_REF\t\t\t256\n+#define TEGRA238_CLK_VPLL1\t\t\t257\n+#define TEGRA238_CLK_XUSB_CORE_DEV\t\t258\n+#define TEGRA238_CLK_XUSB_CORE_HOST\t\t259\n+#define TEGRA238_CLK_XUSB_CORE_MUX\t\t260\n+#define TEGRA238_CLK_XUSB_CORE_SS\t\t261\n+#define TEGRA238_CLK_XUSB_FALCON\t\t262\n+#define TEGRA238_CLK_XUSB_FALCON_HOST\t\t263\n+#define TEGRA238_CLK_XUSB_FALCON_SS\t\t264\n+#define TEGRA238_CLK_XUSB_FS\t\t\t265\n+#define TEGRA238_CLK_XUSB_FS_DEV\t\t266\n+#define TEGRA238_CLK_XUSB_FS_HOST\t\t267\n+#define TEGRA238_CLK_XUSB_HS_HSICP\t\t268\n+#define TEGRA238_CLK_XUSB_SS\t\t\t269\n+#define TEGRA238_CLK_XUSB_SS_DEV\t\t270\n+#define TEGRA238_CLK_XUSB_SS_SUPERSPEED\t\t271\n+\n+#endif /* DT_BINDINGS_CLOCK_NVIDIA_TEGRA238_H */\ndiff --git a/include/dt-bindings/reset/nvidia,tegra238.h b/include/dt-bindings/reset/nvidia,tegra238.h\nnew file mode 100644\nindex 000000000000..bf1eb27f1203\n--- /dev/null\n+++ b/include/dt-bindings/reset/nvidia,tegra238.h\n@@ -0,0 +1,125 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+/* Copyright (c) 2021-2026, NVIDIA CORPORATION. All rights reserved. */\n+\n+#ifndef DT_BINDINGS_RESET_NVIDIA_TEGRA238_H\n+#define DT_BINDINGS_RESET_NVIDIA_TEGRA238_H\n+\n+#define TEGRA238_RESET_ACTMON\t\t\t1\n+#define TEGRA238_RESET_ADSP_ALL\t\t\t2\n+#define TEGRA238_RESET_DSI_CORE\t\t\t3\n+#define TEGRA238_RESET_XUSB_DEV\t\t\t4\n+#define TEGRA238_RESET_XUSB_HOST\t\t5\n+#define TEGRA238_RESET_XUSB_SS\t\t\t6\n+/* RESERVED 7 */\n+#define TEGRA238_RESET_DPAUX\t\t\t8\n+#define TEGRA238_RESET_OFA\t\t\t9\n+/* RESERVED 10:15 */\n+#define TEGRA238_RESET_NVDISPLAY\t\t16\n+/* RESERVED 17 */\n+#define TEGRA238_RESET_GPCDMA\t\t\t18\n+#define TEGRA238_RESET_GPU\t\t\t19\n+#define TEGRA238_RESET_HDA\t\t\t20\n+#define TEGRA238_RESET_HDACODEC\t\t\t21\n+/* RESERVED 22:23 */\n+#define TEGRA238_RESET_I2C1\t\t\t24\n+/* RESERVED 25:28 */\n+#define TEGRA238_RESET_I2C2\t\t\t29\n+#define TEGRA238_RESET_I2C3\t\t\t30\n+#define TEGRA238_RESET_I2C4\t\t\t31\n+#define TEGRA238_RESET_I2C6\t\t\t32\n+#define TEGRA238_RESET_I2C7\t\t\t33\n+#define TEGRA238_RESET_I2C8\t\t\t34\n+#define TEGRA238_RESET_I2C9\t\t\t35\n+#define TEGRA238_RESET_ISP\t\t\t36\n+#define TEGRA238_RESET_MIPI_CAL\t\t\t37\n+#define TEGRA238_RESET_MPHY_CLK_CTL\t\t38\n+#define TEGRA238_RESET_MPHY_L0_RX\t\t39\n+#define TEGRA238_RESET_MPHY_L0_TX\t\t40\n+#define TEGRA238_RESET_MPHY_L1_RX\t\t41\n+#define TEGRA238_RESET_MPHY_L1_TX\t\t42\n+/* RESERVED 43 */\n+#define TEGRA238_RESET_NVDEC\t\t\t44\n+/* RESERVED 45:58 */\n+#define TEGRA238_RESET_NVENC\t\t\t59\n+/* RESERVED 60:63 */\n+#define TEGRA238_RESET_LA\t\t\t64\n+#define TEGRA238_RESET_HWPM\t\t\t65\n+/* RESERVED 66 */\n+#define TEGRA238_RESET_CEC\t\t\t67\n+#define TEGRA238_RESET_PWM1\t\t\t68\n+#define TEGRA238_RESET_PWM2\t\t\t69\n+#define TEGRA238_RESET_PWM3\t\t\t70\n+#define TEGRA238_RESET_PWM4\t\t\t71\n+#define TEGRA238_RESET_PWM5\t\t\t72\n+#define TEGRA238_RESET_PWM6\t\t\t73\n+#define TEGRA238_RESET_PWM7\t\t\t74\n+#define TEGRA238_RESET_PWM8\t\t\t75\n+#define TEGRA238_RESET_QSPI0\t\t\t76\n+/* RESERVED 77:81 */\n+#define TEGRA238_RESET_SDMMC1\t\t\t82\n+#define TEGRA238_RESET_RSVD_83\t\t\t83\n+#define TEGRA238_RESET_RSVD_84\t\t\t84\n+#define TEGRA238_RESET_SDMMC4\t\t\t85\n+/* RESERVED 86:90 */\n+#define TEGRA238_RESET_SPI1\t\t\t91\n+#define TEGRA238_RESET_SPI2\t\t\t92\n+#define TEGRA238_RESET_SPI3\t\t\t93\n+#define TEGRA238_RESET_SPI4\t\t\t94\n+#define TEGRA238_RESET_TACH0\t\t\t95\n+#define TEGRA238_RESET_TACH1\t\t\t96\n+#define TEGRA238_RESET_SPI5\t\t\t97\n+#define TEGRA238_RESET_TSEC\t\t\t98\n+/* RESERVED 99 */\n+#define TEGRA238_RESET_UARTA\t\t\t100\n+#define TEGRA238_RESET_UARTB\t\t\t101\n+#define TEGRA238_RESET_UARTC\t\t\t102\n+#define TEGRA238_RESET_UARTD\t\t\t103\n+#define TEGRA238_RESET_UARTE\t\t\t104\n+#define TEGRA238_RESET_UARTF\t\t\t105\n+/* RESERVED 106 */\n+#define TEGRA238_RESET_UARTH\t\t\t107\n+#define TEGRA238_RESET_UFSHC\t\t\t108\n+#define TEGRA238_RESET_UFSHC_AXI_M\t\t109\n+#define TEGRA238_RESET_UFSHC_LP_SEQ\t\t110\n+#define TEGRA238_RESET_RSVD_111\t\t\t111\n+/* RESERVED 112 */\n+#define TEGRA238_RESET_VIC\t\t\t113\n+#define TEGRA238_RESET_XUSB_PADCTL\t\t114\n+/* RESERVED 115 */\n+#define TEGRA238_RESET_PEX0_CORE_0\t\t116\n+#define TEGRA238_RESET_PEX0_CORE_1\t\t117\n+#define TEGRA238_RESET_PEX0_CORE_2\t\t118\n+#define TEGRA238_RESET_PEX0_CORE_3\t\t119\n+/* RESERVED 120 */\n+#define TEGRA238_RESET_PEX0_CORE_0_APB\t\t121\n+#define TEGRA238_RESET_PEX0_CORE_1_APB\t\t122\n+#define TEGRA238_RESET_PEX0_CORE_2_APB\t\t123\n+#define TEGRA238_RESET_PEX0_CORE_3_APB\t\t124\n+/* RESERVED 125 */\n+#define TEGRA238_RESET_PEX0_COMMON_APB\t\t126\n+#define TEGRA238_RESET_RSVD_127\t\t\t127\n+/* RESERVED 128:143 */\n+#define TEGRA238_RESET_DMIC5\t\t\t144\n+#define TEGRA238_RESET_APE\t\t\t145\n+#define TEGRA238_RESET_PEX_USB_UPHY\t\t146\n+#define TEGRA238_RESET_PEX_USB_UPHY_L0\t\t147\n+#define TEGRA238_RESET_PEX_USB_UPHY_L1\t\t148\n+#define TEGRA238_RESET_PEX_USB_UPHY_L2\t\t149\n+#define TEGRA238_RESET_PEX_USB_UPHY_L3\t\t150\n+#define TEGRA238_RESET_PEX_USB_UPHY_L4\t\t151\n+#define TEGRA238_RESET_PEX_USB_UPHY_L5\t\t152\n+#define TEGRA238_RESET_PEX_USB_UPHY_L6\t\t153\n+#define TEGRA238_RESET_PEX_USB_UPHY_L7\t\t154\n+#define TEGRA238_RESET_PEX_USB_UPHY_PLL0\t159\n+#define TEGRA238_RESET_PEX_USB_UPHY_PLL1\t160\n+#define TEGRA238_RESET_PEX_USB_UPHY_PLL2\t161\n+#define TEGRA238_RESET_PEX_USB_UPHY_PLL3\t162\n+/* RESERVED 163:173 */\n+#define TEGRA238_RESET_FDE\t\t\t174\n+#define TEGRA238_RESET_ADSP_CORE0\t\t175\n+#define TEGRA238_RESET_ADSP_CORE1\t\t176\n+#define TEGRA238_RESET_ADSP_CORE2\t\t177\n+#define TEGRA238_RESET_ADSP_CORE3\t\t178\n+#define TEGRA238_RESET_APE_TKE\t\t\t179\n+\n+#endif /* DT_BINDINGS_RESET_NVIDIA_TEGRA238_H */\n",
    "prefixes": [
        "1/4"
    ]
}