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GET /api/patches/2216134/?format=api
{ "id": 2216134, "url": "http://patchwork.ozlabs.org/api/patches/2216134/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325212628.1234082-5-chunn@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325212628.1234082-5-chunn@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T21:26:28", "name": "[4/4] arm64: tegra: add e2426-1099+e2423-1099 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "593634a8c306e1d7635ae48e83f62035154f9fdd", "submitter": { "id": 92971, "url": "http://patchwork.ozlabs.org/api/people/92971/?format=api", "name": "Chun Ng", "email": "chunn@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325212628.1234082-5-chunn@nvidia.com/mbox/", "series": [ { "id": 497514, "url": "http://patchwork.ozlabs.org/api/series/497514/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497514", "date": "2026-03-25T21:26:26", "name": "arm64: tegra: add initial Tegra238 and E2426-1099+E2423-1099 support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497514/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216134/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216134/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13258-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=IUjYuJDv;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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The device-tree is not yet bootable and further enablement\nwill be added in follow-up patches.\n\nSigned-off-by: Chun Ng <chunn@nvidia.com>\n---\n arch/arm64/boot/dts/nvidia/Makefile | 2 +\n .../nvidia/tegra238-e2426-1099+e2423-1099.dts | 16 ++\n arch/arm64/boot/dts/nvidia/tegra238.dtsi | 190 ++++++++++++++++++\n 3 files changed, 208 insertions(+)\n create mode 100644 arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts\n create mode 100644 arch/arm64/boot/dts/nvidia/tegra238.dtsi", "diff": "diff --git a/arch/arm64/boot/dts/nvidia/Makefile b/arch/arm64/boot/dts/nvidia/Makefile\nindex b139cbd14442..a5357809e222 100644\n--- a/arch/arm64/boot/dts/nvidia/Makefile\n+++ b/arch/arm64/boot/dts/nvidia/Makefile\n@@ -13,6 +13,7 @@ DTC_FLAGS_tegra234-p3737-0000+p3701-0000 := -@\n DTC_FLAGS_tegra234-p3740-0002+p3701-0008 := -@\n DTC_FLAGS_tegra234-p3768-0000+p3767-0000 := -@\n DTC_FLAGS_tegra234-p3768-0000+p3767-0005 := -@\n+DTC_FLAGS_tegra238-e2426-1099+e2423-1099 := -@\n DTC_FLAGS_tegra264-p3971-0089+p3834-0008 := -@\n \n dtb-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra132-norrin.dtb\n@@ -34,4 +35,5 @@ dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3737-0000+p3701-0008.dtb\n dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3740-0002+p3701-0008.dtb\n dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0000.dtb\n dtb-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra234-p3768-0000+p3767-0005.dtb\n+dtb-$(CONFIG_ARCH_TEGRA_238_SOC) += tegra238-e2426-1099+e2423-1099.dtb\n dtb-$(CONFIG_ARCH_TEGRA_264_SOC) += tegra264-p3971-0089+p3834-0008.dtb\ndiff --git a/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts b/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts\nnew file mode 100644\nindex 000000000000..d69ea2114e23\n--- /dev/null\n+++ b/arch/arm64/boot/dts/nvidia/tegra238-e2426-1099+e2423-1099.dts\n@@ -0,0 +1,16 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+\n+/dts-v1/;\n+\n+#include \"tegra238.dtsi\"\n+\n+/ {\n+\tmodel = \"NVIDIA Tegra238 E2426-1099+E2423-1099\";\n+\tcompatible = \"nvidia,e2426-1099+e2423-1099\", \"nvidia,tegra238\";\n+\n+\tbus@0 {\n+\t\tuarta: serial@3100000 {\n+\t\t\tstatus = \"okay\";\n+\t\t};\n+\t};\n+};\ndiff --git a/arch/arm64/boot/dts/nvidia/tegra238.dtsi b/arch/arm64/boot/dts/nvidia/tegra238.dtsi\nnew file mode 100644\nindex 000000000000..0570c3b20e62\n--- /dev/null\n+++ b/arch/arm64/boot/dts/nvidia/tegra238.dtsi\n@@ -0,0 +1,190 @@\n+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */\n+\n+#include <dt-bindings/clock/nvidia,tegra238.h>\n+#include <dt-bindings/interrupt-controller/arm-gic.h>\n+#include <dt-bindings/mailbox/tegra186-hsp.h>\n+#include <dt-bindings/reset/nvidia,tegra238.h>\n+\n+/ {\n+\tcompatible = \"nvidia,tegra238\";\n+\tinterrupt-parent = <&gic>;\n+\t#address-cells = <2>;\n+\t#size-cells = <2>;\n+\n+\tbus@0 {\n+\t\tcompatible = \"simple-bus\";\n+\n+\t\t#address-cells = <2>;\n+\t\t#size-cells = <2>;\n+\t\tranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>;\n+\n+\t\tuarta: serial@3100000 {\n+\t\t\tcompatible = \"arm,pl011\", \"arm,primecell\";\n+\t\t\treg = <0x0 0x3100000 0x0 0x10000>;\n+\t\t\tinterrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tclocks = <&bpmp TEGRA238_CLK_UARTA>,\n+\t\t\t\t <&bpmp TEGRA238_CLK_PLLP_OUT0>;\n+\t\t\tclock-names = \"uartclk\", \"apb_pclk\";\n+\t\t\tassigned-clocks = <&bpmp TEGRA238_CLK_UARTA>;\n+\t\t\tassigned-clock-parents = <&bpmp TEGRA238_CLK_PLLP_OUT0>;\n+\t\t\tresets = <&bpmp TEGRA238_RESET_UARTA>;\n+\t\t\tarm,primecell-periphid = <0x00051011>;\n+\t\t\tstatus = \"disabled\";\n+\t\t};\n+\n+\t\tfuse@3810000 {\n+\t\t\tcompatible = \"nvidia,tegra234-efuse\";\n+\t\t\treg = <0x0 0x03810000 0x0 0x19000>;\n+\t\t\tclocks = <&bpmp TEGRA238_CLK_FUSE>;\n+\t\t\tclock-names = \"fuse\";\n+\t\t};\n+\n+\t\thsp_top0: tegra-hsp@3c00000 {\n+\t\t\tcompatible = \"nvidia,tegra234-hsp\", \"nvidia,tegra194-hsp\";\n+\t\t\treg = <0x0 0x03c00000 0x0 0x000a0000>;\n+\t\t\tinterrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>,\n+\t\t\t\t <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"doorbell\", \"shared0\";\n+\t\t\t#mbox-cells = <2>;\n+\t\t};\n+\n+\t\thsp_top1: tegra-hsp@3d00000 {\n+\t\t\tcompatible = \"nvidia,tegra186-hsp\";\n+\t\t\treg = <0x0 0x03d00000 0x0 0x000a0000>;\n+\t\t\tinterrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"shared0\";\n+\t\t\t#mbox-cells = <2>;\n+\t\t};\n+\n+\t\taon_hsp: tegra-hsp@c150000 {\n+\t\t\tcompatible = \"nvidia,tegra186-hsp\";\n+\t\t\treg = <0x0 0x0c150000 0x0 0x00090000>;\n+\t\t\tinterrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;\n+\t\t\tinterrupt-names = \"shared1\";\n+\t\t};\n+\n+\t\tgic: interrupt-controller@f400000 {\n+\t\t\tcompatible = \"arm,gic-v3\";\n+\t\t\t#interrupt-cells = <3>;\n+\t\t\t#address-cells = <0>;\n+\t\t\t#redistributor-regions = <1>;\n+\t\t\tinterrupt-controller;\n+\t\t\treg = <0x0 0x0f400000 0x0 0x00010000\t/* GICD */\n+\t\t\t 0x0 0x0f440000 0x0 0x00200000>;\t/* GICR CPU 0-15 */\n+\t\t};\n+\n+\t\tsram@40000000 {\n+\t\t\tcompatible = \"nvidia,tegra234-sysram\", \"mmio-sram\";\n+\t\t\treg = <0x0 0x40000000 0x0 0x72000>;\n+\t\t\tranges = <0x0 0x0 0x40000000 0x72000>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\t\t\tno-memory-wc;\n+\n+\t\t\tcpu_bpmp_tx: sram@70000 {\n+\t\t\t\treg = <0x70000 0x1000>;\n+\t\t\t\tlabel = \"cpu-bpmp-tx\";\n+\t\t\t\tpool;\n+\t\t\t};\n+\n+\t\t\tcpu_bpmp_rx: sram@71000 {\n+\t\t\t\treg = <0x71000 0x1000>;\n+\t\t\t\tlabel = \"cpu-bpmp-rx\";\n+\t\t\t\tpool;\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tbpmp: bpmp {\n+\t\tcompatible = \"nvidia,tegra234-bpmp\", \"nvidia,tegra186-bpmp\";\n+\t\tmboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB TEGRA_HSP_DB_MASTER_BPMP>;\n+\t\tshmem = <&cpu_bpmp_tx &cpu_bpmp_rx>;\n+\t\t#clock-cells = <1>;\n+\t\t#reset-cells = <1>;\n+\t\t#power-domain-cells = <1>;\n+\n+\t\tbpmp_i2c: i2c {\n+\t\t\tcompatible = \"nvidia,tegra186-bpmp-i2c\";\n+\t\t\tnvidia,bpmp-bus-id = <5>;\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <0>;\n+\t\t};\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu0_0: cpu@0 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x000>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu0_1: cpu@1 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x100>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu0_2: cpu@2 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x200>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu0_3: cpu@3 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x300>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu0_4: cpu@4 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x400>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu0_5: cpu@5 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x500>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu0_6: cpu@6 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x600>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\n+\t\tcpu0_7: cpu@7 {\n+\t\t\tcompatible = \"arm,armv8\";\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\treg = <0x700>;\n+\n+\t\t\tenable-method = \"psci\";\n+\t\t};\n+\t};\n+\n+\ttimer {\n+\t\tcompatible = \"arm,armv8-timer\";\n+\t\tinterrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,\n+\t\t\t <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;\n+\t};\n+};\n", "prefixes": [ "4/4" ] }