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GET /api/patches/2216094/?format=api
{ "id": 2216094, "url": "http://patchwork.ozlabs.org/api/patches/2216094/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-11-jonathanh@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325192601.239554-11-jonathanh@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T19:26:00", "name": "[10/10] soc/tegra: pmc: Add IO pads for Tegra264", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "b022db560ffa5063626358c6ecdc03103ee40f5b", "submitter": { "id": 66273, "url": "http://patchwork.ozlabs.org/api/people/66273/?format=api", "name": "Jon Hunter", "email": "jonathanh@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-11-jonathanh@nvidia.com/mbox/", "series": [ { "id": 497504, "url": "http://patchwork.ozlabs.org/api/series/497504/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497504", "date": "2026-03-25T19:25:50", "name": "soc/tegra: pmc: Fixes and updates for Tegra264", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497504/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216094/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216094/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13251-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=FmBI7erZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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pr=C", "From": "Jon Hunter <jonathanh@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>", "CC": "<linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com>", "Subject": "[PATCH 10/10] soc/tegra: pmc: Add IO pads for Tegra264", "Date": "Wed, 25 Mar 2026 19:26:00 +0000", "Message-ID": "<20260325192601.239554-11-jonathanh@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260325192601.239554-1-jonathanh@nvidia.com>", "References": "<20260325192601.239554-1-jonathanh@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB51:EE_|MW6PR12MB8949:EE_", "X-MS-Office365-Filtering-Correlation-Id": "8519ed5e-5034-4929-ed6e-08de8aa478e2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|376014|82310400026|1800799024|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\td26bmSVSmAEJyX12dD/re90tcMpf2ZgZLW81CqxD77HPjk64oo/rHDh3aAPYwnKnjj2MtWrES8WQymINbbw1AFfCu8ftC62t66FeGEGpwgyqdYuCOvGc9eQppKPBLikHoHpT+9bzOET1zVBuNdeyd/yS3oLvLe5Wm7sbC+ms3ErH3ITf74wzB5Q4iFeTCPNpGfnHkzDchcwUG//oLeKsq6t7IdZ3wkJEPTrRm+1RPoULqIZJU1V4oC9KLf/U27j6OznhStVnIgTYvqlW/aivrn9WEUywkvJfwmr25aKP4wLz2SfB35wFfY/28tOK4bHUEEp4R8H6iVYJZK+2jcl2GFpPgIZFIAyRM3V6A+BBhz6mDhlDXeBKaD+vaEvwJH2jgtpVz+z83RUaHGJqvJfvVbFR7vpfqeQV47jtxyMuoQEpZsRdCa1knvR/UNnID9+wZThKhtuZ9VhpbdnSG7yowAfn/skHHZHH1mu55V7tvrOATyQVmMqP3+FeujlrcoTdE6Dq9xfB7HU+JSG7mu9WXYDr6hw27dROgcZrnfAEp6xqzvT6wq8AA0bbrRuOptAN1en2AMzoWbFHJJxIIN3qqoe8PFD+yDLTDi+55GL6viWplEy4pdlpPeM/NZLMALccckubR6xykhmWsUjXGAkQwe8Bi5qTDweuYkgsRScg+9zcExR/0yIOPxLIrLfUJ3VPo16B6gxLG3R3wxrEqvXnubVEv5riWcqcdafxTKPWWMW9HY/UyoP2/VpXuZcG5y/S9QW3087CTiNL6aoBufbRuw==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(82310400026)(1800799024)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t3l3bw00WtwqkDMimA5IEW7r5Ox7ytz8zbSFSV/77W6QKLN/gBXF8W9PClPxDJCuzh//kKPc0PH70kJ4xKNsfU8u+AXs5VrSBN2LxHbnEtwaLRVhFSJnPXFR/qKmXYUExGSWUp6vr/pcTkM7nQvcm21YtJxNWLEmsJD/fQSVJe1foeesUXZWXRaIG70NSXEdxy8DPk+34KX/oTLcKvMw4CGSd+pETYnEx++9BMwm0fE9h4j70DmgErEKUVVgyI5wBDOYfeqkxSXVdGxlcafwqV0tjV/vk9OXitzNm45W6fKVGv9HWYAOHGkiDCKCS86geUotfdYQzSjcjcTWhdvtYTLYgdDRRCw3g6mlbzo3Yx/EKCGILuSwlUCyct3MmFJEjaI5BbGC0c8111BplKWqii2nJAaVQENxfofFzmY9uC/wGLyrpKYBH52xrBq5JhKdL", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 19:26:53.8648\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 8519ed5e-5034-4929-ed6e-08de8aa478e2", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL6PEPF0001AB51.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW6PR12MB8949" }, "content": "Populate the IO pads and pins for Tegra264. Tegra264 has internal 1.8V\nand 0.6V regulators that must be enabled when selecting the 1.8V mode\nfor the sdmmc1-hv IO pad. To support this a new 'ena_1v8' member is\nadded to the 'tegra_io_pad_vctrl' structure to populate the bits that\nneed to be set to enable these internal regulators. Although this is\nenabling 1.8V (bit 1) and 0.6V (bit 2) regulators, it is simply called\n'ena_1v8' because these are both enabled for 1.8V operation. Note that\nthese internal regulators are disabled when not using 1.8V mode.\n\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\n---\n drivers/soc/tegra/pmc.c | 66 +++++++++++++++++++++++++++++++++++++++--\n 1 file changed, 64 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex 6f0808faf4b5..eca56119b381 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -201,6 +201,9 @@\n #define TEGRA_SMC_PMC_READ\t0xaa\n #define TEGRA_SMC_PMC_WRITE\t0xbb\n \n+/* Tegra264 and later */\n+#define PMC_IMPL_SDMMC1_HV_PADCTL_0\t0x41004\n+\n struct pmc_clk {\n \tstruct clk_hw hw;\n \tstruct tegra_pmc *pmc;\n@@ -301,6 +304,7 @@ struct tegra_io_pad_vctrl {\n \tenum tegra_io_pad id;\n \tunsigned int offset;\n \tunsigned int ena_3v3;\n+\tunsigned int ena_1v8;\n };\n \n struct tegra_pmc_regs {\n@@ -1931,11 +1935,18 @@ static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,\n \n \tvalue = tegra_pmc_readl(pmc, pad->offset);\n \n-\tif (voltage == TEGRA_IO_PAD_VOLTAGE_1V8)\n+\tif (voltage == TEGRA_IO_PAD_VOLTAGE_1V8) {\n \t\tvalue &= ~BIT(pad->ena_3v3);\n-\telse\n+\n+\t\tif (pad->ena_1v8)\n+\t\t\tvalue |= pad->ena_1v8;\n+\t} else {\n \t\tvalue |= BIT(pad->ena_3v3);\n \n+\t\tif (pad->ena_1v8)\n+\t\t\tvalue &= ~pad->ena_1v8;\n+\t}\n+\n \ttegra_pmc_writel(pmc, value, pad->offset);\n \n \tmutex_unlock(&pmc->powergates_lock);\n@@ -3724,6 +3735,7 @@ static const u8 tegra124_cpu_powergates[] = {\n \t\t.id\t\t= (_id),\t\t\t\t\\\n \t\t.offset\t\t= (_offset),\t\t\t\t\\\n \t\t.ena_3v3\t= (_ena_3v3),\t\t\t\t\\\n+\t\t.ena_1v8\t= 0,\t\t\t\t\t\\\n \t})\n \n #define TEGRA_IO_PIN_DESC(_id, _name)\t\\\n@@ -4583,6 +4595,50 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = {\n \t.has_single_mmio_aperture = false,\n };\n \n+#define TEGRA264_IO_PAD_VCTRL(_id, _offset, _ena_3v3, _ena_1v8)\t\t\\\n+\t((struct tegra_io_pad_vctrl) {\t\t\t\t\t\\\n+\t\t.id\t\t= (_id),\t\t\t\t\\\n+\t\t.offset\t\t= (_offset),\t\t\t\t\\\n+\t\t.ena_3v3\t= (_ena_3v3),\t\t\t\t\\\n+\t\t.ena_1v8\t= (_ena_1v8),\t\t\t\t\\\n+\t})\n+\n+static const struct tegra_io_pad_soc tegra264_io_pads[] = {\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIA, 0, 0x41020, 0x41024, \"csia\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIB, 1, 0x41020, 0x41024, \"csib\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_HDMI_DP0, 0, 0x41050, 0x41054, \"hdmi-dp0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIC, 2, 0x41020, 0x41024, \"csic\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSID, 3, 0x41020, 0x41024, \"csid\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIE, 4, 0x41020, 0x41024, \"csie\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIF, 5, 0x41020, 0x41024, \"csif\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_UFS, 4, 0x41040, 0x41044, \"ufs0\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_EDP, 0, 0x41028, 0x4102c, \"edp\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1, 0, 0x41090, 0x41094, \"sdmmc1\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_SDMMC1_HV, UINT_MAX, UINT_MAX, UINT_MAX, \"sdmmc1-hv\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIG, 6, 0x41020, 0x41024, \"csig\"),\n+\tTEGRA_IO_PAD(TEGRA_IO_PAD_CSIH, 7, 0x41020, 0x41024, \"csih\"),\n+};\n+\n+static const struct tegra_io_pad_vctrl tegra264_io_pad_vctrls[] = {\n+\tTEGRA264_IO_PAD_VCTRL(TEGRA_IO_PAD_SDMMC1_HV, PMC_IMPL_SDMMC1_HV_PADCTL_0, 0, 0x6),\n+};\n+\n+static const struct pinctrl_pin_desc tegra264_pin_descs[] = {\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIA, \"csia\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIB, \"csib\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_HDMI_DP0, \"hdmi-dp0\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIC, \"csic\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSID, \"csid\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIE, \"csie\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIF, \"csif\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_UFS, \"ufs0\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_EDP, \"edp\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1, \"sdmmc1\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_SDMMC1_HV, \"sdmmc1-hv\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIG, \"csig\"),\n+\tTEGRA_IO_PIN_DESC(TEGRA_IO_PAD_CSIH, \"csih\"),\n+};\n+\n static const struct tegra_pmc_regs tegra264_pmc_regs = {\n \t.scratch0 = 0x684,\n \t.rst_status = 0x4,\n@@ -4705,6 +4761,12 @@ static const struct tegra_wake_event tegra264_wake_events[] = {\n \n static const struct tegra_pmc_soc tegra264_pmc_soc = {\n \t.has_io_pad_wren = false,\n+\t.num_io_pads = ARRAY_SIZE(tegra264_io_pads),\n+\t.io_pads = tegra264_io_pads,\n+\t.num_io_pad_vctrls = ARRAY_SIZE(tegra264_io_pad_vctrls),\n+\t.io_pad_vctrls = tegra264_io_pad_vctrls,\n+\t.num_pin_descs = ARRAY_SIZE(tegra264_pin_descs),\n+\t.pin_descs = tegra264_pin_descs,\n \t.regs = &tegra264_pmc_regs,\n \t.init = tegra186_pmc_init,\n \t.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,\n", "prefixes": [ "10/10" ] }