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GET /api/patches/2216093/?format=api
{ "id": 2216093, "url": "http://patchwork.ozlabs.org/api/patches/2216093/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-10-jonathanh@nvidia.com/", "project": { "id": 21, "url": "http://patchwork.ozlabs.org/api/projects/21/?format=api", "name": "Linux Tegra Development", "link_name": "linux-tegra", "list_id": "linux-tegra.vger.kernel.org", "list_email": "linux-tegra@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260325192601.239554-10-jonathanh@nvidia.com>", "list_archive_url": null, "date": "2026-03-25T19:25:59", "name": "[09/10] soc/tegra: pmc: Rename has_impl_33v_pwr flag", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "9b4b0a165435092b28b98c630e67db4cc63e81d7", "submitter": { "id": 66273, "url": "http://patchwork.ozlabs.org/api/people/66273/?format=api", "name": "Jon Hunter", "email": "jonathanh@nvidia.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-tegra/patch/20260325192601.239554-10-jonathanh@nvidia.com/mbox/", "series": [ { "id": 497504, "url": "http://patchwork.ozlabs.org/api/series/497504/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-tegra/list/?series=497504", "date": "2026-03-25T19:25:50", "name": "soc/tegra: pmc: Fixes and updates for Tegra264", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/497504/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2216093/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2216093/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-tegra+bounces-13252-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-tegra@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=Nvidia.com header.i=@Nvidia.com header.a=rsa-sha256\n header.s=selector2 header.b=W1Z/fBf6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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pr=C", "From": "Jon Hunter <jonathanh@nvidia.com>", "To": "Thierry Reding <thierry.reding@gmail.com>", "CC": "<linux-tegra@vger.kernel.org>, Jon Hunter <jonathanh@nvidia.com>", "Subject": "[PATCH 09/10] soc/tegra: pmc: Rename has_impl_33v_pwr flag", "Date": "Wed, 25 Mar 2026 19:25:59 +0000", "Message-ID": "<20260325192601.239554-10-jonathanh@nvidia.com>", "X-Mailer": "git-send-email 2.43.0", "In-Reply-To": "<20260325192601.239554-1-jonathanh@nvidia.com>", "References": "<20260325192601.239554-1-jonathanh@nvidia.com>", "Precedence": "bulk", "X-Mailing-List": "linux-tegra@vger.kernel.org", "List-Id": "<linux-tegra.vger.kernel.org>", "List-Subscribe": "<mailto:linux-tegra+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-tegra+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "X-NVConfidentiality": "public", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-NV-OnPremToCloud": "ExternallySecured", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "BL6PEPF0001AB4F:EE_|LV2PR12MB5943:EE_", "X-MS-Office365-Filtering-Correlation-Id": "65fe81c6-11fc-4b92-aa6a-08de8aa477e3", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|376014|36860700016|82310400026|1800799024|22082099003|56012099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\to7Yxnn5CJshQbtle/xfpwcBZl/v+NcIUkcOHBQyKul2ZH0YlAnMJxfzYtmZE0BqUosbpS+wVUkRXAvENfMFVApMDO+HtYe/uOS8XaRl8H4s1BbQ3jX0Iid5fHvZ87o7ZvYCwRd/QMd2UGV4MSSnLtVLwkuGYwOvlKlbKek0X9qgMx5n0/kyGImYLXR9VwkDkGzuqKDS5J+gwkXJpwW9USaw0Koq+Hl52K53HI/a/3vNPXk5bZcTvxzH6AkZ8324HbBrFhwvVIH1EFDZFtt8hnceQ9zjLmIdocjzVKFAe/BrPh1dAkThpqoSH2uymAIoRhoHhEnajOEEvgHmVqdSlHvfS6erRh03/yaIXpaP9Z+KLAedwWyxbqkkdrqvtZ93MGRVPK+bmefasPwhaUyKfUgRDI/UNSXKdTdE9Cb+sbgZxM9c/6qVR9SJF3IsIaefNAIGOQP3zfmzttkw5+6nk5NGYQSuF7PRqO1KtG/vPfoCgItJ1zpSuyFAOUUhla0e+mN/JJnIg7kMWmC1RQZgpwFyp/rpjYcvEl1epPmcThFBcAkQtPNg9LAneOao0rU0ID7PGgdLJb5+7eldlXK966mOBgAYHrk7zsjRphy2U9z+gVZjksLNhDV0Y/0CnsFwRoert40mZaPobA0+k0eWLe3XmJPmDX5FgPT3nZzFzqJauvWSIhMrZAWxVdhyzF8DATMBHN8/6/fcF924Bk4GQfA/F6f559vGjrHrIgsyuCwXkExgDkpUnXyGpJ9fN3kK49EbBUA0zWa+Sp2OF9jlAdA==", "X-Forefront-Antispam-Report": "\n\tCIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(376014)(36860700016)(82310400026)(1800799024)(22082099003)(56012099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tORD8Ye/uNkgrVnO1sJSdrThIrIqgZOIkyF/MqKAATAbdHSglidYLBCR0yUf/NYmRL10bRzjDLGgm+LgyBvY3HqPw9NAS+NBKKwGxe2akKLi8EP+Z1Fww+tyqzIQugfzIhssev6T9aAJMmqLH9R/+PFErzuqtsn3nyzNNpFEZXlHSBYRJ7sOrFnb5+aUVCkeqVIjBVD8W6qTIq7OPfm1pEiVS00yCLcUwZz0GAa3vCt653wRLPjQWDnTxHNGmmO82jPQPGapchWk6YUPELDFGgFzUH026eWhxQz/VH0x+4ejVZ3WEB3Om6f7frhzUD8ZUnPbcBvBtuciJ6wPEYC5gHQuXaqpUI3ZweEOALNuh+TxD95Y/Xv2Rjpti2VwrAYTdaMZte561VWEN04S7L+5kRdy9UfQd6PwI0bKEszaUSxhcLqvN/m20qEz+HRltcXTU", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Mar 2026 19:26:52.1800\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 65fe81c6-11fc-4b92-aa6a-08de8aa477e3", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tBL6PEPF0001AB4F.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "LV2PR12MB5943" }, "content": "The flag 'has_impl_33v_pwr' is now only used to determine if we need to\nset the write-enable bit before we can set the bit to select if 3.3V IO\nis used or not. Therefore, rename the flag to 'has_io_pad_wren' to\nindicate that the SoC supports the write-enable register.\n\nSigned-off-by: Jon Hunter <jonathanh@nvidia.com>\n---\n drivers/soc/tegra/pmc.c | 22 +++++++++++-----------\n 1 file changed, 11 insertions(+), 11 deletions(-)", "diff": "diff --git a/drivers/soc/tegra/pmc.c b/drivers/soc/tegra/pmc.c\nindex 3dcc679baffa..6f0808faf4b5 100644\n--- a/drivers/soc/tegra/pmc.c\n+++ b/drivers/soc/tegra/pmc.c\n@@ -372,7 +372,7 @@ struct tegra_pmc_soc {\n \tbool has_tsense_reset;\n \tbool has_gpu_clamps;\n \tbool needs_mbist_war;\n-\tbool has_impl_33v_pwr;\n+\tbool has_io_pad_wren;\n \tbool maybe_tz_only;\n \n \tconst struct tegra_io_pad_soc *io_pads;\n@@ -1922,7 +1922,7 @@ static int tegra_io_pad_set_voltage(struct tegra_pmc *pmc, enum tegra_io_pad id,\n \n \tmutex_lock(&pmc->powergates_lock);\n \n-\tif (!pmc->soc->has_impl_33v_pwr) {\n+\tif (pmc->soc->has_io_pad_wren) {\n \t\t/* write-enable PMC_PWR_DET_VALUE[pad->ena_3v3] */\n \t\tvalue = tegra_pmc_readl(pmc, PMC_PWR_DET);\n \t\tvalue |= BIT(pad->ena_3v3);\n@@ -3536,7 +3536,7 @@ static const struct tegra_pmc_soc tegra20_pmc_soc = {\n \t.has_tsense_reset = false,\n \t.has_gpu_clamps = false,\n \t.needs_mbist_war = false,\n-\t.has_impl_33v_pwr = false,\n+\t.has_io_pad_wren = true,\n \t.maybe_tz_only = false,\n \t.num_io_pads = 0,\n \t.io_pads = NULL,\n@@ -3598,7 +3598,7 @@ static const struct tegra_pmc_soc tegra30_pmc_soc = {\n \t.has_tsense_reset = true,\n \t.has_gpu_clamps = false,\n \t.needs_mbist_war = false,\n-\t.has_impl_33v_pwr = false,\n+\t.has_io_pad_wren = true,\n \t.maybe_tz_only = false,\n \t.num_io_pads = 0,\n \t.io_pads = NULL,\n@@ -3656,7 +3656,7 @@ static const struct tegra_pmc_soc tegra114_pmc_soc = {\n \t.has_tsense_reset = true,\n \t.has_gpu_clamps = false,\n \t.needs_mbist_war = false,\n-\t.has_impl_33v_pwr = false,\n+\t.has_io_pad_wren = true,\n \t.maybe_tz_only = false,\n \t.num_io_pads = 0,\n \t.io_pads = NULL,\n@@ -3807,7 +3807,7 @@ static const struct tegra_pmc_soc tegra124_pmc_soc = {\n \t.has_tsense_reset = true,\n \t.has_gpu_clamps = true,\n \t.needs_mbist_war = false,\n-\t.has_impl_33v_pwr = false,\n+\t.has_io_pad_wren = true,\n \t.maybe_tz_only = false,\n \t.num_io_pads = ARRAY_SIZE(tegra124_io_pads),\n \t.io_pads = tegra124_io_pads,\n@@ -3981,7 +3981,7 @@ static const struct tegra_pmc_soc tegra210_pmc_soc = {\n \t.has_tsense_reset = true,\n \t.has_gpu_clamps = true,\n \t.needs_mbist_war = true,\n-\t.has_impl_33v_pwr = false,\n+\t.has_io_pad_wren = true,\n \t.maybe_tz_only = true,\n \t.num_io_pads = ARRAY_SIZE(tegra210_io_pads),\n \t.io_pads = tegra210_io_pads,\n@@ -4195,7 +4195,7 @@ static const struct tegra_pmc_soc tegra186_pmc_soc = {\n \t.has_tsense_reset = false,\n \t.has_gpu_clamps = false,\n \t.needs_mbist_war = false,\n-\t.has_impl_33v_pwr = true,\n+\t.has_io_pad_wren = false,\n \t.maybe_tz_only = false,\n \t.num_io_pads = ARRAY_SIZE(tegra186_io_pads),\n \t.io_pads = tegra186_io_pads,\n@@ -4399,7 +4399,7 @@ static const struct tegra_pmc_soc tegra194_pmc_soc = {\n \t.has_tsense_reset = false,\n \t.has_gpu_clamps = false,\n \t.needs_mbist_war = false,\n-\t.has_impl_33v_pwr = true,\n+\t.has_io_pad_wren = false,\n \t.maybe_tz_only = false,\n \t.num_io_pads = ARRAY_SIZE(tegra194_io_pads),\n \t.io_pads = tegra194_io_pads,\n@@ -4555,7 +4555,7 @@ static const struct tegra_pmc_soc tegra234_pmc_soc = {\n \t.has_tsense_reset = false,\n \t.has_gpu_clamps = false,\n \t.needs_mbist_war = false,\n-\t.has_impl_33v_pwr = true,\n+\t.has_io_pad_wren = false,\n \t.maybe_tz_only = false,\n \t.num_io_pads = ARRAY_SIZE(tegra234_io_pads),\n \t.io_pads = tegra234_io_pads,\n@@ -4704,7 +4704,7 @@ static const struct tegra_wake_event tegra264_wake_events[] = {\n };\n \n static const struct tegra_pmc_soc tegra264_pmc_soc = {\n-\t.has_impl_33v_pwr = true,\n+\t.has_io_pad_wren = false,\n \t.regs = &tegra264_pmc_regs,\n \t.init = tegra186_pmc_init,\n \t.setup_irq_polarity = tegra186_pmc_setup_irq_polarity,\n", "prefixes": [ "09/10" ] }